From d57b62466731e7902f08c20b5c309186200428e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Duval?= Date: Tue, 8 Oct 2013 21:42:40 +0200 Subject: [PATCH] Update FreeBSD network drivers with the 9.2 release --- .../drivers/network/3com/dev/xl/if_xl.c | 6 +- .../drivers/network/ar81xx/dev/ale/if_ale.c | 12 +- .../network/atheros813x/dev/alc/if_alc.c | 24 +- .../network/attansic_l1/dev/age/if_age.c | 214 +- .../network/attansic_l1/dev/age/if_agevar.h | 6 + .../network/attansic_l2/dev/ae/if_ae.c | 50 +- .../network/broadcom440x/dev/bfe/if_bfe.c | 4 +- .../network/broadcom570x/dev/bce/if_bcereg.h | 45 +- .../network/broadcom570x/dev/bge/if_bge.c | 1127 ++++++++--- .../network/broadcom570x/dev/bge/if_bgereg.h | 170 +- .../network/broadcom570x/dev/mii/brgphy.c | 46 +- .../drivers/network/dec21xxx/dev/dc/if_dc.c | 10 +- .../drivers/network/dec21xxx/dev/de/if_de.c | 8 +- .../drivers/network/ipro100/dev/fxp/if_fxp.c | 40 +- .../drivers/network/ipro1000/dev/e1000/README | 2 +- .../network/ipro1000/dev/e1000/e1000_82571.c | 348 ++-- .../network/ipro1000/dev/e1000/e1000_82575.c | 288 +-- .../network/ipro1000/dev/e1000/e1000_82575.h | 5 +- .../network/ipro1000/dev/e1000/e1000_api.c | 47 +- .../network/ipro1000/dev/e1000/e1000_api.h | 8 +- .../ipro1000/dev/e1000/e1000_defines.h | 601 +----- .../network/ipro1000/dev/e1000/e1000_hw.h | 32 +- .../network/ipro1000/dev/e1000/e1000_i210.c | 140 +- .../network/ipro1000/dev/e1000/e1000_i210.h | 18 +- .../ipro1000/dev/e1000/e1000_ich8lan.c | 1800 +++++++++++------ .../ipro1000/dev/e1000/e1000_ich8lan.h | 137 +- .../network/ipro1000/dev/e1000/e1000_mac.c | 324 ++- .../network/ipro1000/dev/e1000/e1000_mac.h | 8 +- .../network/ipro1000/dev/e1000/e1000_manage.c | 27 +- .../network/ipro1000/dev/e1000/e1000_nvm.c | 352 +++- .../network/ipro1000/dev/e1000/e1000_nvm.h | 17 +- .../network/ipro1000/dev/e1000/e1000_osdep.h | 5 +- .../network/ipro1000/dev/e1000/e1000_phy.c | 256 ++- .../network/ipro1000/dev/e1000/e1000_phy.h | 16 +- .../network/ipro1000/dev/e1000/e1000_regs.h | 39 +- .../network/ipro1000/dev/e1000/if_em.c | 7 +- .../network/ipro1000/dev/e1000/if_em.h | 1 + .../network/ipro1000/dev/e1000/if_igb.c | 373 ++-- .../network/ipro1000/dev/e1000/if_igb.h | 4 +- .../network/ipro1000/dev/e1000/if_lem.c | 226 +-- .../network/ipro1000/dev/e1000/if_lem.h | 1 + .../network/jmicron2x0/dev/jme/if_jme.c | 8 +- .../network/marvell_yukon/dev/msk/if_msk.c | 41 +- .../drivers/network/nforce/dev/nfe/if_nfe.c | 6 +- .../drivers/network/pcnet/dev/le/lance.c | 6 +- .../drivers/network/rdc/dev/vte/if_vte.c | 10 +- .../drivers/network/rtl8139/dev/mii/rlphy.c | 4 +- .../drivers/network/rtl81xx/dev/mii/rgephy.c | 11 +- .../network/rtl81xx/dev/mii/rgephyreg.h | 11 + .../drivers/network/rtl81xx/dev/re/if_re.c | 49 +- .../drivers/network/syskonnect/dev/sk/if_sk.c | 28 +- .../network/syskonnect/dev/sk/if_skreg.h | 4 +- .../drivers/network/via_rhine/dev/vr/if_vr.c | 14 +- .../drivers/network/vt612x/dev/vge/if_vge.c | 8 +- .../network/wlan/aironetwifi/dev/an/if_an.c | 11 +- .../wlan/aironetwifi/dev/an/if_an_pci.c | 14 - .../wlan/atheroswifi/dev/ath/ah_osdep.c | 5 +- .../dev/ath/ath_hal/ah_eeprom_v4k.c | 12 +- .../dev/ath/ath_hal/ar5212/ar5212.h | 2 +- .../dev/ath/ath_hal/ar5416/ar5416_ani.c | 5 - .../network/wlan/atheroswifi/dev/ath/if_ath.c | 2 +- .../wlan/atheroswifi/dev/ath/if_ath_tx.c | 2 +- .../wlan/broadcom43xx/dev/bwi/if_bwi.c | 10 +- .../wlan/iprowifi2100/dev/ipw/if_ipw.c | 6 +- .../wlan/iprowifi3945/dev/wpi/if_wpi.c | 8 +- .../wlan/iprowifi4965/dev/iwn/if_iwn.c | 15 +- .../wlan/marvell88w8335/dev/malo/if_malo.c | 6 +- .../marvell88w8335/dev/malo/if_malo_pci.c | 2 +- .../wlan/marvell88w8363/dev/mwl/if_mwl.c | 8 +- .../wlan/marvell88w8363/dev/mwl/if_mwl_pci.c | 33 +- .../wlan/marvell88w8363/dev/mwl/mwlhal.c | 3 +- .../network/wlan/ralinkwifi/dev/ral/rt2560.c | 6 +- .../network/wlan/ralinkwifi/dev/ral/rt2661.c | 6 +- .../network/wlan/ralinkwifi/dev/ral/rt2860.c | 8 +- .../network/wlan/wavelanwifi/dev/wi/if_wi.c | 7 +- .../wlan/wavelanwifi/dev/wi/if_wi_pci.c | 12 +- .../freebsd_network/compat/dev/pci/pcireg.h | 333 ++- 77 files changed, 4460 insertions(+), 3100 deletions(-) diff --git a/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c index 989c5a731e..ccabc08399 100644 --- a/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c +++ b/src/add-ons/kernel/drivers/network/3com/dev/xl/if_xl.c @@ -161,7 +161,7 @@ MODULE_DEPEND(xl, miibus, 1, 1, 1); /* * Various supported device vendors/types and their names. */ -static const struct xl_type const xl_devs[] = { +static const struct xl_type xl_devs[] = { { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, "3Com 3c900-TPO Etherlink XL" }, { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, @@ -1770,7 +1770,7 @@ xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) XL_LOCK_ASSERT(sc); - m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m_new == NULL) return (ENOBUFS); @@ -2379,7 +2379,7 @@ xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) * and would waste cycles. */ if (error) { - m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); + m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); if (m_new == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c index 78c0b4eeaa..b5eb59756c 100644 --- a/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c +++ b/src/add-ons/kernel/drivers/network/ar81xx/dev/ale/if_ale.c @@ -95,7 +95,7 @@ static const struct ale_dev { uint16_t ale_vendorid; uint16_t ale_deviceid; const char *ale_name; -} const ale_devs[] = { +} ale_devs[] = { { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, }; @@ -551,7 +551,7 @@ ale_attach(device_t dev) if (msix_disable == 0 || msi_disable == 0) { if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && pci_alloc_msix(dev, &msixc) == 0) { - if (msic == ALE_MSIX_MESSAGES) { + if (msixc == ALE_MSIX_MESSAGES) { device_printf(dev, "Using %d MSIX messages.\n", msixc); sc->ale_flags |= ALE_FLAG_MSIX; @@ -1640,7 +1640,7 @@ ale_encap(struct ale_softc *sc, struct mbuf **m_head) if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { @@ -1657,7 +1657,7 @@ ale_encap(struct ale_softc *sc, struct mbuf **m_head) if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && (mtod(m, intptr_t) & 3) != 0) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { *m_head = NULL; return (ENOBUFS); @@ -1742,7 +1742,7 @@ ale_encap(struct ale_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -2932,7 +2932,7 @@ ale_stop_mac(struct ale_softc *sc) reg = CSR_READ_4(sc, ALE_MAC_CFG); if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { - reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; + reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); CSR_WRITE_4(sc, ALE_MAC_CFG, reg); } diff --git a/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alc.c b/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alc.c index c73075c6a8..732220fc66 100644 --- a/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alc.c +++ b/src/add-ons/kernel/drivers/network/atheros813x/dev/alc/if_alc.c @@ -683,7 +683,7 @@ alc_aspm(struct alc_softc *sc, int media) if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == (ALC_FLAG_APS | ALC_FLAG_PCIE)) linkcfg = CSR_READ_2(sc, sc->alc_expcap + - PCIR_EXPRESS_LINK_CTL); + PCIER_LINK_CTL); else linkcfg = 0; pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; @@ -698,7 +698,7 @@ alc_aspm(struct alc_softc *sc, int media) if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) linkcfg |= 0x80; - CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, + CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, linkcfg); pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | PM_CFG_HOTRST); @@ -798,10 +798,10 @@ alc_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; - burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); + burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); sc->alc_dma_rd_burst = - (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; - sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; + (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; + sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; if (bootverbose) { device_printf(dev, "Read request size : %u bytes.\n", alc_dma_burst[sc->alc_dma_rd_burst]); @@ -831,9 +831,9 @@ alc_attach(device_t dev) CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); } /* Disable ASPM L0S and L1. */ - cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { - ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); + cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { + ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); if ((ctl & 0x08) != 0) sc->alc_rcb = DMA_CFG_RCB_128; if (bootverbose) @@ -2047,7 +2047,7 @@ alc_encap(struct alc_softc *sc, struct mbuf **m_head) if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { @@ -2125,7 +2125,7 @@ alc_encap(struct alc_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -2803,7 +2803,7 @@ alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; @@ -2923,7 +2923,7 @@ alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) * header from the mbuf chain. This can save lots of CPU * cycles for jumbo frame. */ - MGETHDR(n, M_DONTWAIT, MT_DATA); + MGETHDR(n, M_NOWAIT, MT_DATA); if (n == NULL) { ifp->if_iqdrops++; m_freem(m); diff --git a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_age.c b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_age.c index f4287b0dd6..3850024bb2 100644 --- a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_age.c +++ b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_age.c @@ -142,6 +142,9 @@ static int age_init_rx_ring(struct age_softc *); static void age_init_rr_ring(struct age_softc *); static void age_init_cmb_block(struct age_softc *); static void age_init_smb_block(struct age_softc *); +#ifndef __NO_STRICT_ALIGNMENT +static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *); +#endif static int age_newbuf(struct age_softc *, struct age_rxdesc *); static void age_rxvlan(struct age_softc *); static void age_rxfilter(struct age_softc *); @@ -1133,7 +1136,7 @@ again: /* Create tag for Rx buffers. */ error = bus_dma_tag_create( sc->age_cdata.age_buffer_tag, /* parent */ - 1, 0, /* alignment, boundary */ + AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ @@ -1499,7 +1502,7 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) struct tcphdr *tcp; bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; bus_dmamap_t map; - uint32_t cflags, ip_off, poff, vtag; + uint32_t cflags, hdrlen, ip_off, poff, vtag; int error, i, nsegs, prod, si; AGE_LOCK_ASSERT(sc); @@ -1525,7 +1528,7 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); /* Release original mbufs. */ m_freem(*m_head); if (m == NULL) { @@ -1566,8 +1569,12 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) *m_head = NULL; return (ENOBUFS); } - ip = (struct ip *)(mtod(m, char *) + ip_off); tcp = (struct tcphdr *)(mtod(m, char *) + poff); + m = m_pullup(m, poff + (tcp->th_off << 2)); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } /* * L1 requires IP/TCP header size and offset as * well as TCP pseudo checksum which complicates @@ -1582,14 +1589,11 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) * Reset IP checksum and recompute TCP pseudo * checksum as NDIS specification said. */ + ip = (struct ip *)(mtod(m, char *) + ip_off); + tcp = (struct tcphdr *)(mtod(m, char *) + poff); ip->ip_sum = 0; - if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) - tcp->th_sum = in_pseudo(ip->ip_src.s_addr, - ip->ip_dst.s_addr, - htons((tcp->th_off << 2) + IPPROTO_TCP)); - else - tcp->th_sum = in_pseudo(ip->ip_src.s_addr, - ip->ip_dst.s_addr, htons(IPPROTO_TCP)); + tcp->th_sum = in_pseudo(ip->ip_src.s_addr, + ip->ip_dst.s_addr, htons(IPPROTO_TCP)); } *m_head = m; } @@ -1602,7 +1606,7 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1631,23 +1635,48 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) } m = *m_head; + /* Configure VLAN hardware tag insertion. */ + if ((m->m_flags & M_VLANTAG) != 0) { + vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); + vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); + cflags |= AGE_TD_INSERT_VLAN_TAG; + } + + desc = NULL; + i = 0; if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { - /* Configure TSO. */ - if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { - /* Not TSO but IP/TCP checksum offload. */ - cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; - /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ - m->m_pkthdr.csum_flags &= ~CSUM_TSO; - } else { - /* Request TSO and set MSS. */ - cflags |= AGE_TD_TSO_IPV4; - cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; - cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << - AGE_TD_TSO_MSS_SHIFT); - } + /* Request TSO and set MSS. */ + cflags |= AGE_TD_TSO_IPV4; + cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; + cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << + AGE_TD_TSO_MSS_SHIFT); /* Set IP/TCP header size. */ cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; + /* + * L1 requires the first buffer should only hold IP/TCP + * header data. TCP payload should be handled in other + * descriptors. + */ + hdrlen = poff + (tcp->th_off << 2); + desc = &sc->age_rdata.age_tx_ring[prod]; + desc->addr = htole64(txsegs[0].ds_addr); + desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); + desc->flags = htole32(cflags); + sc->age_cdata.age_tx_cnt++; + AGE_DESC_INC(prod, AGE_TX_RING_CNT); + if (m->m_len - hdrlen > 0) { + /* Handle remaining payload of the 1st fragment. */ + desc = &sc->age_rdata.age_tx_ring[prod]; + desc->addr = htole64(txsegs[0].ds_addr + hdrlen); + desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | + vtag); + desc->flags = htole32(cflags); + sc->age_cdata.age_tx_cnt++; + AGE_DESC_INC(prod, AGE_TX_RING_CNT); + } + /* Handle remaining fragments. */ + i = 1; } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { /* Configure Tx IP/TCP/UDP checksum offload. */ cflags |= AGE_TD_CSUM; @@ -1661,16 +1690,7 @@ age_encap(struct age_softc *sc, struct mbuf **m_head) cflags |= ((poff + m->m_pkthdr.csum_data) << AGE_TD_CSUM_XSUMOFFSET_SHIFT); } - - /* Configure VLAN hardware tag insertion. */ - if ((m->m_flags & M_VLANTAG) != 0) { - vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); - vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); - cflags |= AGE_TD_INSERT_VLAN_TAG; - } - - desc = NULL; - for (i = 0; i < nsegs; i++) { + for (; i < nsegs; i++) { desc = &sc->age_rdata.age_tx_ring[prod]; desc->addr = htole64(txsegs[i].ds_addr); desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); @@ -2255,16 +2275,53 @@ age_txintr(struct age_softc *sc, int tpd_cons) } } +#ifndef __NO_STRICT_ALIGNMENT +static struct mbuf * +age_fixup_rx(struct ifnet *ifp, struct mbuf *m) +{ + struct mbuf *n; + int i; + uint16_t *src, *dst; + + src = mtod(m, uint16_t *); + dst = src - 3; + + if (m->m_next == NULL) { + for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) + *dst++ = *src++; + m->m_data -= 6; + return (m); + } + /* + * Append a new mbuf to received mbuf chain and copy ethernet + * header from the mbuf chain. This can save lots of CPU + * cycles for jumbo frame. + */ + MGETHDR(n, M_NOWAIT, MT_DATA); + if (n == NULL) { + ifp->if_iqdrops++; + m_freem(m); + return (NULL); + } + bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); + m->m_data += ETHER_HDR_LEN; + m->m_len -= ETHER_HDR_LEN; + n->m_len = ETHER_HDR_LEN; + M_MOVE_PKTHDR(n, m); + n->m_next = m; + return (n); +} +#endif + /* Receive a frame. */ static void age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) { struct age_rxdesc *rxd; - struct rx_desc *desc; struct ifnet *ifp; struct mbuf *mp, *m; uint32_t status, index, vtag; - int count, nsegs, pktlen; + int count, nsegs; int rx_cons; AGE_LOCK_ASSERT(sc); @@ -2276,9 +2333,7 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) nsegs = AGE_RX_NSEGS(index); sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); - if ((status & AGE_RRD_ERROR) != 0 && - (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | - AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { + if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { /* * We want to pass the following frames to upper * layer regardless of error status of Rx return @@ -2288,33 +2343,31 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) * o frame length and protocol specific length * does not match. */ - sc->age_cdata.age_rx_cons += nsegs; - sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; - return; + status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; + if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | + AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) + return; } - pktlen = 0; for (count = 0; count < nsegs; count++, AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { rxd = &sc->age_cdata.age_rxdesc[rx_cons]; mp = rxd->rx_m; - desc = rxd->rx_desc; /* Add a new receive buffer to the ring. */ if (age_newbuf(sc, rxd) != 0) { ifp->if_iqdrops++; /* Reuse Rx buffers. */ - if (sc->age_cdata.age_rxhead != NULL) { + if (sc->age_cdata.age_rxhead != NULL) m_freem(sc->age_cdata.age_rxhead); - AGE_RXCHAIN_RESET(sc); - } break; } - /* The length of the first mbuf is computed last. */ - if (count != 0) { - mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); - pktlen += mp->m_len; - } + /* + * Assume we've received a full sized frame. + * Actual size is fixed when we encounter the end of + * multi-segmented frame. + */ + mp->m_len = AGE_RX_BUF_SIZE; /* Chain received mbufs. */ if (sc->age_cdata.age_rxhead == NULL) { @@ -2329,14 +2382,20 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) } if (count == nsegs - 1) { + /* Last desc. for this frame. */ + m = sc->age_cdata.age_rxhead; + m->m_flags |= M_PKTHDR; /* * It seems that L1 controller has no way * to tell hardware to strip CRC bytes. */ - sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; + m->m_pkthdr.len = sc->age_cdata.age_rxlen - + ETHER_CRC_LEN; if (nsegs > 1) { + /* Set last mbuf size. */ + mp->m_len = sc->age_cdata.age_rxlen - + ((nsegs - 1) * AGE_RX_BUF_SIZE); /* Remove the CRC bytes in chained mbufs. */ - pktlen -= ETHER_CRC_LEN; if (mp->m_len <= ETHER_CRC_LEN) { sc->age_cdata.age_rxtail = sc->age_cdata.age_rxprev_tail; @@ -2347,15 +2406,9 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) } else { mp->m_len -= ETHER_CRC_LEN; } - } - - m = sc->age_cdata.age_rxhead; - m->m_flags |= M_PKTHDR; + } else + m->m_len = m->m_pkthdr.len; m->m_pkthdr.rcvif = ifp; - m->m_pkthdr.len = sc->age_cdata.age_rxlen; - /* Set the first mbuf length. */ - m->m_len = sc->age_cdata.age_rxlen - pktlen; - /* * Set checksum information. * It seems that L1 controller can compute partial @@ -2370,9 +2423,9 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) */ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && (status & AGE_RRD_IPV4) != 0) { - m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; if ((status & AGE_RRD_IPCSUM_NOK) == 0) - m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + m->m_pkthdr.csum_flags |= + CSUM_IP_CHECKED | CSUM_IP_VALID; if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { m->m_pkthdr.csum_flags |= @@ -2393,22 +2446,21 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); m->m_flags |= M_VLANTAG; } - +#ifndef __NO_STRICT_ALIGNMENT + m = age_fixup_rx(ifp, m); + if (m != NULL) +#endif + { /* Pass it on. */ AGE_UNLOCK(sc); (*ifp->if_input)(ifp, m); AGE_LOCK(sc); - - /* Reset mbuf chains. */ - AGE_RXCHAIN_RESET(sc); + } } } - if (count != nsegs) { - sc->age_cdata.age_rx_cons += nsegs; - sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; - } else - sc->age_cdata.age_rx_cons = rx_cons; + /* Reset mbuf chains. */ + AGE_RXCHAIN_RESET(sc); } static int @@ -2430,7 +2482,7 @@ age_rxintr(struct age_softc *sc, int rr_prod, int count) sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); for (prog = 0; rr_cons != rr_prod; prog++) { - if (count <= 0) + if (count-- <= 0) break; rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); @@ -2443,16 +2495,16 @@ age_rxintr(struct age_softc *sc, int rr_prod, int count) * I'm not sure whether this check is really needed. */ pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); - if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / - (MCLBYTES - ETHER_ALIGN))) + if (nsegs != (pktlen + (AGE_RX_BUF_SIZE - 1)) / AGE_RX_BUF_SIZE) break; - prog++; /* Received a frame. */ age_rxeof(sc, rxrd); /* Clear return ring. */ rxrd->index = 0; AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); + sc->age_cdata.age_rx_cons += nsegs; + sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; } if (prog > 0) { @@ -3048,11 +3100,13 @@ age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) AGE_LOCK_ASSERT(sc); - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; - m_adj(m, ETHER_ALIGN); +#ifndef __NO_STRICT_ALIGNMENT + m_adj(m, AGE_RX_BUF_ALIGN); +#endif if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { diff --git a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h index db98eb15ae..6ee5423fc8 100644 --- a/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h +++ b/src/add-ons/kernel/drivers/network/attansic_l1/dev/age/if_agevar.h @@ -43,6 +43,12 @@ #define AGE_TSO_MAXSEGSIZE 4096 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) #define AGE_MAXTXSEGS 32 +#define AGE_RX_BUF_ALIGN 8 +#ifndef __NO_STRICT_ALIGNMENT +#define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN) +#else +#define AGE_RX_BUF_SIZE (MCLBYTES) +#endif #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) diff --git a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c index 02a1e796f9..208a670210 100644 --- a/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c +++ b/src/add-ons/kernel/drivers/network/attansic_l2/dev/ae/if_ae.c @@ -585,6 +585,9 @@ ae_init_locked(ae_softc_t *sc) val = eaddr[0] << 8 | eaddr[1]; AE_WRITE_4(sc, AE_EADDR1_REG, val); + bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120); + bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); + bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); /* * Set ring buffers base addresses. */ @@ -1119,7 +1122,7 @@ ae_alloc_rings(ae_softc_t *sc) * Create DMA tag for TxD. */ error = bus_dma_tag_create(sc->dma_parent_tag, - 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, &sc->dma_txd_tag); @@ -1132,7 +1135,7 @@ ae_alloc_rings(ae_softc_t *sc) * Create DMA tag for TxS. */ error = bus_dma_tag_create(sc->dma_parent_tag, - 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, &sc->dma_txs_tag); @@ -1765,6 +1768,10 @@ ae_int_task(void *arg, int pending) ifp = sc->ifp; val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ + if (val == 0) { + AE_UNLOCK(sc); + return; + } /* * Clear interrupts and disable them. @@ -1787,12 +1794,16 @@ ae_int_task(void *arg, int pending) ae_tx_intr(sc); if ((val & AE_ISR_RX_EVENT) != 0) ae_rx_intr(sc); - } + /* + * Re-enable interrupts. + */ + AE_WRITE_4(sc, AE_ISR_REG, 0); - /* - * Re-enable interrupts. - */ - AE_WRITE_4(sc, AE_ISR_REG, 0); + if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + ae_start_locked(ifp); + } + } AE_UNLOCK(sc); } @@ -1853,10 +1864,10 @@ ae_tx_intr(ae_softc_t *sc) ifp->if_oerrors++; sc->tx_inproc--; - - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; } + if ((sc->flags & AE_FLAG_TXAVAIL) != 0) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (sc->tx_inproc < 0) { if_printf(ifp, "Received stray Tx interrupt(s).\n"); sc->tx_inproc = 0; @@ -1864,11 +1875,6 @@ ae_tx_intr(ae_softc_t *sc) if (sc->tx_inproc == 0) sc->wd_timer = 0; /* Unarm watchdog. */ - - if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) - ae_start_locked(ifp); - } /* * Syncronize DMA buffers. @@ -1927,7 +1933,7 @@ ae_rx_intr(ae_softc_t *sc) ae_rxd_t *rxd; struct ifnet *ifp; uint16_t flags; - int error; + int count, error; KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); @@ -1941,7 +1947,7 @@ ae_rx_intr(ae_softc_t *sc) bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - for (;;) { + for (count = 0;; count++) { rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); flags = le16toh(rxd->flags); if ((flags & AE_RXD_UPDATE) == 0) @@ -1968,10 +1974,14 @@ ae_rx_intr(ae_softc_t *sc) } } - /* - * Update Rx index. - */ - AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); + if (count > 0) { + bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* + * Update Rx index. + */ + AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); + } } static void diff --git a/src/add-ons/kernel/drivers/network/broadcom440x/dev/bfe/if_bfe.c b/src/add-ons/kernel/drivers/network/broadcom440x/dev/bfe/if_bfe.c index 6dd33cd591..44514e2d0d 100644 --- a/src/add-ons/kernel/drivers/network/broadcom440x/dev/bfe/if_bfe.c +++ b/src/add-ons/kernel/drivers/network/broadcom440x/dev/bfe/if_bfe.c @@ -792,7 +792,7 @@ bfe_list_newbuf(struct bfe_softc *sc, int c) u_int32_t ctrl; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); m->m_len = m->m_pkthdr.len = MCLBYTES; if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, @@ -1520,7 +1520,7 @@ bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h index be206081a2..8a156f5d8f 100644 --- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h +++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bce/if_bcereg.h @@ -32,10 +32,6 @@ #ifndef _BCEREG_H_DEFINED #define _BCEREG_H_DEFINED -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" -#endif - #include #include #include @@ -623,7 +619,7 @@ struct bce_type { u_int16_t bce_did; u_int16_t bce_svid; u_int16_t bce_sdid; - char *bce_name; + const char *bce_name; }; /****************************************************************************/ @@ -717,7 +713,7 @@ struct flash_spec { u32 page_size; u32 addr_mask; u32 total_size; - u8 *name; + const u8 *name; }; @@ -2002,7 +1998,7 @@ struct l2_fhdr { #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) #define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) #define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) - + #define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff #define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 @@ -6319,31 +6315,31 @@ struct fw_info { u32 text_addr; u32 text_len; u32 text_index; - u32 *text; + const u32 *text; /* Data section. */ u32 data_addr; u32 data_len; u32 data_index; - u32 *data; + const u32 *data; /* SBSS section. */ u32 sbss_addr; u32 sbss_len; u32 sbss_index; - u32 *sbss; + const u32 *sbss; /* BSS section. */ u32 bss_addr; u32 bss_len; u32 bss_index; - u32 *bss; + const u32 *bss; /* Read-only section. */ u32 rodata_addr; u32 rodata_len; u32 rodata_index; - u32 *rodata; + const u32 *rodata; }; #define RV2P_PROC1 0 @@ -6422,7 +6418,9 @@ struct fw_info { struct bce_softc { - /* Interface info. Must be first!! */ + struct mtx bce_mtx; + + /* Interface info */ struct ifnet *bce_ifp; /* Parent device handle */ @@ -6449,13 +6447,8 @@ struct bce_softc /* IRQ Resource Handle */ struct resource *bce_res_irq; - struct mtx bce_mtx; - /* Interrupt handler. */ - driver_intr_t *bce_intr; void *bce_intrhand; - int bce_irq_rid; - int bce_msi_count; /* ASIC Chip ID. */ u32 bce_chipid; @@ -6473,6 +6466,7 @@ struct bce_softc #define BCE_USING_MSIX_FLAG 0x00000100 #define BCE_PCIE_FLAG 0x00000200 #define BCE_USING_TX_FLOW_CONTROL 0x00000400 +#define BCE_USING_RX_FLOW_CONTROL 0x00000800 /* Controller capability flags. */ u32 bce_cap_flags; @@ -6510,7 +6504,7 @@ struct bce_softc u16 link_speed; /* Flash NVRAM settings */ - struct flash_spec *bce_flash_info; + const struct flash_spec *bce_flash_info; /* Flash NVRAM size */ u32 bce_flash_size; @@ -6519,7 +6513,7 @@ struct bce_softc u32 bce_shmem_base; /* Name string */ - char *bce_name; + const char *bce_name; /* Tracks the version of bootcode firmware. */ char bce_bc_ver[32]; @@ -6567,14 +6561,6 @@ struct bce_softc u16 bce_rx_ticks; u32 bce_stats_ticks; - /* ToDo: Can these be removed? */ - u16 bce_comp_prod_trip_int; - u16 bce_comp_prod_trip; - u16 bce_com_ticks_int; - u16 bce_com_ticks; - u16 bce_cmd_ticks_int; - u16 bce_cmd_ticks; - /* The address of the integrated PHY on the MII bus. */ int bce_phy_addr; @@ -6607,11 +6593,9 @@ struct bce_softc int watchdog_timer; /* Frame size and mbuf allocation size for RX frames. */ - u32 max_frame_size; int rx_bd_mbuf_alloc_size; int rx_bd_mbuf_data_len; int rx_bd_mbuf_align_pad; - int pg_bd_mbuf_alloc_size; /* Receive mode settings (i.e promiscuous, multicast, etc.). */ u32 rx_mode; @@ -6835,4 +6819,3 @@ struct bce_softc }; #endif /* __BCEREG_H_DEFINED */ - diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c index d635000c52..7839cc5649 100644 --- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c +++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bge.c @@ -35,10 +35,10 @@ __FBSDID("$FreeBSD$"); /* - * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. + * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver * * The Broadcom BCM5700 is based on technology originally developed by - * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet + * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has * two on-board MIPS R4000 CPUs and can have as much as 16MB of external * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo @@ -139,7 +139,7 @@ MODULE_DEPEND(bge, miibus, 1, 1, 1); static const struct bge_type { uint16_t bge_vid; uint16_t bge_did; -} const bge_devs[] = { +} bge_devs[] = { { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, @@ -216,7 +216,9 @@ static const struct bge_type { { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, @@ -239,7 +241,7 @@ static const struct bge_type { static const struct bge_vendor { uint16_t v_id; const char *v_name; -} const bge_vendors[] = { +} bge_vendors[] = { { ALTEON_VENDORID, "Alteon" }, { ALTIMA_VENDORID, "Altima" }, { APPLE_VENDORID, "Apple" }, @@ -254,7 +256,7 @@ static const struct bge_vendor { static const struct bge_revision { uint32_t br_chipid; const char *br_name; -} const bge_revisions[] = { +} bge_revisions[] = { { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, @@ -328,7 +330,7 @@ static const struct bge_revision { * Some defaults for major revisions, so that newer steppings * that we don't know about have a shot at working. */ -static const struct bge_revision const bge_majorrevs[] = { +static const struct bge_revision bge_majorrevs[] = { { BGE_ASICREV_BCM5700, "unknown BCM5700" }, { BGE_ASICREV_BCM5701, "unknown BCM5701" }, { BGE_ASICREV_BCM5703, "unknown BCM5703" }, @@ -347,6 +349,7 @@ static const struct bge_revision const bge_majorrevs[] = { { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, { BGE_ASICREV_BCM5906, "unknown BCM5906" }, { BGE_ASICREV_BCM57765, "unknown BCM57765" }, + { BGE_ASICREV_BCM57766, "unknown BCM57766" }, { BGE_ASICREV_BCM57780, "unknown BCM57780" }, { BGE_ASICREV_BCM5717, "unknown BCM5717" }, { BGE_ASICREV_BCM5719, "unknown BCM5719" }, @@ -362,9 +365,11 @@ static const struct bge_revision const bge_majorrevs[] = { #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) +#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) -const struct bge_revision * bge_lookup_rev(uint32_t); -const struct bge_vendor * bge_lookup_vendor(uint16_t); +static uint32_t bge_chipid(device_t); +static const struct bge_vendor * bge_lookup_vendor(uint16_t); +static const struct bge_revision * bge_lookup_rev(uint32_t); typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); @@ -463,8 +468,9 @@ static void bge_miibus_statchg(device_t); static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); #endif -#define BGE_RESET_START 1 -#define BGE_RESET_STOP 2 +#define BGE_RESET_SHUTDOWN 0 +#define BGE_RESET_START 1 +#define BGE_RESET_SUSPEND 2 static void bge_sig_post_reset(struct bge_softc *, int); static void bge_sig_legacy(struct bge_softc *, int); static void bge_sig_pre_reset(struct bge_softc *, int); @@ -472,6 +478,13 @@ static void bge_stop_fw(struct bge_softc *); static int bge_reset(struct bge_softc *); static void bge_link_upd(struct bge_softc *); +static void bge_ape_lock_init(struct bge_softc *); +static void bge_ape_read_fw_ver(struct bge_softc *); +static int bge_ape_lock(struct bge_softc *, int); +static void bge_ape_unlock(struct bge_softc *, int); +static void bge_ape_send_event(struct bge_softc *, uint32_t); +static void bge_ape_driver_state_change(struct bge_softc *, int); + /* * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may * leak information to untrusted users. It is also known to cause alignment @@ -480,6 +493,7 @@ static void bge_link_upd(struct bge_softc *); #ifdef BGE_REGISTER_DEBUG static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); +static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); #endif static void bge_add_sysctls(struct bge_softc *); @@ -521,7 +535,7 @@ static int bge_allow_asf = 1; TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); -SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); +static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, "Allow ASF mode if available"); @@ -648,6 +662,318 @@ bge_writembx(struct bge_softc *sc, int off, int val) CSR_READ_4(sc, off); } +/* + * Clear all stale locks and select the lock for this driver instance. + */ +static void +bge_ape_lock_init(struct bge_softc *sc) +{ + uint32_t bit, regbase; + int i; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) + regbase = BGE_APE_LOCK_GRANT; + else + regbase = BGE_APE_PER_LOCK_GRANT; + + /* Clear any stale locks. */ + for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { + switch (i) { + case BGE_APE_LOCK_PHY0: + case BGE_APE_LOCK_PHY1: + case BGE_APE_LOCK_PHY2: + case BGE_APE_LOCK_PHY3: + bit = BGE_APE_LOCK_GRANT_DRIVER0; + break; + default: + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_GRANT_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + } + APE_WRITE_4(sc, regbase + 4 * i, bit); + } + + /* Select the PHY lock based on the device's function number. */ + switch (sc->bge_func_addr) { + case 0: + sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; + break; + case 1: + sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; + break; + case 2: + sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; + break; + case 3: + sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; + break; + default: + device_printf(sc->bge_dev, + "PHY lock not supported on this function\n"); + } +} + +/* + * Check for APE firmware, set flags, and print version info. + */ +static void +bge_ape_read_fw_ver(struct bge_softc *sc) +{ + const char *fwtype; + uint32_t apedata, features; + + /* Check for a valid APE signature in shared memory. */ + apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); + if (apedata != BGE_APE_SEG_SIG_MAGIC) { + sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; + return; + } + + /* Check if APE firmware is running. */ + apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); + if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { + device_printf(sc->bge_dev, "APE signature found " + "but FW status not ready! 0x%08x\n", apedata); + return; + } + + sc->bge_mfw_flags |= BGE_MFW_ON_APE; + + /* Fetch the APE firwmare type and version. */ + apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); + features = APE_READ_4(sc, BGE_APE_FW_FEATURES); + if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { + sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; + fwtype = "NCSI"; + } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { + sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; + fwtype = "DASH"; + } else + fwtype = "UNKN"; + + /* Print the APE firmware version. */ + device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", + fwtype, + (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, + (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, + (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, + (apedata & BGE_APE_FW_VERSION_BLDMSK)); +} + +static int +bge_ape_lock(struct bge_softc *sc, int locknum) +{ + uint32_t bit, gnt, req, status; + int i, off; + + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) + return (0); + + /* Lock request/grant registers have different bases. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { + req = BGE_APE_LOCK_REQ; + gnt = BGE_APE_LOCK_GRANT; + } else { + req = BGE_APE_PER_LOCK_REQ; + gnt = BGE_APE_PER_LOCK_GRANT; + } + + off = 4 * locknum; + + switch (locknum) { + case BGE_APE_LOCK_GPIO: + /* Lock required when using GPIO. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) + return (0); + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_REQ_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_GRC: + /* Lock required to reset the device. */ + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_REQ_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_MEM: + /* Lock required when accessing certain APE memory. */ + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_REQ_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_PHY0: + case BGE_APE_LOCK_PHY1: + case BGE_APE_LOCK_PHY2: + case BGE_APE_LOCK_PHY3: + /* Lock required when accessing PHYs. */ + bit = BGE_APE_LOCK_REQ_DRIVER0; + break; + default: + return (EINVAL); + } + + /* Request a lock. */ + APE_WRITE_4(sc, req + off, bit); + + /* Wait up to 1 second to acquire lock. */ + for (i = 0; i < 20000; i++) { + status = APE_READ_4(sc, gnt + off); + if (status == bit) + break; + DELAY(50); + } + + /* Handle any errors. */ + if (status != bit) { + device_printf(sc->bge_dev, "APE lock %d request failed! " + "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", + locknum, req + off, bit & 0xFFFF, gnt + off, + status & 0xFFFF); + /* Revoke the lock request. */ + APE_WRITE_4(sc, gnt + off, bit); + return (EBUSY); + } + + return (0); +} + +static void +bge_ape_unlock(struct bge_softc *sc, int locknum) +{ + uint32_t bit, gnt; + int off; + + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) + return; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) + gnt = BGE_APE_LOCK_GRANT; + else + gnt = BGE_APE_PER_LOCK_GRANT; + + off = 4 * locknum; + + switch (locknum) { + case BGE_APE_LOCK_GPIO: + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) + return; + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_GRANT_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_GRC: + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_GRANT_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_MEM: + if (sc->bge_func_addr == 0) + bit = BGE_APE_LOCK_GRANT_DRIVER0; + else + bit = (1 << sc->bge_func_addr); + break; + case BGE_APE_LOCK_PHY0: + case BGE_APE_LOCK_PHY1: + case BGE_APE_LOCK_PHY2: + case BGE_APE_LOCK_PHY3: + bit = BGE_APE_LOCK_GRANT_DRIVER0; + break; + default: + return; + } + + APE_WRITE_4(sc, gnt + off, bit); +} + +/* + * Send an event to the APE firmware. + */ +static void +bge_ape_send_event(struct bge_softc *sc, uint32_t event) +{ + uint32_t apedata; + int i; + + /* NCSI does not support APE events. */ + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) + return; + + /* Wait up to 1ms for APE to service previous event. */ + for (i = 10; i > 0; i--) { + if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) + break; + apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); + if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { + APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | + BGE_APE_EVENT_STATUS_EVENT_PENDING); + bge_ape_unlock(sc, BGE_APE_LOCK_MEM); + APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); + break; + } + bge_ape_unlock(sc, BGE_APE_LOCK_MEM); + DELAY(100); + } + if (i == 0) + device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", + event); +} + +static void +bge_ape_driver_state_change(struct bge_softc *sc, int kind) +{ + uint32_t apedata, event; + + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) + return; + + switch (kind) { + case BGE_RESET_START: + /* If this is the first load, clear the load counter. */ + apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); + if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) + APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); + else { + apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); + APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); + } + APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, + BGE_APE_HOST_SEG_SIG_MAGIC); + APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, + BGE_APE_HOST_SEG_LEN_MAGIC); + + /* Add some version info if bge(4) supports it. */ + APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, + BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); + APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, + BGE_APE_HOST_BEHAV_NO_PHYLOCK); + APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, + BGE_APE_HOST_HEARTBEAT_INT_DISABLE); + APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, + BGE_APE_HOST_DRVR_STATE_START); + event = BGE_APE_EVENT_STATUS_STATE_START; + break; + case BGE_RESET_SHUTDOWN: + APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, + BGE_APE_HOST_DRVR_STATE_UNLOAD); + event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; + break; + case BGE_RESET_SUSPEND: + event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; + break; + default: + return; + } + + bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | + BGE_APE_EVENT_STATUS_STATE_CHNGE); +} + /* * Map a single buffer address. */ @@ -812,6 +1138,9 @@ bge_miibus_readreg(device_t dev, int phy, int reg) sc = device_get_softc(dev); + if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) + return (0); + /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { CSR_WRITE_4(sc, BGE_MI_MODE, @@ -846,6 +1175,8 @@ bge_miibus_readreg(device_t dev, int phy, int reg) DELAY(80); } + bge_ape_unlock(sc, sc->bge_phy_ape_lock); + if (val & BGE_MICOMM_READFAIL) return (0); @@ -864,6 +1195,9 @@ bge_miibus_writereg(device_t dev, int phy, int reg, int val) (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) return (0); + if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) + return (0); + /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { CSR_WRITE_4(sc, BGE_MI_MODE, @@ -889,9 +1223,11 @@ bge_miibus_writereg(device_t dev, int phy, int reg, int val) DELAY(80); } + bge_ape_unlock(sc, sc->bge_phy_ape_lock); + if (i == BGE_TIMEOUT) device_printf(sc->bge_dev, - "PHY write timed out (phy %d, reg %d, val %d)\n", + "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", phy, reg, val); return (0); @@ -902,7 +1238,11 @@ bge_miibus_statchg(device_t dev) { struct bge_softc *sc; struct mii_data *mii; + uint32_t mac_mode, rx_mode, tx_mode; + sc = device_get_softc(dev); + if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + return; mii = device_get_softc(sc->bge_miibus); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == @@ -928,30 +1268,40 @@ bge_miibus_statchg(device_t dev) sc->bge_link = 0; if (sc->bge_link == 0) return; - BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); + + /* + * APE firmware touches these registers to keep the MAC + * connected to the outside world. Try to keep the + * accesses atomic. + */ + + /* Set the port mode (MII/GMII) to match the link speed. */ + mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & + ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); + tx_mode = CSR_READ_4(sc, BGE_TX_MODE); + rx_mode = CSR_READ_4(sc, BGE_RX_MODE); + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) - BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); + mac_mode |= BGE_PORTMODE_GMII; else - BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); + mac_mode |= BGE_PORTMODE_MII; - if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { - BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); - if ((IFM_OPTIONS(mii->mii_media_active) & - IFM_ETH_TXPAUSE) != 0) - BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); - else - BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); - if ((IFM_OPTIONS(mii->mii_media_active) & - IFM_ETH_RXPAUSE) != 0) - BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); - else - BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); - } else { - BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); - BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); - BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); - } + /* Set MAC flow control behavior to match link flow control settings. */ + tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; + rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) + tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) + rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; + } else + mac_mode |= BGE_MACMODE_HALF_DUPLEX; + + CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); + DELAY(40); + CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); + CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); } /* @@ -969,12 +1319,12 @@ bge_newbuf_std(struct bge_softc *sc, int i) if (sc->bge_flags & BGE_FLAG_JUMBO_STD && (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MJUM9BYTES; } else { - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; @@ -1025,11 +1375,11 @@ bge_newbuf_jumbo(struct bge_softc *sc, int i) struct mbuf *m; int error, nsegs; - MGETHDR(m, M_DONTWAIT, MT_DATA); + MGETHDR(m, M_NOWAIT, MT_DATA); if (m == NULL) return (ENOBUFS); - m_cljget(m, M_DONTWAIT, MJUM9BYTES); + m_cljget(m, M_NOWAIT, MJUM9BYTES); if (!(m->m_flags & M_EXT)) { m_freem(m); return (ENOBUFS); @@ -1327,12 +1677,19 @@ bge_sig_pre_reset(struct bge_softc *sc, int type) bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, BGE_FW_DRV_STATE_START); break; - case BGE_RESET_STOP: + case BGE_RESET_SHUTDOWN: bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, BGE_FW_DRV_STATE_UNLOAD); break; + case BGE_RESET_SUSPEND: + bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, + BGE_FW_DRV_STATE_SUSPEND); + break; } } + + if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) + bge_ape_driver_state_change(sc, type); } static void @@ -1346,12 +1703,14 @@ bge_sig_post_reset(struct bge_softc *sc, int type) BGE_FW_DRV_STATE_START_DONE); /* START DONE */ break; - case BGE_RESET_STOP: + case BGE_RESET_SHUTDOWN: bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, BGE_FW_DRV_STATE_UNLOAD_DONE); break; } } + if (type == BGE_RESET_SHUTDOWN) + bge_ape_driver_state_change(sc, type); } static void @@ -1364,7 +1723,7 @@ bge_sig_legacy(struct bge_softc *sc, int type) bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, BGE_FW_DRV_STATE_START); break; - case BGE_RESET_STOP: + case BGE_RESET_SHUTDOWN: bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, BGE_FW_DRV_STATE_UNLOAD); break; @@ -1401,11 +1760,6 @@ bge_dma_swap_options(struct bge_softc *sc) #if BYTE_ORDER == BIG_ENDIAN dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; #endif - if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720) - dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA | - BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE | - BGE_MODECTL_HTX2B_ENABLE; - return (dma_options); } @@ -1425,9 +1779,6 @@ bge_chipinit(struct bge_softc *sc) misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); - /* Clear the MAC control register */ - CSR_WRITE_4(sc, BGE_MAC_MODE, 0); - /* * Clear the MAC statistics block in the NIC's * internal memory. @@ -1457,8 +1808,10 @@ bge_chipinit(struct bge_softc *sc) dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); if (sc->bge_flags & BGE_FLAG_PCIE) { - /* Read watermark not used, 128 bytes for write. */ - dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + if (sc->bge_mps >= 256) + dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); + else + dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); } else if (sc->bge_flags & BGE_FLAG_PCIX) { if (BGE_IS_5714_FAMILY(sc)) { /* 256 bytes for read and write. */ @@ -1533,8 +1886,16 @@ bge_chipinit(struct bge_softc *sc) /* * Set up general mode register. */ - mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR | - BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; + mode_ctl = bge_dma_swap_options(sc); + if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { + /* Retain Host-2-BMC settings written by APE firmware. */ + mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & + (BGE_MODECTL_BYTESWAP_B2HRX_DATA | + BGE_MODECTL_WORDSWAP_B2HRX_DATA | + BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); + } + mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | + BGE_MODECTL_TX_NO_PHDR_CSUM; /* * BCM5701 B5 have a bug causing data corruption when using @@ -1562,7 +1923,7 @@ bge_chipinit(struct bge_softc *sc) PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); - /* Set the timer prescaler (always 66Mhz) */ + /* Set the timer prescaler (always 66 MHz). */ CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ @@ -1893,7 +2254,7 @@ bge_blockinit(struct bge_softc *sc) } else if (!BGE_IS_5705_PLUS(sc)) limit = BGE_RX_RINGS_MAX; else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || - sc->bge_asicrev == BGE_ASICREV_BCM57765) + BGE_IS_57765_PLUS(sc)) limit = 4; else limit = 1; @@ -1925,9 +2286,9 @@ bge_blockinit(struct bge_softc *sc) /* Set random backoff seed for TX */ CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, - IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + + (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + - IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + + IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & BGE_TX_BACKOFF_SEED_MASK); /* Set inter-packet gap */ @@ -2025,6 +2386,7 @@ bge_blockinit(struct bge_softc *sc) if (!(BGE_IS_5705_PLUS(sc))) CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + /* Turn on DMA, clear stats. */ val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | @@ -2037,11 +2399,15 @@ bge_blockinit(struct bge_softc *sc) else val |= BGE_PORTMODE_MII; - /* Turn on DMA, clear stats */ + /* Allow APE to send/receive frames. */ + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) + val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; + CSR_WRITE_4(sc, BGE_MAC_MODE, val); + DELAY(40); /* Set misc. local control, enable interrupts on attentions */ - CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); #ifdef notdef /* Assert GPIO pins for PHY reset */ @@ -2111,8 +2477,8 @@ bge_blockinit(struct bge_softc *sc) * Adjust tx margin to prevent TX data corruption and * fix internal FIFO overflow. */ - if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || - sc->bge_asicrev == BGE_ASICREV_BCM5720) { + if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && + sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | BGE_RDMA_RSRVCTRL_TXMRGN_MASK); @@ -2227,7 +2593,7 @@ bge_blockinit(struct bge_softc *sc) return (0); } -const struct bge_revision * +static const struct bge_revision * bge_lookup_rev(uint32_t chipid) { const struct bge_revision *br; @@ -2245,7 +2611,7 @@ bge_lookup_rev(uint32_t chipid) return (NULL); } -const struct bge_vendor * +static const struct bge_vendor * bge_lookup_vendor(uint16_t vid) { const struct bge_vendor *v; @@ -2254,10 +2620,47 @@ bge_lookup_vendor(uint16_t vid) if (v->v_id == vid) return (v); - panic("%s: unknown vendor %d", __func__, vid); return (NULL); } +static uint32_t +bge_chipid(device_t dev) +{ + uint32_t id; + + id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> + BGE_PCIMISCCTL_ASICREV_SHIFT; + if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { + /* + * Find the ASCI revision. Different chips use different + * registers. + */ + switch (pci_get_device(dev)) { + case BCOM_DEVICEID_BCM5717: + case BCOM_DEVICEID_BCM5718: + case BCOM_DEVICEID_BCM5719: + case BCOM_DEVICEID_BCM5720: + id = pci_read_config(dev, + BGE_PCI_GEN2_PRODID_ASICREV, 4); + break; + case BCOM_DEVICEID_BCM57761: + case BCOM_DEVICEID_BCM57762: + case BCOM_DEVICEID_BCM57765: + case BCOM_DEVICEID_BCM57766: + case BCOM_DEVICEID_BCM57781: + case BCOM_DEVICEID_BCM57785: + case BCOM_DEVICEID_BCM57791: + case BCOM_DEVICEID_BCM57795: + id = pci_read_config(dev, + BGE_PCI_GEN15_PRODID_ASICREV, 4); + break; + default: + id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); + } + } + return (id); +} + /* * Probe for a Broadcom chip. Check the PCI vendor and device IDs * against our list and return its name if we find a match. @@ -2275,59 +2678,34 @@ bge_probe(device_t dev) char model[64]; const struct bge_revision *br; const char *pname; - struct bge_softc *sc = device_get_softc(dev); + struct bge_softc *sc; const struct bge_type *t = bge_devs; const struct bge_vendor *v; uint32_t id; uint16_t did, vid; + sc = device_get_softc(dev); sc->bge_dev = dev; vid = pci_get_vendor(dev); did = pci_get_device(dev); while(t->bge_vid != 0) { if ((vid == t->bge_vid) && (did == t->bge_did)) { - id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> - BGE_PCIMISCCTL_ASICREV_SHIFT; - if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { - /* - * Find the ASCI revision. Different chips - * use different registers. - */ - switch (pci_get_device(dev)) { - case BCOM_DEVICEID_BCM5717: - case BCOM_DEVICEID_BCM5718: - case BCOM_DEVICEID_BCM5719: - case BCOM_DEVICEID_BCM5720: - id = pci_read_config(dev, - BGE_PCI_GEN2_PRODID_ASICREV, 4); - break; - case BCOM_DEVICEID_BCM57761: - case BCOM_DEVICEID_BCM57765: - case BCOM_DEVICEID_BCM57781: - case BCOM_DEVICEID_BCM57785: - case BCOM_DEVICEID_BCM57791: - case BCOM_DEVICEID_BCM57795: - id = pci_read_config(dev, - BGE_PCI_GEN15_PRODID_ASICREV, 4); - break; - default: - id = pci_read_config(dev, - BGE_PCI_PRODID_ASICREV, 4); - } - } + id = bge_chipid(dev); br = bge_lookup_rev(id); - v = bge_lookup_vendor(vid); if (bge_has_eaddr(sc) && pci_get_vpd_ident(dev, &pname) == 0) - snprintf(model, 64, "%s", pname); - else - snprintf(model, 64, "%s %s", v->v_name, + snprintf(model, sizeof(model), "%s", pname); + else { + v = bge_lookup_vendor(vid); + snprintf(model, sizeof(model), "%s %s", + v != NULL ? v->v_name : "Unknown", br != NULL ? br->br_name : - "NetXtreme Ethernet Controller"); - snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, - br != NULL ? "" : "unknown ", id); + "NetXtreme/NetLink Ethernet Controller"); + } + snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", + model, br != NULL ? "" : "unknown ", id); device_set_desc_copy(dev, buf); - return (0); + return (BUS_PROBE_DEFAULT); } t++; } @@ -2799,7 +3177,7 @@ bge_mbox_reorder(struct bge_softc *sc) const uint16_t vendor; const uint16_t device; const char *desc; - } const mbox_reorder_lists[] = { + } mbox_reorder_lists[] = { { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, }; devclass_t pci, pcib; @@ -2891,14 +3269,16 @@ bge_attach(device_t dev) { struct ifnet *ifp; struct bge_softc *sc; - uint32_t hwcfg = 0, misccfg; + uint32_t hwcfg = 0, misccfg, pcistate; u_char eaddr[ETHER_ADDR_LEN]; - int capmask, error, f, msicount, phy_addr, reg, rid, trys; + int capmask, error, msicount, reg, rid, trys; sc = device_get_softc(dev); sc->bge_dev = dev; + BGE_LOCK_INIT(sc, device_get_nameunit(dev)); TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); + callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); /* * Map control/status registers. @@ -2910,47 +3290,19 @@ bge_attach(device_t dev) RF_ACTIVE); if (sc->bge_res == NULL) { - device_printf (sc->bge_dev, "couldn't map memory\n"); + device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); error = ENXIO; goto fail; } /* Save various chip information. */ - sc->bge_chipid = - pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> - BGE_PCIMISCCTL_ASICREV_SHIFT; - if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { - /* - * Find the ASCI revision. Different chips use different - * registers. - */ - switch (pci_get_device(dev)) { - case BCOM_DEVICEID_BCM5717: - case BCOM_DEVICEID_BCM5718: - case BCOM_DEVICEID_BCM5719: - case BCOM_DEVICEID_BCM5720: - sc->bge_chipid = pci_read_config(dev, - BGE_PCI_GEN2_PRODID_ASICREV, 4); - break; - case BCOM_DEVICEID_BCM57761: - case BCOM_DEVICEID_BCM57765: - case BCOM_DEVICEID_BCM57781: - case BCOM_DEVICEID_BCM57785: - case BCOM_DEVICEID_BCM57791: - case BCOM_DEVICEID_BCM57795: - sc->bge_chipid = pci_read_config(dev, - BGE_PCI_GEN15_PRODID_ASICREV, 4); - break; - default: - sc->bge_chipid = pci_read_config(dev, - BGE_PCI_PRODID_ASICREV, 4); - } - } + sc->bge_func_addr = pci_get_function(dev); + sc->bge_chipid = bge_chipid(dev); sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); /* Set default PHY address. */ - phy_addr = 1; + sc->bge_phy_addr = 1; /* * PHY address mapping for various devices. * @@ -2962,48 +3314,47 @@ bge_attach(device_t dev) * BCM5719 | 1 | 8 | 2 | 9 | * BCM5720 | 1 | 8 | 2 | 9 | * + * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | + * ---------+-------+-------+-------+-------+ + * BCM57XX | X | X | X | X | + * BCM5704 | X | X | X | X | + * BCM5717 | X | X | X | X | + * BCM5719 | 3 | 10 | 4 | 11 | + * BCM5720 | X | X | X | X | + * * Other addresses may respond but they are not * IEEE compliant PHYs and should be ignored. */ if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || sc->bge_asicrev == BGE_ASICREV_BCM5719 || sc->bge_asicrev == BGE_ASICREV_BCM5720) { - f = pci_get_function(dev); - if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { + if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { if (CSR_READ_4(sc, BGE_SGDIG_STS) & BGE_SGDIGSTS_IS_SERDES) - phy_addr = f + 8; + sc->bge_phy_addr = sc->bge_func_addr + 8; else - phy_addr = f + 1; + sc->bge_phy_addr = sc->bge_func_addr + 1; } else { if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & BGE_CPMU_PHY_STRAP_IS_SERDES) - phy_addr = f + 8; + sc->bge_phy_addr = sc->bge_func_addr + 8; else - phy_addr = f + 1; + sc->bge_phy_addr = sc->bge_func_addr + 1; } } - /* - * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the - * 5705 A0 and A1 chips. - */ - if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || - (sc->bge_asicrev == BGE_ASICREV_BCM5705 && - (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && - sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || - sc->bge_asicrev == BGE_ASICREV_BCM5906) - sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; - if (bge_has_eaddr(sc)) sc->bge_flags |= BGE_FLAG_EADDR; /* Save chipset family. */ switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM57765: + case BGE_ASICREV_BCM57766: + sc->bge_flags |= BGE_FLAG_57765_PLUS; + /* FALLTHROUGH */ case BGE_ASICREV_BCM5717: case BGE_ASICREV_BCM5719: case BGE_ASICREV_BCM5720: - case BGE_ASICREV_BCM57765: sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | BGE_FLAG_JUMBO_FRAME; @@ -3043,41 +3394,42 @@ bge_attach(device_t dev) break; } + /* Identify chips with APE processor. */ + switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM5717: + case BGE_ASICREV_BCM5719: + case BGE_ASICREV_BCM5720: + case BGE_ASICREV_BCM5761: + sc->bge_flags |= BGE_FLAG_APE; + break; + } + + /* Chips with APE need BAR2 access for APE registers/memory. */ + if ((sc->bge_flags & BGE_FLAG_APE) != 0) { + rid = PCIR_BAR(2); + sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->bge_res2 == NULL) { + device_printf (sc->bge_dev, + "couldn't map BAR2 memory\n"); + error = ENXIO; + goto fail; + } + + /* Enable APE register/memory access by host driver. */ + pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); + pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | + BGE_PCISTATE_ALLOW_APE_SHMEM_WR | + BGE_PCISTATE_ALLOW_APE_PSPACE_WR; + pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); + + bge_ape_lock_init(sc); + bge_ape_read_fw_ver(sc); + } + /* Add SYSCTLs, requires the chipset family to be set. */ bge_add_sysctls(sc); - /* Set various PHY bug flags. */ - if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || - sc->bge_chipid == BGE_CHIPID_BCM5701_B0) - sc->bge_phy_flags |= BGE_PHY_CRC_BUG; - if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || - sc->bge_chiprev == BGE_CHIPREV_5704_AX) - sc->bge_phy_flags |= BGE_PHY_ADC_BUG; - if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) - sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; - if (pci_get_subvendor(dev) == DELL_VENDORID) - sc->bge_phy_flags |= BGE_PHY_NO_3LED; - if ((BGE_IS_5705_PLUS(sc)) && - sc->bge_asicrev != BGE_ASICREV_BCM5906 && - sc->bge_asicrev != BGE_ASICREV_BCM5717 && - sc->bge_asicrev != BGE_ASICREV_BCM5719 && - sc->bge_asicrev != BGE_ASICREV_BCM5720 && - sc->bge_asicrev != BGE_ASICREV_BCM5785 && - sc->bge_asicrev != BGE_ASICREV_BCM57765 && - sc->bge_asicrev != BGE_ASICREV_BCM57780) { - if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || - sc->bge_asicrev == BGE_ASICREV_BCM5761 || - sc->bge_asicrev == BGE_ASICREV_BCM5784 || - sc->bge_asicrev == BGE_ASICREV_BCM5787) { - if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && - pci_get_device(dev) != BCOM_DEVICEID_BCM5756) - sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; - if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) - sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; - } else - sc->bge_phy_flags |= BGE_PHY_BER_BUG; - } - /* Identify the chips that use an CPMU. */ if (BGE_IS_5717_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5784 || @@ -3135,9 +3487,12 @@ bge_attach(device_t dev) pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || + pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || + pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || sc->bge_asicrev == BGE_ASICREV_BCM5906) { /* These chips are 10/100 only. */ capmask &= ~BMSR_EXTSTAT; + sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; } /* @@ -3145,8 +3500,8 @@ bge_attach(device_t dev) * TSO. But the firmware is not available to FreeBSD and Linux * claims that the TSO performed by the firmware is slower than * hardware based TSO. Moreover the firmware based TSO has one - * known bug which can't handle TSO if ethernet header + IP/TCP - * header is greater than 80 bytes. The workaround for the TSO + * known bug which can't handle TSO if Ethernet header + IP/TCP + * header is greater than 80 bytes. A workaround for the TSO * bug exist but it seems it's too expensive than not using * TSO at all. Some hardwares also have the TSO bug so limit * the TSO to the controllers that are not affected TSO issues @@ -3182,11 +3537,16 @@ bge_attach(device_t dev) */ sc->bge_flags |= BGE_FLAG_PCIE; sc->bge_expcap = reg; + /* Extract supported maximum payload size. */ + sc->bge_mps = pci_read_config(dev, sc->bge_expcap + + PCIER_DEVICE_CAP, 2); + sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || sc->bge_asicrev == BGE_ASICREV_BCM5720) - pci_set_max_read_req(dev, 2048); - else if (pci_get_max_read_req(dev) != 4096) - pci_set_max_read_req(dev, 4096); + sc->bge_expmrq = 2048; + else + sc->bge_expmrq = 4096; + pci_set_max_read_req(dev, sc->bge_expmrq); } else { /* * Check if the device is in PCI-X Mode. @@ -3257,38 +3617,31 @@ bge_attach(device_t dev) bge_devinfo(sc); - BGE_LOCK_INIT(sc, device_get_nameunit(dev)); - - /* Try to reset the chip. */ - if (bge_reset(sc)) { - device_printf(sc->bge_dev, "chip reset failed\n"); - error = ENXIO; - goto fail; - } - sc->bge_asf_mode = 0; - if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == - BGE_SRAM_DATA_SIG_MAGIC)) { - if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) - & BGE_HWCFG_ASF) { - sc->bge_asf_mode |= ASF_ENABLE; - sc->bge_asf_mode |= ASF_STACKUP; - if (BGE_IS_575X_PLUS(sc)) - sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; + /* No ASF if APE present. */ + if ((sc->bge_flags & BGE_FLAG_APE) == 0) { + if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == + BGE_SRAM_DATA_SIG_MAGIC)) { + if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & + BGE_HWCFG_ASF) { + sc->bge_asf_mode |= ASF_ENABLE; + sc->bge_asf_mode |= ASF_STACKUP; + if (BGE_IS_575X_PLUS(sc)) + sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; + } } } - /* Try to reset the chip again the nice way. */ bge_stop_fw(sc); - bge_sig_pre_reset(sc, BGE_RESET_STOP); + bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); if (bge_reset(sc)) { device_printf(sc->bge_dev, "chip reset failed\n"); error = ENXIO; goto fail; } - bge_sig_legacy(sc, BGE_RESET_STOP); - bge_sig_post_reset(sc, BGE_RESET_STOP); + bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); + bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); if (bge_chipinit(sc)) { device_printf(sc->bge_dev, "chip initialization failed\n"); @@ -3397,12 +3750,52 @@ bge_attach(device_t dev) /* The SysKonnect SK-9D41 is a 1000baseSX card. */ if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { - if (BGE_IS_5714_FAMILY(sc)) + if (BGE_IS_5705_PLUS(sc)) { sc->bge_flags |= BGE_FLAG_MII_SERDES; - else + sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; + } else sc->bge_flags |= BGE_FLAG_TBI; } + /* Set various PHY bug flags. */ + if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || + sc->bge_chipid == BGE_CHIPID_BCM5701_B0) + sc->bge_phy_flags |= BGE_PHY_CRC_BUG; + if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || + sc->bge_chiprev == BGE_CHIPREV_5704_AX) + sc->bge_phy_flags |= BGE_PHY_ADC_BUG; + if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) + sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; + if (pci_get_subvendor(dev) == DELL_VENDORID) + sc->bge_phy_flags |= BGE_PHY_NO_3LED; + if ((BGE_IS_5705_PLUS(sc)) && + sc->bge_asicrev != BGE_ASICREV_BCM5906 && + sc->bge_asicrev != BGE_ASICREV_BCM5785 && + sc->bge_asicrev != BGE_ASICREV_BCM57780 && + !BGE_IS_5717_PLUS(sc)) { + if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || + sc->bge_asicrev == BGE_ASICREV_BCM5761 || + sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5787) { + if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && + pci_get_device(dev) != BCOM_DEVICEID_BCM5756) + sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; + if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) + sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; + } else + sc->bge_phy_flags |= BGE_PHY_BER_BUG; + } + + /* + * Don't enable Ethernet@WireSpeed for the 5700 or the + * 5705 A0 and A1 chips. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + (sc->bge_asicrev == BGE_ASICREV_BCM5705 && + (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && + sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) + sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; + if (sc->bge_flags & BGE_FLAG_TBI) { ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, bge_ifmedia_sts); @@ -3426,13 +3819,13 @@ again: bge_asf_driver_up(sc); error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, - bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, + bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); if (error != 0) { if (trys++ < 4) { device_printf(sc->bge_dev, "Try again\n"); - bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, - BMCR_RESET); + bge_miibus_writereg(sc->bge_dev, + sc->bge_phy_addr, MII_BMCR, BMCR_RESET); goto again; } device_printf(sc->bge_dev, "attaching PHYs failed\n"); @@ -3462,7 +3855,6 @@ again: * Call MI attach routine. */ ether_ifattach(ifp, eaddr); - callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); /* Tell upper layer we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); @@ -3479,31 +3871,32 @@ again: if (sc->bge_tq == NULL) { device_printf(dev, "could not create taskqueue.\n"); ether_ifdetach(ifp); - error = ENXIO; + error = ENOMEM; + goto fail; + } + error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, + "%s taskq", device_get_nameunit(sc->bge_dev)); + if (error != 0) { + device_printf(dev, "could not start threads.\n"); + ether_ifdetach(ifp); goto fail; } - taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", - device_get_nameunit(sc->bge_dev)); error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, &sc->bge_intrhand); - if (error) - ether_ifdetach(ifp); } else error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, &sc->bge_intrhand); if (error) { - bge_detach(dev); + ether_ifdetach(ifp); device_printf(sc->bge_dev, "couldn't set up irq\n"); } - return (0); - fail: - bge_release_resources(sc); - + if (error) + bge_detach(dev); return (error); } @@ -3521,20 +3914,20 @@ bge_detach(device_t dev) ether_poll_deregister(ifp); #endif - BGE_LOCK(sc); - bge_stop(sc); - bge_reset(sc); - BGE_UNLOCK(sc); - - callout_drain(&sc->bge_stat_ch); + if (device_is_attached(dev)) { + ether_ifdetach(ifp); + BGE_LOCK(sc); + bge_stop(sc); + BGE_UNLOCK(sc); + callout_drain(&sc->bge_stat_ch); + } if (sc->bge_tq) taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); - ether_ifdetach(ifp); - if (sc->bge_flags & BGE_FLAG_TBI) { + if (sc->bge_flags & BGE_FLAG_TBI) ifmedia_removeall(&sc->bge_ifmedia); - } else { + else if (sc->bge_miibus != NULL) { bus_generic_detach(dev); device_delete_child(dev, sc->bge_miibus); } @@ -3568,6 +3961,10 @@ bge_release_resources(struct bge_softc *sc) bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bge_res); + if (sc->bge_res2 != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + PCIR_BAR(2), sc->bge_res2); + if (sc->bge_ifp != NULL) if_free(sc->bge_ifp); @@ -3581,13 +3978,18 @@ static int bge_reset(struct bge_softc *sc) { device_t dev; - uint32_t cachesize, command, pcistate, reset, val; + uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; void (*write_op)(struct bge_softc *, int, int); uint16_t devctl; int i; dev = sc->bge_dev; + mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) + mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; + mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; + if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { if (sc->bge_flags & BGE_FLAG_PCIE) @@ -3597,10 +3999,26 @@ bge_reset(struct bge_softc *sc) } else write_op = bge_writereg_ind; + if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && + sc->bge_asicrev != BGE_ASICREV_BCM5701) { + CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); + for (i = 0; i < 8000; i++) { + if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & + BGE_NVRAMSWARB_GNT1) + break; + DELAY(20); + } + if (i == 8000) { + if (bootverbose) + device_printf(dev, "NVRAM lock timedout!\n"); + } + } + /* Take APE lock when performing reset. */ + bge_ape_lock(sc, BGE_APE_LOCK_GRC); + /* Save some important PCI state. */ cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); command = pci_read_config(dev, BGE_PCI_CMD, 4); - pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); pci_write_config(dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | @@ -3625,8 +4043,11 @@ bge_reset(struct bge_softc *sc) /* XXX: Broadcom Linux driver. */ if (sc->bge_flags & BGE_FLAG_PCIE) { - if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ - CSR_WRITE_4(sc, 0x7E2C, 0x20); + if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && + (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { + if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ + CSR_WRITE_4(sc, 0x7E2C, 0x20); + } if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { /* Prevent PCIE link training during global reset */ CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); @@ -3634,6 +4055,15 @@ bge_reset(struct bge_softc *sc) } } + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + val = CSR_READ_4(sc, BGE_VCPU_STATUS); + CSR_WRITE_4(sc, BGE_VCPU_STATUS, + val | BGE_VCPU_STATUS_DRV_RESET); + val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); + CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, + val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); + } + /* * Set GPHY Power Down Override to leave GPHY * powered up in D0 uninitialized. @@ -3645,16 +4075,10 @@ bge_reset(struct bge_softc *sc) /* Issue global reset */ write_op(sc, BGE_MISC_CFG, reset); - if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { - val = CSR_READ_4(sc, BGE_VCPU_STATUS); - CSR_WRITE_4(sc, BGE_VCPU_STATUS, - val | BGE_VCPU_STATUS_DRV_RESET); - val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); - CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, - val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); - } - - DELAY(1000); + if (sc->bge_flags & BGE_FLAG_PCIE) + DELAY(100 * 1000); + else + DELAY(1000); /* XXX: Broadcom Linux driver. */ if (sc->bge_flags & BGE_FLAG_PCIE) { @@ -3664,26 +4088,35 @@ bge_reset(struct bge_softc *sc) pci_write_config(dev, 0xC4, val | (1 << 15), 4); } devctl = pci_read_config(dev, - sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); + sc->bge_expcap + PCIER_DEVICE_CTL, 2); /* Clear enable no snoop and disable relaxed ordering. */ - devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | - PCIM_EXP_CTL_NOSNOOP_ENABLE); - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, + devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | + PCIEM_CTL_NOSNOOP_ENABLE); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, devctl, 2); + pci_set_max_read_req(dev, sc->bge_expmrq); /* Clear error status. */ - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, - PCIM_EXP_STA_CORRECTABLE_ERROR | - PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | - PCIM_EXP_STA_UNSUPPORTED_REQ, 2); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, + PCIEM_STA_CORRECTABLE_ERROR | + PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | + PCIEM_STA_UNSUPPORTED_REQ, 2); } /* Reset some of the PCI state that got zapped by reset. */ pci_write_config(dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); + val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; + if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && + (sc->bge_flags & BGE_FLAG_PCIX) != 0) + val |= BGE_PCISTATE_RETRY_SAME_DMA; + if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) + val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | + BGE_PCISTATE_ALLOW_APE_SHMEM_WR | + BGE_PCISTATE_ALLOW_APE_PSPACE_WR; + pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); pci_write_config(dev, BGE_PCI_CMD, command, 4); - write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); /* * Disable PCI-X relaxed ordering to ensure status block update * comes first then packet buffer DMA. Otherwise driver may @@ -3722,6 +4155,16 @@ bge_reset(struct bge_softc *sc) } else CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + /* Fix up byte swapping. */ + CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); + + val = CSR_READ_4(sc, BGE_MAC_MODE); + val = (val & ~mac_mode_mask) | mac_mode; + CSR_WRITE_4(sc, BGE_MAC_MODE, val); + DELAY(40); + + bge_ape_unlock(sc, BGE_APE_LOCK_GRC); + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { for (i = 0; i < BGE_TIMEOUT; i++) { val = CSR_READ_4(sc, BGE_VCPU_STATUS); @@ -3756,29 +4199,6 @@ bge_reset(struct bge_softc *sc) DELAY(10 * 1000); /* XXX */ } - /* - * XXX Wait for the value of the PCISTATE register to - * return to its original pre-reset state. This is a - * fairly good indicator of reset completion. If we don't - * wait for the reset to fully complete, trying to read - * from the device's non-PCI registers may yield garbage - * results. - */ - for (i = 0; i < BGE_TIMEOUT; i++) { - if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) - break; - DELAY(10); - } - - /* Fix up byte swapping. */ - CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); - - /* Tell the ASF firmware we are up */ - if (sc->bge_asf_mode & ASF_STACKUP) - BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); - - CSR_WRITE_4(sc, BGE_MAC_MODE, 0); - /* * The 5704 in TBI mode apparently needs some special * adjustment to insure the SERDES drive level is set @@ -3800,7 +4220,6 @@ bge_reset(struct bge_softc *sc) val = CSR_READ_4(sc, 0x7C00); CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); } - DELAY(10000); if (sc->bge_asicrev == BGE_ASICREV_BCM5720) BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, @@ -4090,10 +4509,12 @@ bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) bus_dmamap_sync(sc->bge_cdata.bge_status_tag, sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + /* Fetch updates from the status block. */ rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; statusword = sc->bge_ldata.bge_status_block->bge_status; + /* Clear the status so the next pass only sees the changes. */ sc->bge_ldata.bge_status_block->bge_status = 0; bus_dmamap_sync(sc->bge_cdata.bge_status_tag, @@ -4161,11 +4582,12 @@ bge_intr_task(void *arg, int pending) sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - /* Save producer/consumer indexess. */ + /* Save producer/consumer indices. */ rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; status = sc->bge_ldata.bge_status_block->bge_status; status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; + /* Dirty the status flag. */ sc->bge_ldata.bge_status_block->bge_status = 0; bus_dmamap_sync(sc->bge_cdata.bge_status_tag, sc->bge_cdata.bge_status_map, @@ -4315,6 +4737,8 @@ bge_tick(void *xsc) else bge_stats_update(sc); + /* XXX Add APE heartbeat check here? */ + if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { mii = device_get_softc(sc->bge_miibus); /* @@ -4562,7 +4986,7 @@ bge_cksum_pad(struct mbuf *m) /* Allocate new empty mbuf, pad it. Compact later. */ struct mbuf *n; - MGET(n, M_DONTWAIT, MT_DATA); + MGET(n, M_NOWAIT, MT_DATA); if (n == NULL) return (ENOBUFS); n->m_len = 0; @@ -4604,7 +5028,7 @@ bge_check_short_dma(struct mbuf *m) } if (found > 1) { - n = m_defrag(m, M_DONTWAIT); + n = m_defrag(m, M_NOWAIT); if (n == NULL) m_freem(m); } else @@ -4624,7 +5048,7 @@ bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - n = m_dup(m, M_DONTWAIT); + n = m_dup(m, M_NOWAIT); m_freem(m); if (n == NULL) return (NULL); @@ -4727,10 +5151,6 @@ bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) return (error); } } - if (m->m_flags & M_LASTFRAG) - csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; - else if (m->m_flags & M_FRAG) - csum_flags |= BGE_TXBDFLAG_IP_FRAG; } if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { @@ -4745,9 +5165,9 @@ bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) * DMA read operation. */ if (sc->bge_forced_collapse == 1) - m = m_defrag(m, M_DONTWAIT); + m = m_defrag(m, M_NOWAIT); else - m = m_collapse(m, M_DONTWAIT, + m = m_collapse(m, M_NOWAIT, sc->bge_forced_collapse); if (m == NULL) m = *m_head; @@ -4759,7 +5179,7 @@ bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, &nsegs, BUS_DMA_NOWAIT); if (error == EFBIG) { - m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); + m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -4851,29 +5271,6 @@ bge_start_locked(struct ifnet *ifp) if (m_head == NULL) break; - /* - * XXX - * The code inside the if() block is never reached since we - * must mark CSUM_IP_FRAGS in our if_hwassist to start getting - * requests to checksum TCP/UDP in a fragmented packet. - * - * XXX - * safety overkill. If this is a fragmented packet chain - * with delayed TCP/UDP checksums, then only encapsulate - * it if we have enough descriptors to handle the entire - * chain at once. - * (paranoia -- may not actually be needed) - */ - if (m_head->m_flags & M_FIRSTFRAG && - m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { - if ((BGE_TX_RING_CNT - sc->bge_txcnt) < - m_head->m_pkthdr.csum_data + 16) { - IFQ_DRV_PREPEND(&ifp->if_snd, m_head); - ifp->if_drv_flags |= IFF_DRV_OACTIVE; - break; - } - } - /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait @@ -4913,7 +5310,7 @@ bge_start_locked(struct ifnet *ifp) /* * Set a timeout in case the chip goes out to lunch. */ - sc->bge_timer = 5; + sc->bge_timer = BGE_TX_TIMEOUT; } } @@ -5055,9 +5452,14 @@ bge_init_locked(struct bge_softc *sc) } /* Turn on transmitter. */ CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); + DELAY(100); /* Turn on receiver. */ - BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + mode = CSR_READ_4(sc, BGE_RX_MODE); + if (BGE_IS_5755_PLUS(sc)) + mode |= BGE_RXMODE_IPV6_ENABLE; + CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); + DELAY(10); /* * Set the number of good frames to receive after RX MBUF @@ -5065,7 +5467,7 @@ bge_init_locked(struct bge_softc *sc) * this number of frames, it will drop subsequent incoming * frames until the MBUF High Watermark is reached. */ - if (sc->bge_asicrev == BGE_ASICREV_BCM57765) + if (BGE_IS_57765_PLUS(sc)) CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); else CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); @@ -5093,11 +5495,11 @@ bge_init_locked(struct bge_softc *sc) bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); } - bge_ifmedia_upd_locked(ifp); - ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + bge_ifmedia_upd_locked(ifp); + callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); } @@ -5174,6 +5576,7 @@ bge_ifmedia_upd_locked(struct ifnet *ifp) BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); } + DELAY(40); break; default: return (EINVAL); @@ -5219,6 +5622,10 @@ bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) BGE_LOCK(sc); + if ((ifp->if_flags & IFF_UP) == 0) { + BGE_UNLOCK(sc); + return; + } if (sc->bge_flags & BGE_FLAG_TBI) { ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; @@ -5408,12 +5815,40 @@ static void bge_watchdog(struct bge_softc *sc) { struct ifnet *ifp; + uint32_t status; BGE_LOCK_ASSERT(sc); if (sc->bge_timer == 0 || --sc->bge_timer) return; + /* If pause frames are active then don't reset the hardware. */ + if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { + status = CSR_READ_4(sc, BGE_RX_STS); + if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { + /* + * If link partner has us in XOFF state then wait for + * the condition to clear. + */ + CSR_WRITE_4(sc, BGE_RX_STS, status); + sc->bge_timer = BGE_TX_TIMEOUT; + return; + } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && + (status & BGE_RXSTAT_RCVD_XON) != 0) { + /* + * If link partner has us in XOFF state then wait for + * the condition to clear. + */ + CSR_WRITE_4(sc, BGE_RX_STS, status); + sc->bge_timer = BGE_TX_TIMEOUT; + return; + } + /* + * Any other condition is unexpected and the controller + * should be reset. + */ + } + ifp = sc->bge_ifp; if_printf(ifp, "watchdog timeout -- resetting\n"); @@ -5461,7 +5896,7 @@ bge_stop(struct bge_softc *sc) * Tell firmware we're shutting down. */ bge_stop_fw(sc); - bge_sig_pre_reset(sc, BGE_RESET_STOP); + bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); /* * Disable all of the receiver blocks. @@ -5507,8 +5942,8 @@ bge_stop(struct bge_softc *sc) bge_stats_update_regs(sc); bge_reset(sc); - bge_sig_legacy(sc, BGE_RESET_STOP); - bge_sig_post_reset(sc, BGE_RESET_STOP); + bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); + bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); /* * Keep the ASF firmware running if up. @@ -5550,7 +5985,6 @@ bge_shutdown(device_t dev) sc = device_get_softc(dev); BGE_LOCK(sc); bge_stop(sc); - bge_reset(sc); BGE_UNLOCK(sc); return (0); @@ -5637,9 +6071,10 @@ bge_link_upd(struct bge_softc *sc) /* Clear the interrupt. */ CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT); - bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); - bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, - BRGPHY_INTRS); + bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, + BRGPHY_MII_ISR); + bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, + BRGPHY_MII_IMR, BRGPHY_INTRS); } return; } @@ -5649,9 +6084,11 @@ bge_link_upd(struct bge_softc *sc) if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { if (!sc->bge_link) { sc->bge_link++; - if (sc->bge_asicrev == BGE_ASICREV_BCM5704) + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_TBI_SEND_CFGS); + DELAY(40); + } CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); if (bootverbose) if_printf(sc->bge_ifp, "link UP\n"); @@ -5700,7 +6137,7 @@ bge_link_upd(struct bge_softc *sc) bge_miibus_statchg(sc->bge_dev); } - /* Clear the attention. */ + /* Disable MAC attention when link is up. */ CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | BGE_MACSTAT_LINK_CHANGED); @@ -5724,7 +6161,11 @@ bge_add_sysctls(struct bge_softc *sc) SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", - "Register Read"); + "MAC Register Read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", + "APE Register Read"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", @@ -6122,6 +6563,28 @@ bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) return (error); } +static int +bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + int error; + uint16_t result; + uint32_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result < 0x8000) { + sc = (struct bge_softc *)arg1; + val = APE_READ_4(sc, result); + printf("reg 0x%06X = 0x%08X\n", result, val); + } + + return (error); +} + static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) { diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h index 4413775d56..50e6f4592d 100644 --- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h +++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/bge/if_bgereg.h @@ -360,6 +360,7 @@ #define BGE_ASICREV_BCM5784 0x5784 #define BGE_ASICREV_BCM5785 0x5785 #define BGE_ASICREV_BCM57765 0x57785 +#define BGE_ASICREV_BCM57766 0x57766 #define BGE_ASICREV_BCM57780 0x57780 /* chip revisions */ @@ -430,10 +431,14 @@ #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ -#define BGE_PCISTATE_WANT_EXPROM 0x00000020 -#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 +#define BGE_PCISTATE_ROM_ENABLE 0x00000020 +#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 +#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 +#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 +#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 +#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 /* * PCI Clock Control register -- note, this register is read only @@ -459,6 +464,8 @@ #define PCIM_CMD_INTxDIS 0x0400 #endif +/* BAR0 (MAC) Register Definitions */ + /* * High priority mailbox registers * Each mailbox is 64-bits wide, though we only use the @@ -741,6 +748,8 @@ #define BGE_MACMODE_TXDMA_ENB 0x00200000 #define BGE_MACMODE_RXDMA_ENB 0x00400000 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 +#define BGE_MACMODE_APE_RX_EN 0x08000000 +#define BGE_MACMODE_APE_TX_EN 0x10000000 #define BGE_PORTMODE_NONE 0x00000000 #define BGE_PORTMODE_MII 0x00000004 @@ -788,7 +797,7 @@ #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 /* TX backoff seed register */ -#define BGE_TX_BACKOFF_SEED_MASK 0x3F +#define BGE_TX_BACKOFF_SEED_MASK 0x3FF /* Autopoll status register */ #define BGE_AUTOPOLLSTS_ERROR 0x00000001 @@ -828,6 +837,7 @@ #define BGE_RXMODE_RX_PROMISC 0x00000100 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 +#define BGE_RXMODE_IPV6_ENABLE 0x01000000 /* Receive MAC status register */ #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 @@ -1577,6 +1587,22 @@ #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 +/* BD Read DMA Mode register */ +#define BGE_RDMA_BD_MODE 0x4A00 +/* BD Read DMA Mode status register */ +#define BGE_RDMA_BD_STATUS 0x4A04 + +#define BGE_RDMA_BD_MODE_RESET 0x00000001 +#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 + +/* Non-LSO Read DMA Mode register */ +#define BGE_RDMA_NON_LSO_MODE 0x4B00 +/* Non-LSO Read DMA Mode status register */ +#define BGE_RDMA_NON_LSO_STATUS 0x4B04 + +#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 +#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 + /* * Write DMA control registers */ @@ -2064,6 +2090,112 @@ #define BGE_MEMWIN_START 0x00008000 #define BGE_MEMWIN_END 0x0000FFFF +/* BAR1 (APE) Register Definitions */ + +#define BGE_APE_GPIO_MSG 0x0008 +#define BGE_APE_EVENT 0x000C +#define BGE_APE_LOCK_REQ 0x002C +#define BGE_APE_LOCK_GRANT 0x004C + +#define BGE_APE_GPIO_MSG_SHIFT 4 + +#define BGE_APE_EVENT_1 0x00000001 + +#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 + +#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 + +/* APE Shared Memory block (writable by APE only) */ +#define BGE_APE_SEG_SIG 0x4000 +#define BGE_APE_FW_STATUS 0x400C +#define BGE_APE_FW_FEATURES 0x4010 +#define BGE_APE_FW_BEHAVIOR 0x4014 +#define BGE_APE_FW_VERSION 0x4018 +#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 +#define BGE_APE_FW_HEARTBEAT 0x4028 +#define BGE_APE_FW_ERROR_FLAGS 0x4074 + +#define BGE_APE_SEG_SIG_MAGIC 0x41504521 + +#define BGE_APE_FW_STATUS_READY 0x00000100 + +#define BGE_APE_FW_FEATURE_DASH 0x00000001 +#define BGE_APE_FW_FEATURE_NCSI 0x00000002 + +#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 +#define BGE_APE_FW_VERSION_MAJSFT 24 +#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 +#define BGE_APE_FW_VERSION_MINSFT 16 +#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 +#define BGE_APE_FW_VERSION_REVSFT 8 +#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF + +/* Host Shared Memory block (writable by host only) */ +#define BGE_APE_HOST_SEG_SIG 0x4200 +#define BGE_APE_HOST_SEG_LEN 0x4204 +#define BGE_APE_HOST_INIT_COUNT 0x4208 +#define BGE_APE_HOST_DRIVER_ID 0x420C +#define BGE_APE_HOST_BEHAVIOR 0x4210 +#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 +#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 +#define BGE_APE_HOST_DRVR_STATE 0x421C +#define BGE_APE_HOST_WOL_SPEED 0x4224 + +#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 + +#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 + +#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 +#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ + (BGE_APE_HOST_DRIVER_ID_FBSD | \ + ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) + +#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 + +#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 +#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 + +#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 +#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 +#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 +#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 + +#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 + +#define BGE_APE_EVENT_STATUS 0x4300 + +#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 +#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 +#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 +#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 +#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 +#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 +#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 + +#define BGE_APE_DEBUG_LOG 0x4E00 +#define BGE_APE_DEBUG_LOG_LEN 0x0100 + +#define BGE_APE_PER_LOCK_REQ 0x8400 +#define BGE_APE_PER_LOCK_GRANT 0x8420 + +#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 +#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 +#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 +#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 + +#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 +#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 +#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 +#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 + +/* APE Mutex Resources */ +#define BGE_APE_LOCK_PHY0 0 +#define BGE_APE_LOCK_GRC 1 +#define BGE_APE_LOCK_PHY1 2 +#define BGE_APE_LOCK_PHY2 3 +#define BGE_APE_LOCK_MEM 4 +#define BGE_APE_LOCK_PHY3 5 +#define BGE_APE_LOCK_GPIO 7 #define BGE_MEMWIN_READ(sc, x, val) \ do { \ @@ -2352,7 +2484,9 @@ struct bge_status_block { #define BCOM_DEVICEID_BCM5906M 0x1713 #define BCOM_DEVICEID_BCM57760 0x1690 #define BCOM_DEVICEID_BCM57761 0x16B0 +#define BCOM_DEVICEID_BCM57762 0x1682 #define BCOM_DEVICEID_BCM57765 0x16B4 +#define BCOM_DEVICEID_BCM57766 0x1686 #define BCOM_DEVICEID_BCM57780 0x1692 #define BCOM_DEVICEID_BCM57781 0x16B1 #define BCOM_DEVICEID_BCM57785 0x16B5 @@ -2658,7 +2792,7 @@ struct bge_gib { #define BGE_INC(x, y) (x) = (x + 1) % y /* - * Register access macros. The Tigon always uses memory mapped register + * BAR0 MAC register access macros. The Tigon always uses memory mapped register * accesses and all registers must be accessed with 32 bit operations. */ @@ -2673,6 +2807,18 @@ struct bge_gib { #define BGE_CLRBIT(sc, reg, x) \ CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) +/* BAR2 APE register access macros. */ +#define APE_WRITE_4(sc, reg, val) \ + bus_write_4(sc->bge_res2, reg, val) + +#define APE_READ_4(sc, reg) \ + bus_read_4(sc->bge_res2, reg) + +#define APE_SETBIT(sc, reg, x) \ + APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) +#define APE_CLRBIT(sc, reg, x) \ + APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) + #define PCI_SETBIT(dev, reg, x, s) \ pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) #define PCI_CLRBIT(dev, reg, x, s) \ @@ -2782,6 +2928,7 @@ struct bge_dmamap_arg { #define BGE_HWREV_TIGON_II 0x02 #define BGE_TIMEOUT 100000 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ +#define BGE_TX_TIMEOUT 5 struct bge_bcom_hack { int reg; @@ -2799,9 +2946,11 @@ struct bge_softc { device_t bge_miibus; void *bge_intrhand; struct resource *bge_irq; - struct resource *bge_res; + struct resource *bge_res; /* MAC mapped I/O */ + struct resource *bge_res2; /* APE mapped I/O */ struct ifmedia bge_ifmedia; /* TBI media info */ int bge_expcap; + int bge_expmrq; int bge_msicap; int bge_pcixcap; uint32_t bge_flags; @@ -2812,6 +2961,7 @@ struct bge_softc { #define BGE_FLAG_MII_SERDES 0x00000010 #define BGE_FLAG_CPMU_PRESENT 0x00000020 #define BGE_FLAG_TAGGED_STATUS 0x00000040 +#define BGE_FLAG_APE 0x00000080 #define BGE_FLAG_MSI 0x00000100 #define BGE_FLAG_PCIX 0x00000200 #define BGE_FLAG_PCIE 0x00000400 @@ -2825,12 +2975,21 @@ struct bge_softc { #define BGE_FLAG_5755_PLUS 0x00100000 #define BGE_FLAG_5788 0x00200000 #define BGE_FLAG_5717_PLUS 0x00400000 +#define BGE_FLAG_57765_PLUS 0x00800000 #define BGE_FLAG_40BIT_BUG 0x01000000 #define BGE_FLAG_4G_BNDRY_BUG 0x02000000 #define BGE_FLAG_RX_ALIGNBUG 0x04000000 #define BGE_FLAG_SHORT_DMA_BUG 0x08000000 #define BGE_FLAG_4K_RDMA_BUG 0x10000000 #define BGE_FLAG_MBOX_REORDER 0x20000000 + uint32_t bge_mfw_flags; /* Management F/W flags */ +#define BGE_MFW_ON_RXCPU 0x00000001 +#define BGE_MFW_ON_APE 0x00000002 +#define BGE_MFW_TYPE_NCSI 0x00000004 +#define BGE_MFW_TYPE_DASH 0x00000008 + int bge_phy_ape_lock; + int bge_func_addr; + int bge_phy_addr; uint32_t bge_phy_flags; #define BGE_PHY_NO_WIRESPEED 0x00000001 #define BGE_PHY_ADC_BUG 0x00000002 @@ -2845,6 +3004,7 @@ struct bge_softc { uint32_t bge_chiprev; uint8_t bge_asf_mode; uint8_t bge_asf_count; + uint16_t bge_mps; struct bge_ring_data bge_ldata; /* rings */ struct bge_chain_data bge_cdata; /* mbufs */ uint16_t bge_tx_saved_considx; diff --git a/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c b/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c index 57646e56bd..be4276c45a 100644 --- a/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c +++ b/src/add-ons/kernel/drivers/network/broadcom570x/dev/mii/brgphy.c @@ -204,6 +204,13 @@ brgphy_attach(device_t dev) &brgphy_funcs, 0); bsc->serdes_flags = 0; + ifp = sc->mii_pdata->mii_ifp; + + /* Find the MAC driver associated with this PHY. */ + if (strcmp(ifp->if_dname, "bge") == 0) + bge_sc = ifp->if_softc; + else if (strcmp(ifp->if_dname, "bce") == 0) + bce_sc = ifp->if_softc; /* Handle any special cases based on the PHY ID */ switch (sc->mii_mpd_oui) { @@ -235,22 +242,21 @@ brgphy_attach(device_t dev) sc->mii_flags |= MIIF_HAVEFIBER; break; case MII_MODEL_BROADCOM2_BCM5709S: - bsc->serdes_flags |= BRGPHY_5709S; + /* + * XXX + * 5720S and 5709S shares the same PHY id. + * Assume 5720S PHY if parent device is bge(4). + */ + if (bge_sc != NULL) + bsc->serdes_flags |= BRGPHY_5708S; + else + bsc->serdes_flags |= BRGPHY_5709S; sc->mii_flags |= MIIF_HAVEFIBER; break; } break; } - ifp = sc->mii_pdata->mii_ifp; - - /* Find the MAC driver associated with this PHY. */ - if (strcmp(ifp->if_dname, "bge") == 0) { - bge_sc = ifp->if_softc; - } else if (strcmp(ifp->if_dname, "bce") == 0) { - bce_sc = ifp->if_softc; - } - PHY_RESET(sc); /* Read the PHY's capabilities. */ @@ -608,6 +614,11 @@ brgphy_mii_phy_auto(struct mii_softc *sc, int media) (sc->mii_flags & MIIF_FORCEPAUSE) != 0) anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); + ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; + if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) + ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; + PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); + PHY_READ(sc, BRGPHY_MII_1000CTL); } else { anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; if ((media & IFM_FLOW) != 0 || @@ -616,12 +627,6 @@ brgphy_mii_phy_auto(struct mii_softc *sc, int media) PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); } - ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; - if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) - ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; - PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); - ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); - PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); @@ -918,6 +923,15 @@ brgphy_reset(struct mii_softc *sc) break; } break; + case MII_OUI_BROADCOM3: + switch (sc->mii_mpd_model) { + case MII_MODEL_BROADCOM3_BCM5717C: + case MII_MODEL_BROADCOM3_BCM5719C: + case MII_MODEL_BROADCOM3_BCM5720C: + case MII_MODEL_BROADCOM3_BCM57765: + return; + } + break; } ifp = sc->mii_pdata->mii_ifp; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c index 41d9ea3079..5566ad2ef9 100644 --- a/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/dc/if_dc.c @@ -150,7 +150,7 @@ MODULE_DEPEND(dc, miibus, 1, 1, 1); /* * Various supported device vendors/types and their names. */ -static const struct dc_type const dc_devs[] = { +static const struct dc_type dc_devs[] = { { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, "Intel 21143 10/100BaseTX" }, { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, @@ -2650,7 +2650,7 @@ dc_newbuf(struct dc_softc *sc, int i) bus_dma_segment_t segs[1]; int error, nseg; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; @@ -3387,7 +3387,7 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head) defragged = 0; if (sc->dc_flags & DC_TX_COALESCE && ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); defragged = 1; } else { /* @@ -3402,7 +3402,7 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head) if (i > DC_TX_LIST_CNT / 4 || DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) { - m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); + m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); defragged = 1; } } @@ -3419,7 +3419,7 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); if (error == EFBIG) { - if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, + if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS)) == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/dec21xxx/dev/de/if_de.c b/src/add-ons/kernel/drivers/network/dec21xxx/dev/de/if_de.c index 9848c9d353..68d6fe8860 100644 --- a/src/add-ons/kernel/drivers/network/dec21xxx/dev/de/if_de.c +++ b/src/add-ons/kernel/drivers/network/dec21xxx/dev/de/if_de.c @@ -261,7 +261,7 @@ tulip_txprobe(tulip_softc_t * const sc) * to verify the connectivity. */ TULIP_LOCK_ASSERT(sc); - MGETHDR(m, M_DONTWAIT, MT_DATA); + MGETHDR(m, M_NOWAIT, MT_DATA); if (m == NULL) return 0; /* @@ -3521,7 +3521,7 @@ tulip_rx_intr(tulip_softc_t * const sc) ms->m_pkthdr.len = total_len; ms->m_pkthdr.rcvif = ifp; m0 = ms; - ms = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + ms = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); #endif TULIP_UNLOCK(sc); CTR1(KTR_TULIP, "tulip_rx_intr: passing %p to upper layer", m0); @@ -3532,7 +3532,7 @@ tulip_rx_intr(tulip_softc_t * const sc) * If we are priming the TULIP with mbufs, then allocate * a new cluster for the next descriptor. */ - ms = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + ms = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); #ifndef __NO_STRICT_ALIGNMENT skip_input: @@ -3974,7 +3974,7 @@ tulip_txput(tulip_softc_t * const sc, struct mbuf *m) * to recopy it into one mbuf and then try again. If * we can't recopy it, try again later. */ - m0 = m_defrag(m, M_DONTWAIT); + m0 = m_defrag(m, M_NOWAIT); if (m0 == NULL) { sc->tulip_flags |= TULIP_WANTTXSTART; #if defined(TULIP_DEBUG) diff --git a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c index bcbfe1bddb..36581abd47 100644 --- a/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c +++ b/src/add-ons/kernel/drivers/network/ipro100/dev/fxp/if_fxp.c @@ -111,7 +111,7 @@ static int tx_threshold = 64; * * See struct fxp_cb_config for the bit definitions. */ -static const u_char const fxp_cb_config_template[] = { +static const u_char fxp_cb_config_template[] = { 0x0, 0x0, /* cb_status */ 0x0, 0x0, /* cb_command */ 0x0, 0x0, 0x0, 0x0, /* link_addr */ @@ -155,7 +155,7 @@ static const u_char const fxp_cb_config_template[] = { * particular variants, but we don't currently differentiate between * them. */ -static const struct fxp_ident const fxp_ident_table[] = { +static const struct fxp_ident fxp_ident_table[] = { { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, @@ -452,7 +452,6 @@ fxp_attach(device_t dev) * Enable bus mastering. */ pci_enable_busmaster(dev); - val = pci_read_config(dev, PCIR_COMMAND, 2); /* * Figure out which we should try first - memory mapping or i/o mapping? @@ -610,6 +609,7 @@ fxp_attach(device_t dev) * is a valid cacheline size (8 or 16 dwords), then tell * the board to turn on MWI. */ + val = pci_read_config(dev, PCIR_COMMAND, 2); if (val & PCIM_CMD_MWRICEN && pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) sc->flags |= FXP_FLAG_MWI_ENABLE; @@ -1075,7 +1075,8 @@ fxp_suspend(device_t dev) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; sc->flags |= FXP_FLAG_WOL; /* Reconfigure hardware to accept magic frames. */ - fxp_init_body(sc, 1); + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + fxp_init_body(sc, 0); } pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); } @@ -1447,7 +1448,7 @@ fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) if (M_WRITABLE(*m_head) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; @@ -1563,7 +1564,7 @@ fxp_encap(struct fxp_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head, segs, &nseg, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg); + m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -2141,8 +2142,10 @@ fxp_tick(void *xsc) */ if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { sc->rx_idle_secs = 0; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 1); + } return; } /* @@ -2240,6 +2243,7 @@ fxp_watchdog(struct fxp_softc *sc) device_printf(sc->dev, "device timeout\n"); sc->ifp->if_oerrors++; + sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 1); } @@ -2274,6 +2278,10 @@ fxp_init_body(struct fxp_softc *sc, int setmedia) int i, prm; FXP_LOCK_ASSERT(sc, MA_OWNED); + + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + return; + /* * Cancel any pending I/O */ @@ -2628,7 +2636,7 @@ fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) bus_dmamap_t tmp_map; int error; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); @@ -2813,6 +2821,7 @@ fxp_miibus_statchg(device_t dev) */ if (sc->revision == FXP_REV_82557) return; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 0); } @@ -2836,9 +2845,10 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) if (ifp->if_flags & IFF_UP) { if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) && ((ifp->if_flags ^ sc->if_flags) & - (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) + (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 0); - else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) fxp_init_body(sc, 1); } else { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) @@ -2851,8 +2861,10 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) case SIOCADDMULTI: case SIOCDELMULTI: FXP_LOCK(sc); - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 0); + } FXP_UNLOCK(sc); break; @@ -2942,8 +2954,10 @@ fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); reinit++; } - if (reinit > 0 && ifp->if_flags & IFF_UP) + if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; fxp_init_body(sc, 0); + } FXP_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; @@ -3053,7 +3067,7 @@ static const struct ucode { int length; u_short int_delay_offset; u_short bundle_max_offset; -} const ucode_table[] = { +} ucode_table[] = { { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/README b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/README index 88879e1840..c0abeacccf 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/README +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/README @@ -389,7 +389,7 @@ For general information and support, go to the Intel support website at: http://support.intel.com If an issue is identified, support is through email only at: -freebsdnic@mailbox.intel.com +freebsd@intel.com License diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82571.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82571.c index 30015c1eaa..ca7a1d021f 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82571.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82571.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,8 +32,7 @@ ******************************************************************************/ /*$FreeBSD$*/ -/* - * 82571EB Gigabit Ethernet Controller +/* 82571EB Gigabit Ethernet Controller * 82571EB Gigabit Ethernet Controller (Copper) * 82571EB Gigabit Ethernet Controller (Fiber) * 82571EB Dual Port Gigabit Mezzanine Adapter @@ -51,9 +50,6 @@ #include "e1000_api.h" -static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); -static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); static void e1000_release_nvm_82571(struct e1000_hw *hw); static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, @@ -78,7 +74,6 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); -static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); @@ -99,13 +94,13 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_init_phy_params_82571"); if (hw->phy.media_type != e1000_media_type_copper) { phy->type = e1000_phy_none; - goto out; + return E1000_SUCCESS; } phy->addr = 1; @@ -165,8 +160,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; break; default: - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; break; } @@ -174,7 +168,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) ret_val = e1000_get_phy_id_82571(hw); if (ret_val) { DEBUGOUT("Error getting PHY ID\n"); - goto out; + return ret_val; } /* Verify phy id */ @@ -201,7 +195,6 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) if (ret_val) DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); -out: return ret_val; } @@ -241,8 +234,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) if (((eecd >> 15) & 0x3) == 0x3) { nvm->type = e1000_nvm_flash_hw; nvm->word_size = 2048; - /* - * Autonomous Flash update bit must be cleared due + /* Autonomous Flash update bit must be cleared due * to Flash update issue. */ eecd &= ~E1000_EECD_AUPDEN; @@ -254,8 +246,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) nvm->type = e1000_nvm_eeprom_spi; size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); - /* - * Added to a constant, "size" becomes the left-shift value + /* Added to a constant, "size" becomes the left-shift value * for setting word_size. */ size += NVM_WORD_SIZE_BASE_SHIFT; @@ -382,12 +373,11 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) /* FWSM register */ mac->has_fwsm = TRUE; - /* - * ARC supported; valid only if manageability features are + /* ARC supported; valid only if manageability features are * enabled. */ - mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & - E1000_FWSM_MODE_MASK) ? TRUE : FALSE; + mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_FWSM_MODE_MASK); break; case e1000_82574: case e1000_82583: @@ -405,8 +395,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) break; } - /* - * Ensure that the inter-port SWSM.SMBI lock bit is clear before + /* Ensure that the inter-port SWSM.SMBI lock bit is clear before * first NVM or PHY acess. This should be done for single-port * devices, and for one port only on dual-port devices so that * for those devices we can still use the SMBI lock to synchronize @@ -422,8 +411,9 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | E1000_SWSM2_LOCK); force_clear_smbi = TRUE; - } else + } else { force_clear_smbi = FALSE; + } break; default: force_clear_smbi = TRUE; @@ -443,10 +433,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); } - /* - * Initialze device specific counter of SMBI acquisition - * timeouts. - */ + /* Initialze device specific counter of SMBI acquisition timeouts. */ hw->dev_spec._82571.smb_counter = 0; return E1000_SUCCESS; @@ -477,7 +464,7 @@ void e1000_init_function_pointers_82571(struct e1000_hw *hw) static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 phy_id = 0; DEBUGFUNC("e1000_get_phy_id_82571"); @@ -485,8 +472,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * The 82571 firmware may still be configuring the PHY. + /* The 82571 firmware may still be configuring the PHY. * In this case, we cannot access the PHY until the * configuration is done. So we explicitly set the * PHY ID. @@ -494,29 +480,29 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) phy->id = IGP01E1000_I_PHY_ID; break; case e1000_82573: - ret_val = e1000_get_phy_id(hw); + return e1000_get_phy_id(hw); break; case e1000_82574: case e1000_82583: ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); if (ret_val) - goto out; + return ret_val; phy->id = (u32)(phy_id << 16); usec_delay(20); ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); if (ret_val) - goto out; + return ret_val; phy->id |= (u32)(phy_id); phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); break; default: - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; break; } -out: - return ret_val; + + return E1000_SUCCESS; } /** @@ -528,15 +514,13 @@ out: static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) { u32 swsm; - s32 ret_val = E1000_SUCCESS; s32 sw_timeout = hw->nvm.word_size + 1; s32 fw_timeout = hw->nvm.word_size + 1; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_82571"); - /* - * If we have timedout 3 times on trying to acquire + /* If we have timedout 3 times on trying to acquire * the inter-port SMBI semaphore, there is old code * operating on the other port, and it is not * releasing SMBI. Modify the number of times that @@ -576,12 +560,10 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_82571(hw); DEBUGOUT("Driver can't access the NVM\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -613,22 +595,19 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) { u32 extcnf_ctrl; - s32 ret_val = E1000_SUCCESS; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_82573"); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; do { + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) break; - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; - msec_delay(2); i++; } while (i < MDIO_OWNERSHIP_TIMEOUT); @@ -637,12 +616,10 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_82573(hw); DEBUGOUT("Driver can't access the PHY\n"); - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -712,7 +689,7 @@ static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) **/ static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) { - u16 data = E1000_READ_REG(hw, E1000_POEMB); + u32 data = E1000_READ_REG(hw, E1000_POEMB); DEBUGFUNC("e1000_set_d0_lplu_state_82574"); @@ -738,7 +715,7 @@ static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) **/ static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) { - u16 data = E1000_READ_REG(hw, E1000_POEMB); + u32 data = E1000_READ_REG(hw, E1000_POEMB); DEBUGFUNC("e1000_set_d3_lplu_state_82574"); @@ -771,7 +748,7 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) ret_val = e1000_get_hw_semaphore_82571(hw); if (ret_val) - goto out; + return ret_val; switch (hw->mac.type) { case e1000_82573: @@ -784,7 +761,6 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) if (ret_val) e1000_put_hw_semaphore_82571(hw); -out: return ret_val; } @@ -817,7 +793,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw) static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_write_nvm_82571"); @@ -857,31 +833,27 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) ret_val = e1000_update_nvm_checksum_generic(hw); if (ret_val) - goto out; + return ret_val; - /* - * If our nvm is an EEPROM, then we're done + /* If our nvm is an EEPROM, then we're done * otherwise, commit the checksum to the flash NVM. */ if (hw->nvm.type != e1000_nvm_flash_hw) - goto out; + return E1000_SUCCESS; /* Check for pending operations. */ for (i = 0; i < E1000_FLASH_UPDATES; i++) { msec_delay(1); - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) break; } - if (i == E1000_FLASH_UPDATES) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (i == E1000_FLASH_UPDATES) + return -E1000_ERR_NVM; /* Reset the firmware if using STM opcode. */ if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { - /* - * The enabling of and the actual reset must be done + /* The enabling of and the actual reset must be done * in two write cycles. */ E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); @@ -895,17 +867,14 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) for (i = 0; i < E1000_FLASH_UPDATES; i++) { msec_delay(1); - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) break; } - if (i == E1000_FLASH_UPDATES) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (i == E1000_FLASH_UPDATES) + return -E1000_ERR_NVM; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -944,19 +913,17 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, { struct e1000_nvm_info *nvm = &hw->nvm; u32 i, eewr = 0; - s32 ret_val = 0; + s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_write_nvm_eewr_82571"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } for (i = 0; i < words; i++) { @@ -975,7 +942,6 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, break; } -out: return ret_val; } @@ -988,7 +954,6 @@ out: static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) { s32 timeout = PHY_CFG_TIMEOUT; - s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_get_cfg_done_82571"); @@ -1001,12 +966,10 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) } if (!timeout) { DEBUGOUT("MNG configuration cycle has not completed.\n"); - ret_val = -E1000_ERR_RESET; - goto out; + return -E1000_ERR_RESET; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1023,39 +986,40 @@ out: static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; DEBUGFUNC("e1000_set_d0_lplu_state_82571"); if (!(phy->ops.read_reg)) - goto out; + return E1000_SUCCESS; ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); if (ret_val) - goto out; + return ret_val; if (active) { data |= IGP02E1000_PM_D0_LPLU; ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, data); if (ret_val) - goto out; + return ret_val; /* When LPLU is enabled, we should disable SmartSpeed */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else { data &= ~IGP02E1000_PM_D0_LPLU; ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, data); - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -1065,32 +1029,31 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1101,13 +1064,12 @@ out: **/ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) { - u32 ctrl, ctrl_ext; + u32 ctrl, ctrl_ext, eecd, tctl; s32 ret_val; DEBUGFUNC("e1000_reset_hw_82571"); - /* - * Prevent the PCI-E bus from sticking if there is no TLP connection + /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); @@ -1118,13 +1080,14 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); E1000_WRITE_REG(hw, E1000_RCTL, 0); - E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + tctl = E1000_READ_REG(hw, E1000_TCTL); + tctl &= ~E1000_TCTL_EN; + E1000_WRITE_REG(hw, E1000_TCTL, tctl); E1000_WRITE_FLUSH(hw); msec_delay(10); - /* - * Must acquire the MDIO ownership before MAC reset. + /* Must acquire the MDIO ownership before MAC reset. * Ownership defaults to firmware after a reset. */ switch (hw->mac.type) { @@ -1167,15 +1130,23 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) ret_val = e1000_get_auto_rd_done_generic(hw); if (ret_val) /* We don't want to continue accessing MAC registers. */ - goto out; + return ret_val; - /* - * Phy configuration from NVM just starts after EECD_AUTO_RD is set. + /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. * Need to wait for Phy configuration completion before accessing * NVM and Phy. */ switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + /* REQ and GNT bits need to be cleared when using AUTO_RD + * to access the EEPROM. + */ + eecd = E1000_READ_REG(hw, E1000_EECD); + eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + break; case e1000_82573: case e1000_82574: case e1000_82583: @@ -1193,7 +1164,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) /* Install any alternate MAC address into RAR0 */ ret_val = e1000_check_alt_mac_addr_generic(hw); if (ret_val) - goto out; + return ret_val; e1000_set_laa_state_82571(hw, TRUE); } @@ -1202,8 +1173,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) if (hw->phy.media_type == e1000_media_type_internal_serdes) hw->mac.serdes_link_state = e1000_serdes_link_down; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1225,16 +1195,15 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); + /* An error is not fatal and we should not stop init due to this */ if (ret_val) DEBUGOUT("Error initializing identification LED\n"); - /* This is not fatal and we should not stop init due to this */ /* Disabling VLAN filtering */ DEBUGOUT("Initializing the IEEE VLAN\n"); mac->ops.clear_vfta(hw); - /* Setup the receive address. */ - /* + /* Setup the receive address. * If, however, a locally administered address was assigned to the * 82571, we must reserve a RAR for it to work around an issue where * resetting one port will reload the MAC on the other port. @@ -1277,8 +1246,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) break; } - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -1377,8 +1345,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); } - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 */ if ((hw->mac.type == e1000_82571) || @@ -1388,6 +1355,15 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); } + /* Disable IPv6 extension header parsing because some malformed + * IPv6 headers can hang the Rx. + */ + if (hw->mac.type <= e1000_82573) { + reg = E1000_READ_REG(hw, E1000_RFCTL); + reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); + E1000_WRITE_REG(hw, E1000_RFCTL, reg); + } + /* PCI-Ex Control Registers */ switch (hw->mac.type) { case e1000_82574: @@ -1396,8 +1372,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) reg |= (1 << 22); E1000_WRITE_REG(hw, E1000_GCR, reg); - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * apply workaround for hardware errata documented in errata * docs Fixes issue where some error prone or unreliable PCIe * completions are occurring, particularly with ASPM enabled. @@ -1435,25 +1410,25 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw) case e1000_82574: case e1000_82583: if (hw->mng_cookie.vlan_id != 0) { - /* - * The VFTA is a 4096b bit-field, each identifying + /* The VFTA is a 4096b bit-field, each identifying * a single VLAN ID. The following operations * determine which 32b entry (i.e. offset) into the * array we want to set the VLAN ID (i.e. bit) of * the manageability unit. */ vfta_offset = (hw->mng_cookie.vlan_id >> - E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; - vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & - E1000_VFTA_ENTRY_BIT_SHIFT_MASK); + E1000_VFTA_ENTRY_SHIFT) & + E1000_VFTA_ENTRY_MASK; + vfta_bit_in_reg = + 1 << (hw->mng_cookie.vlan_id & + E1000_VFTA_ENTRY_BIT_SHIFT_MASK); } break; default: break; } for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { - /* - * If the offset we want to clear is the same offset of the + /* If the offset we want to clear is the same offset of the * manageability VLAN ID, then clear all bits except that of * the manageability unit. */ @@ -1495,8 +1470,7 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw) ctrl = hw->mac.ledctl_mode2; if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { - /* - * If no link, then turn LED on by setting the invert bit + /* If no link, then turn LED on by setting the invert bit * for each LED that's "on" (0x0E) in ledctl_mode2. */ for (i = 0; i < 4; i++) @@ -1519,30 +1493,28 @@ bool e1000_check_phy_82574(struct e1000_hw *hw) { u16 status_1kbt = 0; u16 receive_errors = 0; - bool phy_hung = FALSE; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_check_phy_82574"); - /* - * Read PHY Receive Error counter first, if its is max - all F's then + /* Read PHY Receive Error counter first, if its is max - all F's then * read the Base1000T status register If both are max then PHY is hung. */ ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); if (ret_val) - goto out; + return FALSE; if (receive_errors == E1000_RECEIVE_ERROR_MAX) { ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, &status_1kbt); if (ret_val) - goto out; + return FALSE; if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == E1000_IDLE_ERROR_COUNT_MASK) - phy_hung = TRUE; + return TRUE; } -out: - return phy_hung; + + return FALSE; } @@ -1560,8 +1532,7 @@ static s32 e1000_setup_link_82571(struct e1000_hw *hw) { DEBUGFUNC("e1000_setup_link_82571"); - /* - * 82573 does not have a word in the NVM to determine + /* 82573 does not have a word in the NVM to determine * the default flow control setting, so we explicitly * set it to full. */ @@ -1608,17 +1579,14 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) ret_val = e1000_copper_link_setup_igp(hw); break; default: - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; break; } if (ret_val) - goto out; + return ret_val; - ret_val = e1000_setup_copper_link_generic(hw); - -out: - return ret_val; + return e1000_setup_copper_link_generic(hw); } /** @@ -1635,8 +1603,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * If SerDes loopback mode is entered, there is no form + /* If SerDes loopback mode is entered, there is no form * of reset to take the adapter out of that mode. So we * have to explicitly take the adapter out of loopback * mode. This prevents drivers from twiddling their thumbs @@ -1685,16 +1652,17 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); status = E1000_READ_REG(hw, E1000_STATUS); + E1000_READ_REG(hw, E1000_RXCW); + /* SYNCH bit and IV bit are sticky */ + usec_delay(10); rxcw = E1000_READ_REG(hw, E1000_RXCW); if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { - /* Receiver is synchronized with no invalid bits. */ switch (mac->serdes_link_state) { case e1000_serdes_link_autoneg_complete: if (!(status & E1000_STATUS_LU)) { - /* - * We have lost link, retry autoneg before + /* We have lost link, retry autoneg before * reporting link failure */ mac->serdes_link_state = @@ -1707,15 +1675,12 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) break; case e1000_serdes_link_forced_up: - /* - * If we are receiving /C/ ordered sets, re-enable + /* If we are receiving /C/ ordered sets, re-enable * auto-negotiation in the TXCW register and disable * forced link in the Device Control register in an * attempt to auto-negotiate with our link partner. - * If the partner code word is null, stop forcing - * and restart auto negotiation. */ - if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { + if (rxcw & E1000_RXCW_C) { /* Enable autoneg, and unforce link up */ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); E1000_WRITE_REG(hw, E1000_CTRL, @@ -1731,8 +1696,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_autoneg_progress: if (rxcw & E1000_RXCW_C) { - /* - * We received /C/ ordered sets, meaning the + /* We received /C/ ordered sets, meaning the * link partner has autonegotiated, and we can * trust the Link Up (LU) status bit. */ @@ -1748,8 +1712,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) DEBUGOUT("AN_PROG -> DOWN\n"); } } else { - /* - * The link partner did not autoneg. + /* The link partner did not autoneg. * Force link up and full duplex, and change * state to forced. */ @@ -1774,8 +1737,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_down: default: - /* - * The link was down but the receiver has now gained + /* The link was down but the receiver has now gained * valid sync, so lets see if we can bring the link * up. */ @@ -1794,17 +1756,18 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) mac->serdes_link_state = e1000_serdes_link_down; DEBUGOUT("ANYSTATE -> DOWN\n"); } else { - /* - * Check several times, if Sync and Config - * both are consistently 1 then simply ignore - * the Invalid bit and restart Autoneg + /* Check several times, if SYNCH bit and CONFIG + * bit both are consistently 1 then simply ignore + * the IV bit and restart Autoneg */ for (i = 0; i < AN_RETRY_COUNT; i++) { usec_delay(10); rxcw = E1000_READ_REG(hw, E1000_RXCW); - if ((rxcw & E1000_RXCW_IV) && - !((rxcw & E1000_RXCW_SYNCH) && - (rxcw & E1000_RXCW_C))) { + if ((rxcw & E1000_RXCW_SYNCH) && + (rxcw & E1000_RXCW_C)) + continue; + + if (rxcw & E1000_RXCW_IV) { mac->serdes_has_link = FALSE; mac->serdes_link_state = e1000_serdes_link_down; @@ -1845,7 +1808,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } switch (hw->mac.type) { @@ -1862,8 +1825,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) break; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1900,15 +1862,14 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) /* If workaround is activated... */ if (state) - /* - * Hold a copy of the LAA in RAR[14] This is done so that + /* Hold a copy of the LAA in RAR[14] This is done so that * between the time RAR[0] gets clobbered and the time it * gets fixed, the actual LAA is in one of the RARs and no * incoming packets directed to this port are dropped. * Eventually the LAA will be in RAR[0] and RAR[14]. */ hw->mac.ops.rar_set(hw, hw->mac.addr, - hw->mac.rar_entry_count - 1); + hw->mac.rar_entry_count - 1); return; } @@ -1925,25 +1886,23 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; DEBUGFUNC("e1000_fix_nvm_checksum_82571"); if (nvm->type != e1000_nvm_flash_hw) - goto out; + return E1000_SUCCESS; - /* - * Check bit 4 of word 10h. If it is 0, firmware is done updating + /* Check bit 4 of word 10h. If it is 0, firmware is done updating * 10h-12h. Checksum may need to be fixed. */ ret_val = nvm->ops.read(hw, 0x10, 1, &data); if (ret_val) - goto out; + return ret_val; if (!(data & 0x10)) { - /* - * Read 0x23 and check bit 15. This bit is a 1 + /* Read 0x23 and check bit 15. This bit is a 1 * when the checksum has already been fixed. If * the checksum is still wrong and this bit is a * 1, we need to return bad checksum. Otherwise, @@ -1952,19 +1911,20 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) */ ret_val = nvm->ops.read(hw, 0x23, 1, &data); if (ret_val) - goto out; + return ret_val; if (!(data & 0x8000)) { data |= 0x8000; ret_val = nvm->ops.write(hw, 0x23, 1, &data); if (ret_val) - goto out; + return ret_val; ret_val = nvm->ops.update(hw); + if (ret_val) + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } @@ -1974,25 +1934,21 @@ out: **/ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; - DEBUGFUNC("e1000_read_mac_addr_82571"); if (hw->mac.type == e1000_82571) { - /* - * If there's an alternate MAC address place it in RAR0 + s32 ret_val; + + /* If there's an alternate MAC address place it in RAR0 * so that it will override the Si installed default perm * address. */ ret_val = e1000_check_alt_mac_addr_generic(hw); if (ret_val) - goto out; + return ret_val; } - ret_val = e1000_read_mac_addr_generic(hw); - -out: - return ret_val; + return e1000_read_mac_addr_generic(hw); } /** @@ -2007,7 +1963,7 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) struct e1000_phy_info *phy = &hw->phy; struct e1000_mac_info *mac = &hw->mac; - if (!(phy->ops.check_reset_block)) + if (!phy->ops.check_reset_block) return; /* If the management interface is not enabled, then power down */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.c index a04e3fad22..5722f4688c 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -144,6 +144,8 @@ static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) break; case e1000_82580: case e1000_i350: + case e1000_i210: + case e1000_i211: reg = E1000_READ_REG(hw, E1000_MDICNFG); ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); break; @@ -332,6 +334,7 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) } else { nvm->type = e1000_nvm_flash_hw; } + /* Function Pointers */ nvm->ops.acquire = e1000_acquire_nvm_82575; nvm->ops.release = e1000_release_nvm_82575; @@ -385,11 +388,16 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->rar_entry_count = E1000_RAR_ENTRIES_82576; if (mac->type == e1000_82580) mac->rar_entry_count = E1000_RAR_ENTRIES_82580; - if (mac->type == e1000_i350) { + if (mac->type == e1000_i350) mac->rar_entry_count = E1000_RAR_ENTRIES_I350; - /* Enable EEE default settings for i350 */ + + /* Enable EEE default settings for EEE supported devices */ + if (mac->type >= e1000_i350) dev_spec->eee_disable = FALSE; - } + + /* Allow a single clear of the SW semaphore on I210 and newer */ + if (mac->type >= e1000_i210) + dev_spec->clear_semaphore_once = TRUE; /* Set if part includes ASF firmware */ mac->asf_firmware_present = TRUE; @@ -428,7 +436,7 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->ops.config_collision_dist = e1000_config_collision_dist_82575; /* multicast address update */ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; - if (hw->mac.type == e1000_i350) { + if (mac->type == e1000_i350) { /* writing VFTA */ mac->ops.write_vfta = e1000_write_vfta_i350; /* clearing VFTA */ @@ -439,6 +447,9 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) /* clearing VFTA */ mac->ops.clear_vfta = e1000_clear_vfta_generic; } + if (hw->mac.type >= e1000_82580) + mac->ops.validate_mdi_setting = + e1000_validate_mdi_setting_crossover_generic; /* ID LED init */ mac->ops.id_led_init = e1000_id_led_init_generic; /* blink LED */ @@ -634,6 +645,8 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) break; case e1000_82580: case e1000_i350: + case e1000_i210: + case e1000_i211: mdic = E1000_READ_REG(hw, E1000_MDICNFG); mdic &= E1000_MDICNFG_PHY_MASK; phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; @@ -1143,6 +1156,15 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw) */ hw->mac.get_link_status = !hw->mac.serdes_has_link; + /* + * Configure Flow Control now that Auto-Neg has completed. + * First, we need to restore the desired flow control + * settings because we may have had to re-autoneg with a + * different link partner. + */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) + DEBUGOUT("Error configuring flow control\n"); } else { ret_val = e1000_check_for_copper_link_generic(hw); } @@ -1222,6 +1244,7 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, *duplex = FULL_DUPLEX; else *duplex = HALF_DUPLEX; + } else { mac->serdes_has_link = FALSE; *speed = 0; @@ -1397,7 +1420,8 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw) static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) { u32 ctrl; - s32 ret_val; + s32 ret_val; + u32 phpm_reg; DEBUGFUNC("e1000_setup_copper_link_82575"); @@ -1406,6 +1430,13 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + /* Clear Go Link Disconnect bit */ + if (hw->mac.type >= e1000_82580) { + phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); + phpm_reg &= ~E1000_82580_PM_GO_LINKD; + E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); + } + ret_val = e1000_setup_serdes_link_82575(hw); if (ret_val) goto out; @@ -1423,12 +1454,17 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) switch (hw->phy.type) { case e1000_phy_i210: case e1000_phy_m88: - if (hw->phy.id == I347AT4_E_PHY_ID || - hw->phy.id == M88E1112_E_PHY_ID || - hw->phy.id == M88E1340M_E_PHY_ID) + switch (hw->phy.id) { + case I347AT4_E_PHY_ID: + case M88E1112_E_PHY_ID: + case M88E1340M_E_PHY_ID: + case I210_I_PHY_ID: ret_val = e1000_copper_link_setup_m88_gen2(hw); - else + break; + default: ret_val = e1000_copper_link_setup_m88(hw); + break; + } break; case e1000_phy_igp_3: ret_val = e1000_copper_link_setup_igp(hw); @@ -1460,7 +1496,7 @@ out: **/ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) { - u32 ctrl_ext, ctrl_reg, reg; + u32 ctrl_ext, ctrl_reg, reg, anadv_reg; bool pcs_autoneg; s32 ret_val = E1000_SUCCESS; u16 data; @@ -1544,26 +1580,47 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); - /* - * We force flow control to prevent the CTRL register values from being - * overwritten by the autonegotiated flow control values - */ - reg |= E1000_PCS_LCTL_FORCE_FCTRL; - if (pcs_autoneg) { /* Set PCS register for autoneg */ reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ + + /* Disable force flow control for autoneg */ + reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; + + /* Configure flow control advertisement for autoneg */ + anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); + anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); + + switch (hw->fc.requested_mode) { + case e1000_fc_full: + case e1000_fc_rx_pause: + anadv_reg |= E1000_TXCW_ASM_DIR; + anadv_reg |= E1000_TXCW_PAUSE; + break; + case e1000_fc_tx_pause: + anadv_reg |= E1000_TXCW_ASM_DIR; + break; + default: + break; + } + + E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); + DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); } else { /* Set PCS register for forced link */ reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ + + /* Force flow control for forced link */ + reg |= E1000_PCS_LCTL_FORCE_FCTRL; + DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); } E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); - if (!e1000_sgmii_active_82575(hw)) + if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) e1000_force_mac_fc_generic(hw); return ret_val; @@ -1582,137 +1639,70 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) **/ static s32 e1000_get_media_type_82575(struct e1000_hw *hw) { - u32 lan_id = 0; - s32 ret_val = E1000_ERR_CONFIG; struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; + s32 ret_val = E1000_SUCCESS; u32 ctrl_ext = 0; - u32 current_link_mode = 0; - u16 init_ctrl_wd_3 = 0; - u8 init_ctrl_wd_3_offset = 0; - u8 init_ctrl_wd_3_bit_offset = 0; + u32 link_mode = 0; /* Set internal phy as default */ dev_spec->sgmii_active = FALSE; dev_spec->module_plugged = FALSE; - /* - * Check if NVM access method is attached already. - * If it is then Init Control Word #3 is considered - * otherwise runtime CSR register content is taken. - */ - /* Get CSR setting */ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); - /* Get link mode setting */ - if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) { - /* Take link mode from EEPROM */ - - /* - * Get LAN port ID to derive its - * adequate Init Control Word #3 - */ - lan_id = ((E1000_READ_REG(hw, E1000_STATUS) & - E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET); - /* - * Derive Init Control Word #3 offset - * and mask to pick up link mode setting. - */ - if (hw->mac.type < e1000_82580) { - init_ctrl_wd_3_offset = lan_id ? - NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B; - init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET; - } else { - init_ctrl_wd_3_offset = - NVM_82580_LAN_FUNC_OFFSET(lan_id) + - NVM_INIT_CONTROL3_PORT_A; - init_ctrl_wd_3_bit_offset = - NVM_WORD24_82580_LNK_MODE_OFFSET; - } - /* Read Init Control Word #3*/ - hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3); - - /* - * Align link mode bits to - * their CTRL_EXT location. - */ - current_link_mode = init_ctrl_wd_3; - current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET - - init_ctrl_wd_3_bit_offset); - current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK; - - /* - * Switch to CSR for all but internal PHY. - */ - if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII) - /* Take link mode from CSR */ - current_link_mode = ctrl_ext & - E1000_CTRL_EXT_LINK_MODE_MASK; - } else { - /* Take link mode from CSR */ - current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; - } - - switch (current_link_mode) { + /* extract link mode setting */ + link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; + switch (link_mode) { case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: hw->phy.media_type = e1000_media_type_internal_serdes; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX; break; case E1000_CTRL_EXT_LINK_MODE_GMII: hw->phy.media_type = e1000_media_type_copper; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII; break; case E1000_CTRL_EXT_LINK_MODE_SGMII: - case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: /* Get phy control interface type set (MDIO vs. I2C)*/ if (e1000_sgmii_uses_mdio_82575(hw)) { hw->phy.media_type = e1000_media_type_copper; dev_spec->sgmii_active = TRUE; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII; - } else { - ret_val = e1000_set_sfp_media_type_82575(hw); - if (ret_val != E1000_SUCCESS) - goto out; - if (hw->phy.media_type == - e1000_media_type_internal_serdes) { - current_link_mode = - E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; - } else if (hw->phy.media_type == - e1000_media_type_copper) { - current_link_mode = - E1000_CTRL_EXT_LINK_MODE_SGMII; - } + break; } - break; - default: - DEBUGOUT("Link mode mask doesn't fit bit field size\n"); - goto out; - } - /* - * Do not change current link mode setting - * if media type is fibre or has not been - * recognized. - */ - if ((hw->phy.media_type != e1000_media_type_unknown) && - (hw->phy.media_type != e1000_media_type_fiber)) { - /* Update link mode */ - ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; - E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | - current_link_mode); - } - - ret_val = E1000_SUCCESS; -out: - /* - * If media type was not identified then return media type - * defined by the CTRL_EXT settings. - */ - if (hw->phy.media_type == e1000_media_type_unknown) { - if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) - hw->phy.media_type = e1000_media_type_copper; - else + /* fall through for I2C based SGMII */ + case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: + /* read media type from SFP EEPROM */ + ret_val = e1000_set_sfp_media_type_82575(hw); + if ((ret_val != E1000_SUCCESS) || + (hw->phy.media_type == e1000_media_type_unknown)) { + /* + * If media type was not identified then return media + * type defined by the CTRL_EXT settings. + */ hw->phy.media_type = e1000_media_type_internal_serdes; + + if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = TRUE; + } + + break; + } + + /* do not change link mode for 100BaseFX */ + if (dev_spec->eth_flags.e100_base_fx) + break; + + /* change current link mode setting */ + ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; + + if (hw->phy.media_type == e1000_media_type_copper) + ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; + else + ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; + + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + + break; } return ret_val; @@ -1730,40 +1720,52 @@ static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) s32 ret_val = E1000_ERR_CONFIG; u32 ctrl_ext = 0; struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; - struct sfp_e1000_flags eth_flags = {0}; + struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; u8 tranceiver_type = 0; + s32 timeout = 3; - /* Turn I2C interface ON */ + /* Turn I2C interface ON and power on sfp cage */ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); + E1000_WRITE_FLUSH(hw); + /* Read SFP module data */ - ret_val = e1000_read_sfp_data_byte(hw, + while (timeout) { + ret_val = e1000_read_sfp_data_byte(hw, E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), &tranceiver_type); + if (ret_val == E1000_SUCCESS) + break; + msec_delay(100); + timeout--; + } if (ret_val != E1000_SUCCESS) goto out; + ret_val = e1000_read_sfp_data_byte(hw, E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), - (u8 *)ð_flags); + (u8 *)eth_flags); if (ret_val != E1000_SUCCESS) goto out; - /* - * Check if there is some SFP - * module plugged and powered - */ + + /* Check if there is some SFP module plugged and powered */ if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { dev_spec->module_plugged = TRUE; - if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { + if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { hw->phy.media_type = e1000_media_type_internal_serdes; - } else if (eth_flags.e1000_base_t) { + } else if (eth_flags->e100_base_fx) { + dev_spec->sgmii_active = TRUE; + hw->phy.media_type = e1000_media_type_internal_serdes; + } else if (eth_flags->e1000_base_t) { dev_spec->sgmii_active = TRUE; hw->phy.media_type = e1000_media_type_copper; } else { - hw->phy.media_type = e1000_media_type_unknown; - DEBUGOUT("PHY module has not been recognized\n"); - goto out; + hw->phy.media_type = e1000_media_type_unknown; + DEBUGOUT("PHY module has not been recognized\n"); + goto out; } } else { hw->phy.media_type = e1000_media_type_unknown; @@ -2334,6 +2336,10 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw) hw->dev_spec._82575.global_device_reset = FALSE; + /* 82580 does not reliably do global_device_reset due to hw errata */ + if (hw->mac.type == e1000_82580) + global_device_reset = FALSE; + /* Get current control state. */ ctrl = E1000_READ_REG(hw, E1000_CTRL); @@ -2660,10 +2666,15 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw) /* enable or disable per user setting */ if (!(hw->dev_spec._82575.eee_disable)) { + u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); + ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | E1000_EEER_LPI_FC); + /* This bit should not be set in normal operation. */ + if (eee_su & E1000_EEE_SU_LPI_CLK_STP) + DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); } else { ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | @@ -3275,3 +3286,4 @@ void e1000_i2c_bus_clear(struct e1000_hw *hw) e1000_i2c_stop(hw); } + diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.h index 4b2b245f3d..c6bbe186c0 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_82575.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -360,10 +360,13 @@ struct e1000_adv_tx_context_desc { #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ +#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ +#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ +#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.c index 4b2a43d728..158191304b 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -289,6 +289,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_PCH2_LV_V: mac->type = e1000_pch2lan; break; + case E1000_DEV_ID_PCH_LPT_I217_LM: + case E1000_DEV_ID_PCH_LPT_I217_V: + case E1000_DEV_ID_PCH_LPTLP_I218_LM: + case E1000_DEV_ID_PCH_LPTLP_I218_V: + mac->type = e1000_pch_lpt; + break; case E1000_DEV_ID_82575EB_COPPER: case E1000_DEV_ID_82575EB_FIBER_SERDES: case E1000_DEV_ID_82575GB_QUAD_COPPER: @@ -323,6 +329,9 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_I350_DA4: mac->type = e1000_i350; break; +#if defined(QV_RELEASE) && defined(SPRINGVILLE_FLASHLESS_HW) + case E1000_DEV_ID_I210_NVMLESS: +#endif /* QV_RELEASE && SPRINGVILLE_FLASHLESS_HW */ case E1000_DEV_ID_I210_COPPER: case E1000_DEV_ID_I210_COPPER_OEM1: case E1000_DEV_ID_I210_COPPER_IT: @@ -332,14 +341,17 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) mac->type = e1000_i210; break; case E1000_DEV_ID_I211_COPPER: - mac->type = e1000_i211; - break; + mac->type = e1000_i211; + break; case E1000_DEV_ID_82576_VF: + case E1000_DEV_ID_82576_VF_HV: mac->type = e1000_vfadapt; break; case E1000_DEV_ID_I350_VF: + case E1000_DEV_ID_I350_VF_HV: mac->type = e1000_vfadapt_i350; break; + default: /* Should never have loaded on this device */ ret_val = -E1000_ERR_MAC_INIT; @@ -428,6 +440,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device) case e1000_ich10lan: case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: e1000_init_function_pointers_ich8lan(hw); break; case e1000_82575: @@ -873,11 +886,7 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum) { - if (hw->mac.ops.mng_host_if_write) - return hw->mac.ops.mng_host_if_write(hw, buffer, length, - offset, sum); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum); } /** @@ -890,10 +899,7 @@ s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, struct e1000_host_mng_command_header *hdr) { - if (hw->mac.ops.mng_write_cmd_header) - return hw->mac.ops.mng_write_cmd_header(hw, hdr); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_write_cmd_header_generic(hw, hdr); } /** @@ -908,23 +914,20 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, **/ s32 e1000_mng_enable_host_if(struct e1000_hw *hw) { - if (hw->mac.ops.mng_enable_host_if) - return hw->mac.ops.mng_enable_host_if(hw); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_enable_host_if_generic(hw); } /** - * e1000_wait_autoneg - Waits for autonegotiation completion + * e1000_set_obff_timer - Set Optimized Buffer Flush/Fill timer * @hw: pointer to the HW structure + * @itr: u32 indicating itr value * - * Waits for autoneg to complete. Currently no func pointer exists and all - * implementations are handled in the generic version of this function. + * Set the OBFF timer based on the given interrupt rate. **/ -s32 e1000_wait_autoneg(struct e1000_hw *hw) +s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr) { - if (hw->mac.ops.wait_autoneg) - return hw->mac.ops.wait_autoneg(hw); + if (hw->mac.ops.set_obff_timer) + return hw->mac.ops.set_obff_timer(hw, itr); return E1000_SUCCESS; } diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.h index 4c061c0958..69db1be90d 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_api.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ extern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw); extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw); extern void e1000_init_function_pointers_i210(struct e1000_hw *hw); +s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr); s32 e1000_set_mac_type(struct e1000_hw *hw); s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device); s32 e1000_init_mac_params(struct e1000_hw *hw); @@ -105,7 +106,6 @@ s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); -s32 e1000_wait_autoneg(struct e1000_hw *hw); s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); bool e1000_check_mng_mode(struct e1000_hw *hw); @@ -162,4 +162,6 @@ u32 e1000_translate_register_82542(u32 reg); (((length) > min_frame_size) && \ ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1))))) -#endif +#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b)) +#define E1000_DIVIDE_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) /* ceil(a/b) */ +#endif /* _E1000_API_H_ */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h index a4a0ed0500..48c04b013d 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_defines.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -43,15 +43,7 @@ /* Wake Up Control */ #define E1000_WUC_APME 0x00000001 /* APM Enable */ #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ -#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ -#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ -#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ -#define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */ -#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ -#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ -#define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */ -#define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */ /* Wake Up Filter Control */ #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ @@ -61,41 +53,7 @@ #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ -#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ -#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */ -#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */ -#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */ -#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */ -#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */ -#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */ -#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */ -#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ -#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ -#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ -#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ -#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ -#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ -#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */ -#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */ -#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */ -#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /* wakeup filters mask */ -#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Flexible Filters bits offset */ -#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /* 4 flexible filters mask */ -#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /* 6 wakeup filters mask */ -#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /* 6 flexible filters mask */ -#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */ -#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 wu filters */ -#define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 wu filters */ -#define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */ -#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */ -#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* 6 flexible filters mask */ -#define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* 8 flexible filters mask */ -/* - * For 82576 to utilize Extended filter masks in addition to - * existing (filter) masks - */ -#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ /* Wake Up Status */ #define E1000_WUS_LNKC E1000_WUFC_LNKC @@ -103,74 +61,18 @@ #define E1000_WUS_EX E1000_WUFC_EX #define E1000_WUS_MC E1000_WUFC_MC #define E1000_WUS_BC E1000_WUFC_BC -#define E1000_WUS_ARP E1000_WUFC_ARP -#define E1000_WUS_IPV4 E1000_WUFC_IPV4 -#define E1000_WUS_IPV6 E1000_WUFC_IPV6 -#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY -#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY -#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY -#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY -#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 -#define E1000_WUS_FLX0 E1000_WUFC_FLX0 -#define E1000_WUS_FLX1 E1000_WUFC_FLX1 -#define E1000_WUS_FLX2 E1000_WUFC_FLX2 -#define E1000_WUS_FLX3 E1000_WUFC_FLX3 -#define E1000_WUS_FLX4 E1000_WUFC_FLX4 -#define E1000_WUS_FLX5 E1000_WUFC_FLX5 -#define E1000_WUS_FLX6 E1000_WUFC_FLX6 -#define E1000_WUS_FLX7 E1000_WUFC_FLX7 -#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY -#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY -#define E1000_WUS_FLX6_PHY 0x0400 -#define E1000_WUS_FLX7_PHY 0x0800 -#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS -#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 -#define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8 -#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 - -/* Wake Up Packet Length */ -#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ - -/* Four Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 -/* Six Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6 -/* Eight Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8 -/* Two Extended Flexible Filters are supported (82576) */ -#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 -#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ -#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ - -/* Each Flexible Filter is at most 128 (0x80) bytes in length */ -#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 - -#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX -#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 -#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8 -#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX -#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX /* Extended Device Control */ -#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ -#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ -#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN -#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ -#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ -/* Reserved (bits 4,5) in >= 82575 */ +#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ -#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */ -#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ -#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ -#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ -#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ /* Physical Func Reset Done Indication */ #define E1000_CTRL_EXT_PFRSTD 0x00004000 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ @@ -179,42 +81,22 @@ #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 /* Offset of the link mode field in Ctrl Ext register */ #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 -#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 -#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 #define E1000_CTRL_EXT_EIAME 0x01000000 #define E1000_CTRL_EXT_IRCA 0x00000001 -#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 -#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 -#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 -#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 -#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 -#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ -/* IAME enable bit (27) was removed in >= 82575 */ #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ -/* packet buffer parity error detection enabled */ -#define E1000_CRTL_EXT_PB_PAREN 0x01000000 -/* descriptor FIFO parity error detection enable */ -#define E1000_CTRL_EXT_DF_PAREN 0x02000000 -#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ #define E1000_CTRL_EXT_LSECCK 0x00001000 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 -#define E1000_I2CCMD_REG_ADDR 0x00FF0000 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 -#define E1000_I2CCMD_PHY_ADDR 0x07000000 #define E1000_I2CCMD_OPCODE_READ 0x08000000 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 -#define E1000_I2CCMD_RESET 0x10000000 #define E1000_I2CCMD_READY 0x20000000 -#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 #define E1000_I2CCMD_ERROR 0x80000000 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) @@ -235,11 +117,9 @@ #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ -#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ -#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ @@ -248,11 +128,8 @@ #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ -#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ -#define E1000_RXD_SPC_PRI_SHIFT 13 -#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ -#define E1000_RXD_SPC_CFI_SHIFT 12 +#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ #define E1000_RXDEXT_STATERR_LB 0x00040000 #define E1000_RXDEXT_STATERR_CE 0x01000000 #define E1000_RXDEXT_STATERR_SE 0x02000000 @@ -262,13 +139,6 @@ #define E1000_RXDEXT_STATERR_IPE 0x40000000 #define E1000_RXDEXT_STATERR_RXE 0x80000000 -#define E1000_RXDEXT_LSECH 0x01000000 -#define E1000_RXDEXT_LSECE_MASK 0x60000000 -#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000 -#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 -#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000 -#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000 - /* mask to determine if packets should be dropped due to frame errors */ #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ @@ -285,57 +155,25 @@ E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_RXE) -#define E1000_MRQC_ENABLE_MASK 0x00000007 -#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 -#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 -#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 -#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF /* Management Control */ #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ -#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ -#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ -#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ -#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ -#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ -#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ -/* Enable Neighbor Discovery Filtering */ -#define E1000_MANC_NEIGHBOR_EN 0x00004000 -#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ -#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ -#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ -#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ /* Enable MAC address filtering */ #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MNG packets to host memory */ #define E1000_MANC_EN_MNG2HOST 0x00200000 -/* Enable IP address filtering */ -#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 -#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */ -#define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */ -#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ -#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ -#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ -#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ -#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ -#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ -#define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */ -#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */ - -#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ -#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ @@ -351,19 +189,11 @@ #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ -#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ -#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ -#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */ -#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */ #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ -#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ -#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ -#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ -#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ @@ -381,11 +211,8 @@ #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ -#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ -#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ -/* - * Use byte values for the following shift parameters +/* Use byte values for the following shift parameters * Usage: * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & * E1000_PSRCTL_BSIZE0_MASK) | @@ -420,16 +247,11 @@ #define E1000_SWFW_PHY3_SM 0x40 #define E1000_SWFW_SW_MNG_SM 0x400 -/* FACTPS Definitions */ -#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ /* Device Control */ #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ -#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ -#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ -#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ @@ -437,50 +259,35 @@ #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ -#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ -#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ -/* Defined polarity of Dock/Undock indication in SDP[0] */ -#define E1000_CTRL_D_UD_POLARITY 0x00004000 -/* Reset both PHY ports, through PHYRST_N pin */ -#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 -/* enable link status from external LINK_0 and LINK_1 pins */ -#define E1000_CTRL_EXT_LINK_EN 0x00010000 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ +#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ +#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ -#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ #define E1000_CTRL_RST 0x04000000 /* Global reset */ #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ -#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ -#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ -/* - * Bit definitions for the Management Data IO (MDIO) and Management Data - * Clock (MDC) pins in the Device Control Register. - */ -#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 -#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 -#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR -#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA #define E1000_CONNSW_ENRGSRC 0x4 +#define E1000_CONNSW_PHYSD 0x400 +#define E1000_CONNSW_SERDESD 0x200 #define E1000_PCS_CFG_PCS_EN 8 #define E1000_PCS_LCTL_FLV_LINK_UP 1 #define E1000_PCS_LCTL_FSV_10 0 @@ -489,65 +296,37 @@ #define E1000_PCS_LCTL_FDV_FULL 8 #define E1000_PCS_LCTL_FSD 0x10 #define E1000_PCS_LCTL_FORCE_LINK 0x20 -#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 #define E1000_PCS_LCTL_AN_RESTART 0x20000 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 -#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 -#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 -#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 -#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 -#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 #define E1000_PCS_LSTS_LINK_OK 1 -#define E1000_PCS_LSTS_SPEED_10 0 #define E1000_PCS_LSTS_SPEED_100 2 #define E1000_PCS_LSTS_SPEED_1000 4 #define E1000_PCS_LSTS_DUPLEX_FULL 8 #define E1000_PCS_LSTS_SYNK_OK 0x10 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 -#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 -#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 -#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 -#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 /* Device Status */ #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ #define E1000_STATUS_FUNC_SHIFT 2 -#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ -#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ -#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_MASK 0x000000C0 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ -#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ -/* Change in Dock/Undock state clear on write '0'. */ -#define E1000_STATUS_DOCK_CI 0x00000800 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ -#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ -#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */ -#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ -#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ -#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ -/* BMC external code execution disabled */ -#define E1000_STATUS_BMC_LITE 0x01000000 -#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ -#define E1000_STATUS_FUSE_8 0x04000000 -#define E1000_STATUS_FUSE_9 0x08000000 -#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */ -#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */ /* Constants used to interpret the masked PCI-X bus speed. */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ @@ -578,8 +357,6 @@ ADVERTISE_100_FULL) #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) -#define E1000_ALL_FULL_DUPLEX ( \ - ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX @@ -587,51 +364,20 @@ /* LED Control */ #define E1000_PHY_LED0_MODE_MASK 0x00000007 #define E1000_PHY_LED0_IVRT 0x00000008 -#define E1000_PHY_LED0_BLINK 0x00000010 #define E1000_PHY_LED0_MASK 0x0000001F #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F #define E1000_LEDCTL_LED0_MODE_SHIFT 0 -#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 #define E1000_LEDCTL_LED0_IVRT 0x00000040 #define E1000_LEDCTL_LED0_BLINK 0x00000080 -#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 -#define E1000_LEDCTL_LED1_MODE_SHIFT 8 -#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 -#define E1000_LEDCTL_LED1_IVRT 0x00004000 -#define E1000_LEDCTL_LED1_BLINK 0x00008000 -#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 -#define E1000_LEDCTL_LED2_MODE_SHIFT 16 -#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 -#define E1000_LEDCTL_LED2_IVRT 0x00400000 -#define E1000_LEDCTL_LED2_BLINK 0x00800000 -#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 -#define E1000_LEDCTL_LED3_MODE_SHIFT 24 -#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 -#define E1000_LEDCTL_LED3_IVRT 0x40000000 -#define E1000_LEDCTL_LED3_BLINK 0x80000000 -#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 -#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 #define E1000_LEDCTL_MODE_LINK_UP 0x2 -#define E1000_LEDCTL_MODE_ACTIVITY 0x3 -#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 -#define E1000_LEDCTL_MODE_LINK_10 0x5 -#define E1000_LEDCTL_MODE_LINK_100 0x6 -#define E1000_LEDCTL_MODE_LINK_1000 0x7 -#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 -#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 -#define E1000_LEDCTL_MODE_COLLISION 0xA -#define E1000_LEDCTL_MODE_BUS_SPEED 0xB -#define E1000_LEDCTL_MODE_BUS_SIZE 0xC -#define E1000_LEDCTL_MODE_PAUSED 0xD #define E1000_LEDCTL_MODE_LED_ON 0xE #define E1000_LEDCTL_MODE_LED_OFF 0xF /* Transmit Descriptor bit definitions */ #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ -#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ @@ -650,21 +396,14 @@ #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ -/* Extended desc bits for Linksec and timesync */ -#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */ #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ /* Transmit Control */ -#define E1000_TCTL_RST 0x00000001 /* software reset */ #define E1000_TCTL_EN 0x00000002 /* enable Tx */ -#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ -#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ -#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ -#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ /* Transmit Arbitration Count */ @@ -672,29 +411,19 @@ /* SerDes Control */ #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 +#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 /* Receive Checksum Control */ -#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ -#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ /* Header split receive */ -#define E1000_RFCTL_ISCSI_DIS 0x00000001 -#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E -#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 #define E1000_RFCTL_NFSW_DIS 0x00000040 #define E1000_RFCTL_NFSR_DIS 0x00000080 -#define E1000_RFCTL_NFS_VER_MASK 0x00000300 -#define E1000_RFCTL_NFS_VER_SHIFT 8 -#define E1000_RFCTL_IPV6_DIS 0x00000400 -#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 #define E1000_RFCTL_ACK_DIS 0x00001000 -#define E1000_RFCTL_ACKD_DIS 0x00002000 -#define E1000_RFCTL_IPFRSP_DIS 0x00004000 #define E1000_RFCTL_EXTEN 0x00008000 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 @@ -712,8 +441,6 @@ #define DEFAULT_82543_TIPG_IPGT_COPPER 8 #define E1000_TIPG_IPGT_MASK 0x000003FF -#define E1000_TIPG_IPGR1_MASK 0x000FFC00 -#define E1000_TIPG_IPGR2_MASK 0x3FF00000 #define DEFAULT_82542_TIPG_IPGR1 2 #define DEFAULT_82543_TIPG_IPGR1 8 @@ -741,7 +468,6 @@ #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 -#define E1000_PHY_CTRL_SPD_EN 0x00000001 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 @@ -749,8 +475,10 @@ #define E1000_KABGTXD_BGSQLBIAS 0x00050000 +/* Low Power IDLE Control */ +#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ + /* PBA constants */ -#define E1000_PBA_6K 0x0006 /* 6KB */ #define E1000_PBA_8K 0x0008 /* 8KB */ #define E1000_PBA_10K 0x000A /* 10KB */ #define E1000_PBA_12K 0x000C /* 12KB */ @@ -770,10 +498,15 @@ #define E1000_PBA_48K 0x0030 /* 48KB */ #define E1000_PBA_64K 0x0040 /* 64KB */ -#define E1000_PBA_RXA_MASK 0xFFFF; +#define E1000_PBA_RXA_MASK 0xFFFF #define E1000_PBS_16K E1000_PBA_16K -#define E1000_PBS_24K E1000_PBA_24K + +/* Uncorrectable/correctable ECC Error counts and enable bits */ +#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF +#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 +#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 +#define E1000_PBECCSTS_ECC_ENABLE 0x00010000 #define IFS_MAX 80 #define IFS_MIN 40 @@ -784,7 +517,6 @@ /* SW Semaphore Register */ #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ -#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ @@ -798,33 +530,19 @@ #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ -#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ #define E1000_ICR_TXD_LOW 0x00008000 -#define E1000_ICR_SRPD 0x00010000 -#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ #define E1000_ICR_MNG 0x00040000 /* Manageability event */ -#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ +#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ +#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ /* If this bit asserted, the driver should claim the interrupt */ #define E1000_ICR_INT_ASSERTED 0x80000000 -#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ -#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ -#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ -#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ -#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ -/* FW changed the status of DISSW bit in the FWSM */ -#define E1000_ICR_DSW 0x00000020 -/* LAN connected device generates an interrupt */ -#define E1000_ICR_PHYINT 0x00001000 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ -#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ @@ -862,18 +580,7 @@ #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ -/* - * This defines the bits that are set in the Interrupt Mask - * Set/Read Register. Each bit is documented below: - * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) - * o RXSEQ = Receive Sequence Error - */ -#define POLL_IMS_ENABLE_MASK ( \ - E1000_IMS_RXDMT0 | \ - E1000_IMS_RXSEQ) - -/* - * This defines the bits that are set in the Interrupt Mask +/* This defines the bits that are set in the Interrupt Mask * Set/Read Register. Each bit is documented below: * o RXT0 = Receiver Timer Interrupt (ring 0) * o TXDW = Transmit Descriptor Written Back @@ -897,34 +604,11 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ -#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ -#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMS_SRPD E1000_ICR_SRPD -#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ +#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ -/* Q0 Rx desc FIFO parity error */ -#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 -/* Q0 Tx desc FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 -/* host arb read buffer parity error */ -#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR -/* packet buffer parity error */ -#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR -/* Q1 Rx desc FIFO parity error */ -#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 -/* Q1 Tx desc FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 -#define E1000_IMS_DSW E1000_ICR_DSW -#define E1000_IMS_PHYINT E1000_ICR_PHYINT #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ -#define E1000_IMS_EPRST E1000_ICR_EPRST #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ @@ -947,41 +631,9 @@ #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ /* Interrupt Cause Set */ -#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ -#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ -#define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */ -#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ -#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ -#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ -#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_ICS_SRPD E1000_ICR_SRPD -#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ -#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ -/* Q0 Rx desc FIFO parity error */ -#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 -/* Q0 Tx desc FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 -/* host arb read buffer parity error */ -#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR -/* packet buffer parity error */ -#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR -/* Q1 Rx desc FIFO parity error */ -#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 -/* Q1 Tx desc FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 -#define E1000_ICS_DSW E1000_ICR_DSW -#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ -#define E1000_ICS_PHYINT E1000_ICR_PHYINT -#define E1000_ICS_EPRST E1000_ICR_EPRST /* Extended Interrupt Cause Set */ #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ @@ -1004,7 +656,6 @@ #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ -#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ /* Enable the counting of descriptors still to be processed. */ @@ -1019,8 +670,7 @@ #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ -/* Receive Address */ -/* +/* Receive Address * Number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. * Technically, we have 16 spots. However, we reserve one of these spots @@ -1032,8 +682,6 @@ #define E1000_RAL_MAC_ADDR_LEN 4 #define E1000_RAH_MAC_ADDR_LEN 2 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 -#define E1000_RAH_POOL_MASK 0x03FC0000 -#define E1000_RAH_POOL_SHIFT 18 #define E1000_RAH_POOL_1 0x00040000 /* Error Codes */ @@ -1073,30 +721,21 @@ /* Flow Control */ #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ -#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ /* Transmit Configuration Word */ #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ -#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ -#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ -#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ -#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ -#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ /* Receive Configuration Word */ #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ -#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ -#define E1000_RXCW_CC 0x10000000 /* Receive config change */ #define E1000_RXCW_C 0x20000000 /* Receive config */ #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ -#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ @@ -1109,6 +748,13 @@ #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ +#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ + +#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 +#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 + +#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 +#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 @@ -1130,6 +776,11 @@ #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 #define E1000_TIMINCA_16NS_SHIFT 24 +#define E1000_TIMINCA_INCPERIOD_SHIFT 24 +#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF + +#define E1000_TSICR_TXTS 0x00000002 +#define E1000_TSIM_TXTS 0x00000002 /* TUPLE Filtering Configuration */ #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ @@ -1170,7 +821,7 @@ #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ - +#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ /* PCI Express Control */ #define E1000_GCR_RXD_NO_SNOOP 0x00000001 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 @@ -1314,10 +965,6 @@ #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ #define E1000_EECD_DI 0x00000004 /* NVM Data In */ #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ -#define E1000_EECD_FWE_MASK 0x00000030 -#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ -#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ -#define E1000_EECD_FWE_SHIFT 4 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ #define E1000_EECD_PRES 0x00000100 /* NVM Present */ @@ -1335,28 +982,28 @@ #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ #define E1000_EECD_SIZE_EX_SHIFT 11 -#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ -#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ -#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ -#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ -#define E1000_EECD_SECVAL_SHIFT 22 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ +#define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ #define E1000_FLUDONE_ATTEMPTS 20000 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ -#define E1000_I210_FIFO_SEL_RX 0x00 +#define E1000_I210_FIFO_SEL_RX 0x00 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 -#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ -#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ +#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ +/* Secure FLASH mode requires removing MSb */ +#define E1000_I210_FW_PTR_MASK 0x7FFF +/* Firmware code revision field word offset*/ +#define E1000_I210_FW_VER_OFFSET 328 + #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ #define E1000_NVM_RW_REG_START 1 /* Start operation */ @@ -1368,13 +1015,11 @@ /* NVM Word Offsets */ #define NVM_COMPAT 0x0003 #define NVM_ID_LED_SETTINGS 0x0004 -#define NVM_VERSION 0x0005 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ #define NVM_PHY_CLASS_WORD 0x0007 -#define NVM_ETRACK_WORD 0x0042 -#define NVM_COMB_VER_OFF 0x0083 -#define NVM_COMB_VER_PTR 0x003d - +#define E1000_I210_NVM_FW_MODULE_PTR 0x0010 +#define E1000_I350_NVM_FW_MODULE_PTR 0x0051 +#define NVM_FUTURE_INIT_WORD1 0x0019 #define NVM_MAC_ADDR 0x0000 #define NVM_SUB_DEV_ID 0x000B #define NVM_SUB_VEN_ID 0x000C @@ -1385,15 +1030,15 @@ #define NVM_LED_1_CFG 0x001C #define NVM_LED_0_2_CFG 0x001F -#define NVM_INIT_CONTROL1_REG 0x000A +#define NVM_COMPAT_VALID_CSUM 0x0001 +#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 + #define NVM_INIT_CONTROL2_REG 0x000F -#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 #define NVM_INIT_CONTROL3_PORT_B 0x0014 #define NVM_INIT_3GIO_3 0x001A #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 #define NVM_INIT_CONTROL3_PORT_A 0x0024 #define NVM_CFG 0x0012 -#define NVM_FLASH_VERSION 0x0032 #define NVM_ALT_MAC_ADDR_PTR 0x0037 #define NVM_CHECKSUM_REG 0x003F #define NVM_COMPATIBILITY_REG_3 0x0003 @@ -1419,9 +1064,7 @@ #define NVM_WORD0F_PAUSE_MASK 0x3000 #define NVM_WORD0F_PAUSE 0x1000 #define NVM_WORD0F_ASM_DIR 0x2000 -#define NVM_WORD0F_ANE 0x0800 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 -#define NVM_WORD0F_LPLU 0x0001 /* Mask bits for fields in Word 0x1a of the NVM */ #define NVM_WORD1A_ASPM_MASK 0x000C @@ -1435,7 +1078,7 @@ /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ #define NVM_SUM 0xBABA -#define NVM_MAC_ADDR_OFFSET 0 +/* PBA (printed board assembly) number words */ #define NVM_PBA_OFFSET_0 8 #define NVM_PBA_OFFSET_1 9 #define NVM_PBA_PTR_GUARD 0xFAFA @@ -1460,16 +1103,10 @@ #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ -#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ -#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ /* SPI NVM Status Register */ #define NVM_STATUS_RDY_SPI 0x01 -#define NVM_STATUS_WEN_SPI 0x02 -#define NVM_STATUS_BP0_SPI 0x04 -#define NVM_STATUS_BP1_SPI 0x08 -#define NVM_STATUS_WPEN_SPI 0x80 /* Word definitions for ID LED Settings */ #define ID_LED_RESERVED_0000 0x0000 @@ -1523,8 +1160,7 @@ #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ #define MAX_PHY_MULTI_PAGE_REG 0xF -/* Bit definitions for valid PHY IDs. */ -/* +/* Bit definitions for valid PHY IDs. * I = Integrated * E = External */ @@ -1532,7 +1168,6 @@ #define M88E1000_I_PHY_ID 0x01410C30 #define M88E1011_I_PHY_ID 0x01410C20 #define IGP01E1000_I_PHY_ID 0x02A80380 -#define M88E1011_I_REV_4 0x04 #define M88E1111_I_PHY_ID 0x01410CC0 #define M88E1112_E_PHY_ID 0x01410C90 #define I347AT4_E_PHY_ID 0x01410DC0 @@ -1547,6 +1182,7 @@ #define I82577_E_PHY_ID 0x01540050 #define I82578_E_PHY_ID 0x004DD040 #define I82579_E_PHY_ID 0x01540090 +#define I217_E_PHY_ID 0x015400A0 #define I82580_I_PHY_ID 0x015403A0 #define I350_I_PHY_ID 0x015403B0 #define I210_I_PHY_ID 0x01410C00 @@ -1556,8 +1192,6 @@ /* M88E1000 Specific Registers */ #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ -#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ -#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ @@ -1568,11 +1202,7 @@ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ /* M88E1000 PHY Specific Control Register */ -#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ -#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ -/* 1=CLK125 low, 0=CLK125 toggling */ -#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ @@ -1580,24 +1210,13 @@ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* Auto crossover enabled all speeds */ #define M88E1000_PSCR_AUTO_X_MODE 0x0060 -/* - * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold - * 0=Normal 10BASE-T Rx Threshold - */ -#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 -/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ -#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 -#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ -#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ /* M88E1000 PHY Specific Status Register */ -#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ -/* - * 0 = <50M +/* 0 = <50M * 1 = 50-80M * 2 = 80-110M * 3 = 110-140M @@ -1606,64 +1225,33 @@ #define M88E1000_PSSR_CABLE_LENGTH 0x0380 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ -#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ -#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 -/* M88E1000 Extended PHY Specific Control Register */ -#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ -/* - * 1 = Lost lock detect enabled. - * Will assert lost lock and bring - * link down if idle not seen - * within 1ms in 1000BASE-T - */ -#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the slave */ #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 -#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ - -/* M88E1111 Specific Registers */ -#define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */ -#define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */ - -/* M88E1111 page select register mask */ -#define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF -#define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F /* Intel I347AT4 Registers */ - #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ #define I347AT4_PAGE_SELECT 0x16 /* I347AT4 Extended PHY Specific Control Register */ -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 @@ -1685,14 +1273,7 @@ /* M88EC018 Rev 2 specific DownShift settings */ #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C @@ -1700,8 +1281,7 @@ /* BME1000 PHY Specific Control Register */ #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ -/* - * Bits... +/* Bits... * 15-5: page * 4-0: register offset */ @@ -1712,49 +1292,24 @@ /* GG82563 Specific Registers */ #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ -#define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */ -#define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */ -#define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */ -#define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */ #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ -/* Test Clock Control (use reg. 29 to select) */ -#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) /* MAC Specific Control Register */ #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) -#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */ #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ /* Page 193 - Port Control Registers */ /* Kumeran Mode Control */ #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) -#define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */ -#define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */ -#define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */ #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ -/* Rate Adaptation Control */ -#define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) /* Page 194 - KMRN Registers */ -/* FIFO's Control/Status */ -#define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) -#define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */ #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ -#define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */ -#define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */ -#define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */ -/* Link Partner Advertised Ability */ -#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) -#define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */ -/* Link Partner Advertised Next page */ -#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) -#define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */ /* MDI Control */ -#define E1000_MDIC_DATA_MASK 0x0000FFFF #define E1000_MDIC_REG_MASK 0x001F0000 #define E1000_MDIC_REG_SHIFT 16 #define E1000_MDIC_PHY_MASK 0x03E00000 @@ -1762,7 +1317,6 @@ #define E1000_MDIC_OP_WRITE 0x04000000 #define E1000_MDIC_OP_READ 0x08000000 #define E1000_MDIC_READY 0x10000000 -#define E1000_MDIC_INT_EN 0x20000000 #define E1000_MDIC_ERROR 0x40000000 #define E1000_MDIC_DEST 0x80000000 @@ -1834,38 +1388,13 @@ /* Lx power decision based on DMA coal */ #define E1000_PCIEMISC_LX_DECISION 0x00000080 +#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ -#define E1000_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ -/* Minimum time for 1000BASE-T where no data will be transmit following move out - * of EEE LPI Tx state - */ -#define E1000_TW_SYSTEM_1000_MASK 0x000000FF -/* Minimum time for 100BASE-T where no data will be transmit following move out - * of EEE LPI Tx state - */ -#define E1000_TW_SYSTEM_100_MASK 0x0000FF00 -#define E1000_TW_SYSTEM_100_SHIFT 8 -#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ -#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ -#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ -#define E1000_LTRMINV_SCALE_SHIFT 10 -/* Reg val to set scale to 1024 nsec */ -#define E1000_LTRMINV_SCALE_1024 2 -/* Reg val to set scale to 32768 nsec */ -#define E1000_LTRMINV_SCALE_32768 3 -#define E1000_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ -#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ -#define E1000_LTRMAXV_SCALE_SHIFT 10 -/* Reg val to set scale to 1024 nsec */ -#define E1000_LTRMAXV_SCALE_1024 2 -/* Reg val to set scale to 32768 nsec */ -#define E1000_LTRMAXV_SCALE_32768 3 -#define E1000_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ -/* Proxy Filer Control */ +/* Proxy Filter Control */ #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ @@ -1873,7 +1402,7 @@ #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ -#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */ +#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ /* Proxy Status */ #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_hw.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_hw.h index 50a5ce2c28..e8a8c174ca 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_hw.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -123,13 +123,16 @@ struct e1000_hw; #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 - #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 #define E1000_DEV_ID_PCH2_LV_V 0x1503 +#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A +#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B +#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A +#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 #define E1000_DEV_ID_82576 0x10C9 #define E1000_DEV_ID_82576_FIBER 0x10E6 #define E1000_DEV_ID_82576_SERDES 0x10E7 @@ -139,7 +142,9 @@ struct e1000_hw; #define E1000_DEV_ID_82576_NS_SERDES 0x1518 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D #define E1000_DEV_ID_82576_VF 0x10CA +#define E1000_DEV_ID_82576_VF_HV 0x152D #define E1000_DEV_ID_I350_VF 0x1520 +#define E1000_DEV_ID_I350_VF_HV 0x152F #define E1000_DEV_ID_82575EB_COPPER 0x10A7 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 @@ -165,6 +170,7 @@ struct e1000_hw; #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 + #define E1000_REVISION_0 0 #define E1000_REVISION_1 1 #define E1000_REVISION_2 2 @@ -206,6 +212,7 @@ enum e1000_mac_type { e1000_ich10lan, e1000_pchlan, e1000_pch2lan, + e1000_pch_lpt, e1000_82575, e1000_82576, e1000_82580, @@ -255,6 +262,7 @@ enum e1000_phy_type { e1000_phy_82578, e1000_phy_82577, e1000_phy_82579, + e1000_phy_i217, e1000_phy_82580, e1000_phy_vf, e1000_phy_i210, @@ -651,13 +659,13 @@ struct e1000_host_mng_command_info { #include "e1000_manage.h" #include "e1000_mbx.h" +/* Function pointers for the MAC. */ struct e1000_mac_operations { - /* Function pointers for the MAC. */ s32 (*init_params)(struct e1000_hw *); s32 (*id_led_init)(struct e1000_hw *); s32 (*blink_led)(struct e1000_hw *); + bool (*check_mng_mode)(struct e1000_hw *); s32 (*check_for_link)(struct e1000_hw *); - bool (*check_mng_mode)(struct e1000_hw *hw); s32 (*cleanup_led)(struct e1000_hw *); void (*clear_hw_cntrs)(struct e1000_hw *); void (*clear_vfta)(struct e1000_hw *); @@ -679,17 +687,12 @@ struct e1000_mac_operations { void (*rar_set)(struct e1000_hw *, u8*, u32); s32 (*read_mac_addr)(struct e1000_hw *); s32 (*validate_mdi_setting)(struct e1000_hw *); - s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); - s32 (*mng_write_cmd_header)(struct e1000_hw *hw, - struct e1000_host_mng_command_header*); - s32 (*mng_enable_host_if)(struct e1000_hw *); - s32 (*wait_autoneg)(struct e1000_hw *); + s32 (*set_obff_timer)(struct e1000_hw *, u32); s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); void (*release_swfw_sync)(struct e1000_hw *, u16); }; -/* - * When to use various PHY register access functions: +/* When to use various PHY register access functions: * * Func Caller * Function Does Does When to use @@ -731,6 +734,7 @@ struct e1000_phy_operations { s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); }; +/* Function pointers for the NVM. */ struct e1000_nvm_operations { s32 (*init_params)(struct e1000_hw *); s32 (*acquire)(struct e1000_hw *); @@ -785,6 +789,7 @@ struct e1000_mac_info { enum e1000_serdes_link_state serdes_link_state; bool serdes_has_link; bool tx_pkt_filtering; + u32 max_frame_size; }; struct e1000_phy_info { @@ -915,7 +920,7 @@ struct e1000_shadow_ram { bool modified; }; -#define E1000_SHADOW_RAM_WORDS 2048 +#define E1000_SHADOW_RAM_WORDS 2048 struct e1000_dev_spec_ich8lan { bool kmrn_lock_loss_workaround_enabled; @@ -924,6 +929,7 @@ struct e1000_dev_spec_ich8lan { E1000_MUTEX swflag_mutex; bool nvm_k1_enabled; bool eee_disable; + u16 eee_lp_ability; }; struct e1000_dev_spec_82575 { @@ -931,7 +937,9 @@ struct e1000_dev_spec_82575 { bool global_device_reset; bool eee_disable; bool module_plugged; + bool clear_semaphore_once; u32 mtu; + struct sfp_e1000_flags eth_flags; }; struct e1000_dev_spec_vf { diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.c index f8e8bad0d8..63302c0d37 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -38,7 +38,6 @@ static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw); static void e1000_release_nvm_i210(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw); -static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw); static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw); @@ -105,13 +104,14 @@ s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) } swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); - if (!(swfw_sync & fwmask)) + if (!(swfw_sync & (fwmask | swmask))) break; /* * Firmware currently using resource (fwmask) + * or other software thread using resource (swmask) */ - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); msec_delay_irq(5); i++; } @@ -125,7 +125,7 @@ s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) swfw_sync |= swmask; E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); out: return ret_val; @@ -152,7 +152,7 @@ void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) swfw_sync &= ~mask; E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); } /** @@ -164,12 +164,45 @@ void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw) { u32 swsm; - s32 ret_val = E1000_SUCCESS; s32 timeout = hw->nvm.word_size + 1; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_i210"); + /* Get the SW semaphore */ + while (i < timeout) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + + usec_delay(50); + i++; + } + + if (i == timeout) { + /* + * In rare circumstances, the driver may not have released the + * SW semaphore. Clear the semaphore once before giving up. + */ + if (hw->dev_spec._82575.clear_semaphore_once) { + hw->dev_spec._82575.clear_semaphore_once = FALSE; + e1000_put_hw_semaphore_generic(hw); + for (i = 0; i < timeout; i++) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + + usec_delay(50); + } + } + + /* If we do not have the semaphore here, we have to give up. */ + if (i == timeout) { + DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + return -E1000_ERR_NVM; + } + } + /* Get the FW semaphore. */ for (i = 0; i < timeout; i++) { swsm = E1000_READ_REG(hw, E1000_SWSM); @@ -186,31 +219,10 @@ static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_generic(hw); DEBUGOUT("Driver can't access the NVM\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; -} - -/** - * e1000_put_hw_semaphore_i210 - Release hardware semaphore - * @hw: pointer to the HW structure - * - * Release hardware semaphore used to access the PHY or NVM - **/ -static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw) -{ - u32 swsm; - - DEBUGFUNC("e1000_put_hw_semaphore_i210"); - - swsm = E1000_READ_REG(hw, E1000_SWSM); - - swsm &= ~E1000_SWSM_SWESMBI; - - E1000_WRITE_REG(hw, E1000_SWSM, swsm); + return E1000_SUCCESS; } /** @@ -364,8 +376,8 @@ out: * * Wrapper function to return data formerly found in the NVM. **/ -static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words, - u16 *data) +static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data) { s32 ret_val = E1000_SUCCESS; @@ -380,15 +392,40 @@ static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words, if (ret_val != E1000_SUCCESS) DEBUGOUT("MAC Addr not found in iNVM\n"); break; - case NVM_ID_LED_SETTINGS: case NVM_INIT_CTRL_2: - case NVM_INIT_CTRL_4: - case NVM_LED_1_CFG: - case NVM_LED_0_2_CFG: - e1000_read_invm_i211(hw, (u8)offset, data); + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_INIT_CTRL_2_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } break; - case NVM_COMPAT: - *data = ID_LED_DEFAULT_I210; + case NVM_INIT_CTRL_4: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_INIT_CTRL_4_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; + case NVM_LED_1_CFG: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_LED_1_CFG_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; + case NVM_LED_0_2_CFG: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_LED_0_2_CFG_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; + case NVM_ID_LED_SETTINGS: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = ID_LED_RESERVED_FFFF; + ret_val = E1000_SUCCESS; + } break; case NVM_SUB_DEV_ID: *data = hw->subsystem_device_id; @@ -554,26 +591,6 @@ out: return ret_val; } -/** - * e1000_get_flash_presence_i210 - Check if flash device is detected. - * @hw: pointer to the HW structure - * - **/ -static bool e1000_get_flash_presence_i210(struct e1000_hw *hw) -{ - u32 eec = 0; - bool ret_val = FALSE; - - DEBUGFUNC("e1000_get_flash_presence_i210"); - - eec = E1000_READ_REG(hw, E1000_EECD); - - if (eec & E1000_EECD_FLASH_DETECTED_I210) - ret_val = TRUE; - - return ret_val; -} - /** * e1000_update_flash_i210 - Commit EEPROM to the flash * @hw: pointer to the HW structure @@ -690,10 +707,7 @@ void e1000_init_function_pointers_i210(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_i210: - if (e1000_get_flash_presence_i210(hw)) - hw->nvm.ops.init_params = e1000_init_nvm_params_i210; - else - hw->nvm.ops.init_params = e1000_init_nvm_params_i211; + hw->nvm.ops.init_params = e1000_init_nvm_params_i210; break; case e1000_i211: hw->nvm.ops.init_params = e1000_init_nvm_params_i211; diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.h index a0cd93576d..d7711fe093 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_i210.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -43,8 +43,6 @@ s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_invm_i211(struct e1000_hw *hw, u8 address, u16 *data); -s32 e1000_check_for_copper_link_i210(struct e1000_hw *hw); -s32 e1000_set_ltr_i210(struct e1000_hw *hw, bool link); s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask); void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask); @@ -69,6 +67,15 @@ enum E1000_INVM_STRUCTURE_TYPE { #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 +#define E1000_INVM_ULT_BYTES_SIZE 8 +#define E1000_INVM_RECORD_SIZE_IN_BYTES 4 +#define E1000_INVM_VER_FIELD_ONE 0x1FF8 +#define E1000_INVM_VER_FIELD_TWO 0x7FE000 +#define E1000_INVM_IMGTYPE_FIELD 0x1F800000 + +#define E1000_INVM_MAJOR_MASK 0x3F0 +#define E1000_INVM_MINOR_MASK 0xF +#define E1000_INVM_MAJOR_SHIFT 4 #define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ @@ -77,4 +84,9 @@ enum E1000_INVM_STRUCTURE_TYPE { (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) +/* NVM offset defaults for I211 devices */ +#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243 +#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1 +#define NVM_LED_1_CFG_DEFAULT_I211 0x0184 +#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C #endif diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.c index 98aefc4fc0..bd94355527 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,8 +32,7 @@ ******************************************************************************/ /*$FreeBSD$*/ -/* - * 82562G 10/100 Network Connection +/* 82562G 10/100 Network Connection * 82562G-2 10/100 Network Connection * 82562GT 10/100 Network Connection * 82562GT-2 10/100 Network Connection @@ -64,10 +63,6 @@ #include "e1000_api.h" -static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); -static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); -static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); @@ -75,6 +70,7 @@ static void e1000_release_nvm_ich8lan(struct e1000_hw *hw); static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); +static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count); @@ -99,6 +95,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex); static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); @@ -111,8 +108,6 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw); static s32 e1000_led_off_pchlan(struct e1000_hw *hw); static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); -static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); -static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, @@ -123,21 +118,13 @@ static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data); static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte); -static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, - u32 offset, u8 data); -static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, - u8 size, u16 data); static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); -static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); -static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) - -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ +static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ /* Offset 04h HSFSTS */ @@ -180,20 +167,190 @@ union ich8_hws_flash_regacc { u16 regval; }; -static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) +/** + * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers + * @hw: pointer to the HW structure + * + * Test access to the PHY registers by reading the PHY ID registers. If + * the PHY ID is already known (e.g. resume path) compare it with known ID, + * otherwise assume the read PHY ID is correct if it is valid. + * + * Assumes the sw/fw/hw semaphore is already acquired. + **/ +static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) { - u32 ctrl; + u16 phy_reg = 0; + u32 phy_id = 0; + s32 ret_val; + u16 retry_count; - DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan"); + for (retry_count = 0; retry_count < 2; retry_count++) { + ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); + if (ret_val || (phy_reg == 0xFFFF)) + continue; + phy_id = (u32)(phy_reg << 16); - ctrl = E1000_READ_REG(hw, E1000_CTRL); - ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; - ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; - E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - usec_delay(10); - ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; - E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); + if (ret_val || (phy_reg == 0xFFFF)) { + phy_id = 0; + continue; + } + phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); + break; + } + + if (hw->phy.id) { + if (hw->phy.id == phy_id) + return TRUE; + } else if (phy_id) { + hw->phy.id = phy_id; + hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); + return TRUE; + } + + /* In case the PHY needs to be in mdio slow mode, + * set slow mode and try to get the PHY id again. + */ + hw->phy.ops.release(hw); + ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (!ret_val) + ret_val = e1000_get_phy_id(hw); + hw->phy.ops.acquire(hw); + + return !ret_val; +} + +/** + * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds + * @hw: pointer to the HW structure + * + * Workarounds/flow necessary for PHY initialization during driver load + * and resume paths. + **/ +static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) +{ + u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); + s32 ret_val; + u16 phy_reg; + + DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); + + /* Gate automatic PHY configuration by hardware on managed and + * non-managed 82579 and newer adapters. + */ + e1000_gate_hw_phy_config_ich8lan(hw, TRUE); + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) { + DEBUGOUT("Failed to initialize PHY flow\n"); + goto out; + } + + /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is + * inaccessible and resetting the PHY is not blocked, toggle the + * LANPHYPC Value bit to force the interconnect to PCIe mode. + */ + switch (hw->mac.type) { + case e1000_pch_lpt: + if (e1000_phy_is_accessible_pchlan(hw)) + break; + + /* Before toggling LANPHYPC, see if PHY is accessible by + * forcing MAC to SMBus mode first. + */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + + /* fall-through */ + case e1000_pch2lan: + if (e1000_phy_is_accessible_pchlan(hw)) { + if (hw->mac.type == e1000_pch_lpt) { + /* Unforce SMBus mode in PHY */ + hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, + &phy_reg); + phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; + hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, + phy_reg); + + /* Unforce SMBus mode in MAC */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + } + break; + } + + /* fall-through */ + case e1000_pchlan: + if ((hw->mac.type == e1000_pchlan) && + (fwsm & E1000_ICH_FWSM_FW_VALID)) + break; + + if (hw->phy.ops.check_reset_block(hw)) { + DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); + break; + } + + DEBUGOUT("Toggling LANPHYPC\n"); + + /* Set Phy Config Counter to 50msec */ + mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); + mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); + + if (hw->mac.type == e1000_pch_lpt) { + /* Toggling LANPHYPC brings the PHY out of SMBus mode + * So ensure that the MAC is also out of SMBus mode + */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + } + + /* Toggle LANPHYPC Value bit */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL); + mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; + mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; + E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); + E1000_WRITE_FLUSH(hw); + usec_delay(10); + mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; + E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); + E1000_WRITE_FLUSH(hw); + if (hw->mac.type < e1000_pch_lpt) { + msec_delay(50); + } else { + u16 count = 20; + do { + msec_delay(5); + } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & + E1000_CTRL_EXT_LPCD) && count--); + } + break; + default: + break; + } + + hw->phy.ops.release(hw); + + /* Reset the PHY before any access to it. Doing so, ensures + * that the PHY is in a known good state before we read/write + * PHY registers. The generic reset is sufficient here, + * because we haven't determined the PHY type yet. + */ + ret_val = e1000_phy_hw_reset_generic(hw); + +out: + /* Ungate automatic PHY configuration on non-managed 82579 */ + if ((hw->mac.type == e1000_pch2lan) && + !(fwsm & E1000_ICH_FWSM_FW_VALID)) { + msec_delay(10); + e1000_gate_hw_phy_config_ich8lan(hw, FALSE); + } + + return ret_val; } /** @@ -205,7 +362,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_init_phy_params_pchlan"); @@ -230,70 +387,40 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; - if (!hw->phy.ops.check_reset_block(hw)) { - u32 fwsm = E1000_READ_REG(hw, E1000_FWSM); - - /* - * The MAC-PHY interconnect may still be in SMBus mode after - * Sx->S0. If resetting the PHY is not blocked, toggle the - * LANPHYPC Value bit to force the interconnect to PCIe mode. - */ - e1000_toggle_lanphypc_value_ich8lan(hw); - msec_delay(50); - - /* - * Gate automatic PHY configuration by hardware on - * non-managed 82579 - */ - if ((hw->mac.type == e1000_pch2lan) && - !(fwsm & E1000_ICH_FWSM_FW_VALID)) - e1000_gate_hw_phy_config_ich8lan(hw, TRUE); - - /* - * Reset the PHY before any access to it. Doing so, ensures - * that the PHY is in a known good state before we read/write - * PHY registers. The generic reset is sufficient here, - * because we haven't determined the PHY type yet. - */ - ret_val = e1000_phy_hw_reset_generic(hw); - if (ret_val) - goto out; - - /* Ungate automatic PHY configuration on non-managed 82579 */ - if ((hw->mac.type == e1000_pch2lan) && - !(fwsm & E1000_ICH_FWSM_FW_VALID)) { - msec_delay(10); - e1000_gate_hw_phy_config_ich8lan(hw, FALSE); - } - } - phy->id = e1000_phy_unknown; - switch (hw->mac.type) { - default: - ret_val = e1000_get_phy_id(hw); - if (ret_val) - goto out; - if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) + + ret_val = e1000_init_phy_workarounds_pchlan(hw); + if (ret_val) + return ret_val; + + if (phy->id == e1000_phy_unknown) + switch (hw->mac.type) { + default: + ret_val = e1000_get_phy_id(hw); + if (ret_val) + return ret_val; + if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) + break; + /* fall-through */ + case e1000_pch2lan: + case e1000_pch_lpt: + /* In case the PHY needs to be in mdio slow mode, + * set slow mode and try to get the PHY id again. + */ + ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (ret_val) + return ret_val; + ret_val = e1000_get_phy_id(hw); + if (ret_val) + return ret_val; break; - /* fall-through */ - case e1000_pch2lan: - /* - * In case the PHY needs to be in mdio slow mode, - * set slow mode and try to get the PHY id again. - */ - ret_val = e1000_set_mdio_slow_mode_hv(hw); - if (ret_val) - goto out; - ret_val = e1000_get_phy_id(hw); - if (ret_val) - goto out; - break; - } + } phy->type = e1000_get_phy_type_from_id(phy->id); switch (phy->type) { case e1000_phy_82577: case e1000_phy_82579: + case e1000_phy_i217: phy->ops.check_polarity = e1000_check_polarity_82577; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; @@ -312,7 +439,6 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) break; } -out: return ret_val; } @@ -325,7 +451,7 @@ out: static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 i = 0; DEBUGFUNC("e1000_init_phy_params_ich8lan"); @@ -346,8 +472,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) phy->ops.power_up = e1000_power_up_phy_copper; phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; - /* - * We may need to do this twice - once for IGP and if that fails, + /* We may need to do this twice - once for IGP and if that fails, * we'll set BM func pointers and try again */ ret_val = e1000_determine_phy_address(hw); @@ -357,7 +482,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) ret_val = e1000_determine_phy_address(hw); if (ret_val) { DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); - goto out; + return ret_val; } } @@ -367,7 +492,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) msec_delay(1); ret_val = e1000_get_phy_id(hw); if (ret_val) - goto out; + return ret_val; } /* Verify phy id */ @@ -401,12 +526,11 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; break; default: - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; + break; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -421,7 +545,6 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) struct e1000_nvm_info *nvm = &hw->nvm; struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 gfpreg, sector_base_addr, sector_end_addr; - s32 ret_val = E1000_SUCCESS; u16 i; DEBUGFUNC("e1000_init_nvm_params_ich8lan"); @@ -429,16 +552,14 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) /* Can't read flash registers if the register set isn't mapped. */ if (!hw->flash_address) { DEBUGOUT("ERROR: Flash registers not mapped\n"); - ret_val = -E1000_ERR_CONFIG; - goto out; + return -E1000_ERR_CONFIG; } nvm->type = e1000_nvm_flash_sw; gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); - /* - * sector_X_addr is a "sector"-aligned address (4096 bytes) + /* sector_X_addr is a "sector"-aligned address (4096 bytes) * Add 1 to sector_end_addr since this sector is included in * the overall size. */ @@ -448,8 +569,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) /* flash_base_addr is byte-aligned */ nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; - /* - * find total size of the NVM, then cut in half since the total + /* find total size of the NVM, then cut in half since the total * size represents two separate NVM banks. */ nvm->flash_bank_size = (sector_end_addr - sector_base_addr) @@ -478,8 +598,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; nvm->ops.write = e1000_write_nvm_ich8lan; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -536,7 +655,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) /* clear hardware counters */ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; - /* LED operations */ + /* LED and other operations */ switch (mac->type) { case e1000_ich8lan: case e1000_ich9lan: @@ -558,10 +677,11 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) case e1000_pch2lan: mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; mac->ops.rar_set = e1000_rar_set_pch2lan; + /* fall-through */ + case e1000_pch_lpt: /* multicast address update for pch2 */ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_pch2lan; - /* fall-through */ case e1000_pchlan: /* check management mode */ mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; @@ -579,55 +699,385 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) break; } -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) if (mac->type == e1000_pch_lpt) { + mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; + mac->ops.rar_set = e1000_rar_set_pch_lpt; + mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; + mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; } -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ /* Enable PCS Lock-loss workaround for ICH8 */ if (mac->type == e1000_ich8lan) e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); - /* Gate automatic PHY configuration by hardware on managed 82579 */ - if ((mac->type == e1000_pch2lan) && - (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) - e1000_gate_hw_phy_config_ich8lan(hw, TRUE); - return E1000_SUCCESS; } +/** + * __e1000_access_emi_reg_locked - Read/write EMI register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: pointer to value to read/write from/to the EMI address + * @read: boolean flag to indicate read or write + * + * This helper function assumes the SW/FW/HW Semaphore is already acquired. + **/ +static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, + u16 *data, bool read) +{ + s32 ret_val; + + DEBUGFUNC("__e1000_access_emi_reg_locked"); + + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); + if (ret_val) + return ret_val; + + if (read) + ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, + data); + else + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, + *data); + + return ret_val; +} + +/** + * e1000_read_emi_reg_locked - Read Extended Management Interface register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: value to be read from the EMI address + * + * Assumes the SW/FW/HW Semaphore is already acquired. + **/ +s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) +{ + DEBUGFUNC("e1000_read_emi_reg_locked"); + + return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); +} + +/** + * e1000_write_emi_reg_locked - Write Extended Management Interface register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: value to be written to the EMI address + * + * Assumes the SW/FW/HW Semaphore is already acquired. + **/ +static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) +{ + DEBUGFUNC("e1000_read_emi_reg_locked"); + + return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); +} + /** * e1000_set_eee_pchlan - Enable/disable EEE support * @hw: pointer to the HW structure * - * Enable/disable EEE based on setting in dev_spec structure. The bits in - * the LPI Control register will remain set only if/when link is up. + * Enable/disable EEE based on setting in dev_spec structure, the duplex of + * the link and the EEE capabilities of the link partner. The LPI Control + * register bits will remain set only if/when link is up. **/ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - s32 ret_val = E1000_SUCCESS; - u16 phy_reg; + s32 ret_val; + u16 lpi_ctrl; DEBUGFUNC("e1000_set_eee_pchlan"); - if (hw->phy.type != e1000_phy_82579) - goto out; + if ((hw->phy.type != e1000_phy_82579) && + (hw->phy.type != e1000_phy_i217)) + return E1000_SUCCESS; - ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); + ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; - if (dev_spec->eee_disable) - phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; - else - phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; + ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); + if (ret_val) + goto release; + + /* Clear bits that enable EEE in various speeds */ + lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; + + /* Enable EEE if not disabled by user */ + if (!dev_spec->eee_disable) { + u16 lpa, pcs_status, data; + + /* Save off link partner's EEE ability */ + switch (hw->phy.type) { + case e1000_phy_82579: + lpa = I82579_EEE_LP_ABILITY; + pcs_status = I82579_EEE_PCS_STATUS; + break; + case e1000_phy_i217: + lpa = I217_EEE_LP_ABILITY; + pcs_status = I217_EEE_PCS_STATUS; + break; + default: + ret_val = -E1000_ERR_PHY; + goto release; + } + ret_val = e1000_read_emi_reg_locked(hw, lpa, + &dev_spec->eee_lp_ability); + if (ret_val) + goto release; + + /* Enable EEE only for speeds in which the link partner is + * EEE capable. + */ + if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) + lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; + + if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { + hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); + if (data & NWAY_LPAR_100TX_FD_CAPS) + lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; + else + /* EEE is not supported in 100Half, so ignore + * partner's EEE in 100 ability if full-duplex + * is not advertised. + */ + dev_spec->eee_lp_ability &= + ~I82579_EEE_100_SUPPORTED; + } + + /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ + ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); + if (ret_val) + goto release; + } + + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); +release: + hw->phy.ops.release(hw); - ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); -out: return ret_val; } +/** + * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP + * @hw: pointer to the HW structure + * @link: link up bool flag + * + * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications + * preventing further DMA write requests. Workaround the issue by disabling + * the de-assertion of the clock request when in 1Gpbs mode. + **/ +static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) +{ + u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); + s32 ret_val = E1000_SUCCESS; + + if (link && (E1000_READ_REG(hw, E1000_STATUS) & + E1000_STATUS_SPEED_1000)) { + u16 kmrn_reg; + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + return ret_val; + + ret_val = + e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, + &kmrn_reg); + if (ret_val) + goto release; + + ret_val = + e1000_write_kmrn_reg_locked(hw, + E1000_KMRNCTRLSTA_K1_CONFIG, + kmrn_reg & + ~E1000_KMRNCTRLSTA_K1_ENABLE); + if (ret_val) + goto release; + + usec_delay(10); + + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); + + ret_val = + e1000_write_kmrn_reg_locked(hw, + E1000_KMRNCTRLSTA_K1_CONFIG, + kmrn_reg); +release: + hw->phy.ops.release(hw); + } else { + /* clear FEXTNVM6 bit 8 on link down or 10/100 */ + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); + } + + return ret_val; +} + +static u64 e1000_ltr2ns(u16 ltr) +{ + u32 value, scale; + + /* Determine the latency in nsec based on the LTR value & scale */ + value = ltr & E1000_LTRV_VALUE_MASK; + scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; + + return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); +} + +/** + * e1000_platform_pm_pch_lpt - Set platform power management values + * @hw: pointer to the HW structure + * @link: bool indicating link status + * + * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" + * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed + * when link is up (which must not exceed the maximum latency supported + * by the platform), otherwise specify there is no LTR requirement. + * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop + * latencies in the LTR Extended Capability Structure in the PCIe Extended + * Capability register set, on this device LTR is set by writing the + * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and + * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) + * message to the PMC. + * + * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) + * high-water mark. + **/ +static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) +{ + u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | + link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; + u16 lat_enc = 0; /* latency encoded */ + s32 obff_hwm = 0; + + DEBUGFUNC("e1000_platform_pm_pch_lpt"); + + if (link) { + u16 speed, duplex, scale = 0; + u16 max_snoop, max_nosnoop; + u16 max_ltr_enc; /* max LTR latency encoded */ + s64 lat_ns; /* latency (ns) */ + s64 value; + u32 rxa; + + if (!hw->mac.max_frame_size) { + DEBUGOUT("max_frame_size not set.\n"); + return -E1000_ERR_CONFIG; + } + + hw->mac.ops.get_link_up_info(hw, &speed, &duplex); + if (!speed) { + DEBUGOUT("Speed not set.\n"); + return -E1000_ERR_CONFIG; + } + + /* Rx Packet Buffer Allocation size (KB) */ + rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; + + /* Determine the maximum latency tolerated by the device. + * + * Per the PCIe spec, the tolerated latencies are encoded as + * a 3-bit encoded scale (only 0-5 are valid) multiplied by + * a 10-bit value (0-1023) to provide a range from 1 ns to + * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, + * 1=2^5ns, 2=2^10ns,...5=2^25ns. + */ + lat_ns = ((s64)rxa * 1024 - + (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; + if (lat_ns < 0) + lat_ns = 0; + else + lat_ns /= speed; + + value = lat_ns; + while (value > E1000_LTRV_VALUE_MASK) { + scale++; + value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); + } + if (scale > E1000_LTRV_SCALE_MAX) { + DEBUGOUT1("Invalid LTR latency scale %d\n", scale); + return -E1000_ERR_CONFIG; + } + lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); + + /* Determine the maximum latency tolerated by the platform */ + e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); + e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); + max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); + + if (lat_enc > max_ltr_enc) { + lat_enc = max_ltr_enc; + lat_ns = e1000_ltr2ns(max_ltr_enc); + } + + if (lat_ns) { + lat_ns *= speed * 1000; + lat_ns /= 8; + lat_ns /= 1000000000; + obff_hwm = (s32)(rxa - lat_ns); + } + + if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { + DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); + return -E1000_ERR_CONFIG; + } + } + + /* Set Snoop and No-Snoop latencies the same */ + reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); + E1000_WRITE_REG(hw, E1000_LTRV, reg); + + /* Set OBFF high water mark */ + reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; + reg |= obff_hwm; + E1000_WRITE_REG(hw, E1000_SVT, reg); + + /* Enable OBFF */ + reg = E1000_READ_REG(hw, E1000_SVCR); + reg |= E1000_SVCR_OFF_EN; + /* Always unblock interrupts to the CPU even when the system is + * in OBFF mode. This ensures that small round-robin traffic + * (like ping) does not get dropped or experience long latency. + */ + reg |= E1000_SVCR_OFF_MASKINT; + E1000_WRITE_REG(hw, E1000_SVCR, reg); + + return E1000_SUCCESS; +} + +/** + * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer + * @hw: pointer to the HW structure + * @itr: interrupt throttling rate + * + * Configure OBFF with the updated interrupt rate. + **/ +static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) +{ + u32 svcr; + s32 timer; + + DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); + + /* Convert ITR value into microseconds for OBFF timer */ + timer = itr & E1000_ITR_MASK; + timer = (timer * E1000_ITR_MULT) / 1000; + + if ((timer < 0) || (timer > E1000_ITR_MASK)) { + DEBUGOUT1("Invalid OBFF timer %d\n", timer); + return -E1000_ERR_CONFIG; + } + + svcr = E1000_READ_REG(hw, E1000_SVCR); + svcr &= ~E1000_SVCR_OFF_TIMER_MASK; + svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; + E1000_WRITE_REG(hw, E1000_SVCR, svcr); + + return E1000_SUCCESS; +} + /** * e1000_check_for_copper_link_ich8lan - Check for link (Copper) * @hw: pointer to the HW structure @@ -645,39 +1095,77 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); - /* - * We only want to go out to the PHY registers to see if Auto-Neg + /* We only want to go out to the PHY registers to see if Auto-Neg * has completed and/or if our link status has changed. The * get_link_status flag is set upon receiving a Link Status * Change or Rx Sequence Error interrupt. */ - if (!mac->get_link_status) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!mac->get_link_status) + return E1000_SUCCESS; - /* - * First we want to see if the MII Status Register reports + /* First we want to see if the MII Status Register reports * link. If so, then we want to get the current speed/duplex * of the PHY. */ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); if (ret_val) - goto out; + return ret_val; if (hw->mac.type == e1000_pchlan) { ret_val = e1000_k1_gig_workaround_hv(hw, link); if (ret_val) - goto out; + return ret_val; + } + + /* When connected at 10Mbps half-duplex, 82579 parts are excessively + * aggressive resulting in many collisions. To avoid this, increase + * the IPG and reduce Rx latency in the PHY. + */ + if ((hw->mac.type == e1000_pch2lan) && link) { + u32 reg; + reg = E1000_READ_REG(hw, E1000_STATUS); + if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { + reg = E1000_READ_REG(hw, E1000_TIPG); + reg &= ~E1000_TIPG_IPGT_MASK; + reg |= 0xFF; + E1000_WRITE_REG(hw, E1000_TIPG, reg); + + /* Reduce Rx latency in analog PHY */ + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + return ret_val; + + ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0); + + hw->phy.ops.release(hw); + + if (ret_val) + return ret_val; + } + } + + /* Work-around I218 hang issue */ + if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || + (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { + ret_val = e1000_k1_workaround_lpt_lp(hw, link); + if (ret_val) + return ret_val; } -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) if (hw->mac.type == e1000_pch_lpt) { + /* Set platform power management values for Latency Tolerance + * Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF). + */ + ret_val = e1000_platform_pm_pch_lpt(hw, link); + if (ret_val) + return ret_val; } -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ + /* Clear link partner's EEE ability */ + hw->dev_spec.ich8lan.eee_lp_ability = 0; + if (!link) - goto out; /* No link detected */ + return E1000_SUCCESS; /* No link detected */ mac->get_link_status = FALSE; @@ -685,17 +1173,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) case e1000_pch2lan: ret_val = e1000_k1_workaround_lv(hw); if (ret_val) - goto out; + return ret_val; /* fall-thru */ case e1000_pchlan: if (hw->phy.type == e1000_phy_82578) { ret_val = e1000_link_stall_workaround_hv(hw); if (ret_val) - goto out; + return ret_val; } - /* - * Workaround for PCHx parts in half-duplex: + /* Workaround for PCHx parts in half-duplex: * Set the number of preambles removed from the packet * when it is passed from the PHY to the MAC to prevent * the MAC from misinterpreting the packet type. @@ -713,8 +1200,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) break; } - /* - * Check if there was DownShift, must be checked + /* Check if there was DownShift, must be checked * immediately after link-up */ e1000_check_downshift_generic(hw); @@ -722,26 +1208,21 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) /* Enable/Disable EEE after link up */ ret_val = e1000_set_eee_pchlan(hw); if (ret_val) - goto out; + return ret_val; - /* - * If we are forcing speed/duplex, then we simply return since + /* If we are forcing speed/duplex, then we simply return since * we have already determined whether we have link or not. */ - if (!mac->autoneg) { - ret_val = -E1000_ERR_CONFIG; - goto out; - } + if (!mac->autoneg) + return -E1000_ERR_CONFIG; - /* - * Auto-Neg is enabled. Auto Speed Detection takes care + /* Auto-Neg is enabled. Auto Speed Detection takes care * of MAC speed/duplex configuration. So we only need to * configure Collision Distance in the MAC. */ - hw->mac.ops.config_collision_dist(hw); + mac->ops.config_collision_dist(hw); - /* - * Configure Flow Control now that Auto-Neg has completed. + /* Configure Flow Control now that Auto-Neg has completed. * First, we need to restore the desired flow control * settings because we may have had to re-autoneg with a * different link partner. @@ -750,7 +1231,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) if (ret_val) DEBUGOUT("Error configuring flow control\n"); -out: return ret_val; } @@ -774,6 +1254,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) break; case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: hw->phy.ops.init_params = e1000_init_phy_params_pchlan; break; default: @@ -957,8 +1438,7 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) DEBUGFUNC("e1000_rar_set_pch2lan"); - /* - * HW expects these in little endian so we reverse the byte order + /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ rar_low = ((u32) addr[0] | @@ -980,11 +1460,19 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) } if (index < hw->mac.rar_entry_count) { + s32 ret_val; + + ret_val = e1000_acquire_swflag_ich8lan(hw); + if (ret_val) + goto out; + E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); E1000_WRITE_FLUSH(hw); E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); E1000_WRITE_FLUSH(hw); + e1000_release_swflag_ich8lan(hw); + /* verify the register updates */ if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) @@ -994,6 +1482,85 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) (index - 1), E1000_READ_REG(hw, E1000_FWSM)); } +out: + DEBUGOUT1("Failed to write receive address at index %d\n", index); +} + +/** + * e1000_rar_set_pch_lpt - Set receive address registers + * @hw: pointer to the HW structure + * @addr: pointer to the receive address + * @index: receive address array register + * + * Sets the receive address register array at index to the address passed + * in by addr. For LPT, RAR[0] is the base address register that is to + * contain the MAC address. SHRA[0-10] are the shared receive address + * registers that are shared between the Host and manageability engine (ME). + **/ +static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) +{ + u32 rar_low, rar_high; + u32 wlock_mac; + + DEBUGFUNC("e1000_rar_set_pch_lpt"); + + /* HW expects these in little endian so we reverse the byte order + * from network order (big endian) to little endian + */ + rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | + ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); + + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); + + /* If MAC address zero, no need to set the AV bit */ + if (rar_low || rar_high) + rar_high |= E1000_RAH_AV; + + if (index == 0) { + E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); + E1000_WRITE_FLUSH(hw); + return; + } + + /* The manageability engine (ME) can lock certain SHRAR registers that + * it is using - those registers are unavailable for use. + */ + if (index < hw->mac.rar_entry_count) { + wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & + E1000_FWSM_WLOCK_MAC_MASK; + wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; + + /* Check if all SHRAR registers are locked */ + if (wlock_mac == 1) + goto out; + + if ((wlock_mac == 0) || (index <= wlock_mac)) { + s32 ret_val; + + ret_val = e1000_acquire_swflag_ich8lan(hw); + + if (ret_val) + goto out; + + E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), + rar_low); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), + rar_high); + E1000_WRITE_FLUSH(hw); + + e1000_release_swflag_ich8lan(hw); + + /* verify the register updates */ + if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && + (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) + return; + } + } + +out: DEBUGOUT1("Failed to write receive address at index %d\n", index); } @@ -1072,21 +1639,34 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw) { u16 phy_data; u32 strap = E1000_READ_REG(hw, E1000_STRAP); - s32 ret_val = E1000_SUCCESS; + u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> + E1000_STRAP_SMT_FREQ_SHIFT; + s32 ret_val; strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); if (ret_val) - goto out; + return ret_val; phy_data &= ~HV_SMB_ADDR_MASK; phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; - ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); -out: - return ret_val; + if (hw->phy.type == e1000_phy_i217) { + /* Restore SMBus frequency */ + if (freq--) { + phy_data &= ~HV_SMB_ADDR_FREQ_MASK; + phy_data |= (freq & (1 << 0)) << + HV_SMB_ADDR_FREQ_LOW_SHIFT; + phy_data |= (freq & (1 << 1)) << + (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); + } else { + DEBUGOUT("Unsupported SMB frequency in PHY\n"); + } + } + + return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); } /** @@ -1105,8 +1685,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); - /* - * Initialize the PHY from the NVM on ICH platforms. This + /* Initialize the PHY from the NVM on ICH platforms. This * is needed due to an issue where the NVM configuration is * not properly autoloaded after power transitions. * Therefore, after each PHY reset, we will load the @@ -1125,6 +1704,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) /* Fall-thru */ case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; break; default: @@ -1137,45 +1717,42 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) data = E1000_READ_REG(hw, E1000_FEXTNVM); if (!(data & sw_cfg_mask)) - goto out; + goto release; - /* - * Make sure HW does not configure LCD from PHY + /* Make sure HW does not configure LCD from PHY * extended configuration before SW configuration */ data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - if (!(hw->mac.type == e1000_pch2lan)) { - if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) - goto out; - } + if ((hw->mac.type < e1000_pch2lan) && + (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) + goto release; cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; if (!cnf_size) - goto out; + goto release; cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; - if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && - (hw->mac.type == e1000_pchlan)) || - (hw->mac.type == e1000_pch2lan)) { - /* - * HW configures the SMBus address and LEDs when the + if (((hw->mac.type == e1000_pchlan) && + !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || + (hw->mac.type > e1000_pchlan)) { + /* HW configures the SMBus address and LEDs when the * OEM and LCD Write Enable bits are set in the NVM. * When both NVM bits are cleared, SW will configure * them instead. */ ret_val = e1000_write_smbus_addr(hw); if (ret_val) - goto out; + goto release; data = E1000_READ_REG(hw, E1000_LEDCTL); ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, (u16)data); if (ret_val) - goto out; + goto release; } /* Configure LCD from extended configuration region. */ @@ -1187,12 +1764,12 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, ®_data); if (ret_val) - goto out; + goto release; ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 1, ®_addr); if (ret_val) - goto out; + goto release; /* Save off the PHY page for future writes. */ if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { @@ -1206,10 +1783,10 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, reg_data); if (ret_val) - goto out; + goto release; } -out: +release: hw->phy.ops.release(hw); return ret_val; } @@ -1233,12 +1810,12 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) DEBUGFUNC("e1000_k1_gig_workaround_hv"); if (hw->mac.type != e1000_pchlan) - goto out; + return E1000_SUCCESS; /* Wrap the whole flow with the sw flag */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ if (link) { @@ -1292,7 +1869,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) release: hw->phy.ops.release(hw); -out: + return ret_val; } @@ -1308,7 +1885,7 @@ out: **/ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u32 ctrl_reg = 0; u32 ctrl_ext = 0; u32 reg = 0; @@ -1319,7 +1896,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, &kmrn_reg); if (ret_val) - goto out; + return ret_val; if (k1_enable) kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; @@ -1329,7 +1906,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, kmrn_reg); if (ret_val) - goto out; + return ret_val; usec_delay(20); ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); @@ -1347,8 +1924,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) E1000_WRITE_FLUSH(hw); usec_delay(20); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1368,28 +1944,28 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) DEBUGFUNC("e1000_oem_bits_config_ich8lan"); - if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) + if (hw->mac.type < e1000_pchlan) return ret_val; ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val; - if (!(hw->mac.type == e1000_pch2lan)) { + if (hw->mac.type == e1000_pchlan) { mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) - goto out; + goto release; } mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) - goto out; + goto release; mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); if (ret_val) - goto out; + goto release; oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); @@ -1399,10 +1975,6 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) oem_reg |= HV_OEM_BITS_LPLU; - - /* Set Restart auto-neg to activate the bits */ - if (!hw->phy.ops.check_reset_block(hw)) - oem_reg |= HV_OEM_BITS_RESTART_AN; } else { if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) @@ -1413,9 +1985,14 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) oem_reg |= HV_OEM_BITS_LPLU; } + /* Set Restart auto-neg to activate the bits */ + if ((d0_state || (hw->mac.type != e1000_pchlan)) && + !hw->phy.ops.check_reset_block(hw)) + oem_reg |= HV_OEM_BITS_RESTART_AN; + ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); -out: +release: hw->phy.ops.release(hw); return ret_val; @@ -1456,13 +2033,13 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); if (hw->mac.type != e1000_pchlan) - goto out; + return E1000_SUCCESS; /* Set MDIO slow mode before any other MDIO access */ if (hw->phy.type == e1000_phy_82577) { ret_val = e1000_set_mdio_slow_mode_hv(hw); if (ret_val) - goto out; + return ret_val; } if (((hw->phy.type == e1000_phy_82577) && @@ -1471,18 +2048,17 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) /* Disable generation of early preamble */ ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); if (ret_val) - goto out; + return ret_val; /* Preamble tuning for SSC */ ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); if (ret_val) - goto out; + return ret_val; } if (hw->phy.type == e1000_phy_82578) { - /* - * Return registers to default by doing a soft reset then + /* Return registers to default by doing a soft reset then * writing 0x3140 to the control register. */ if (hw->phy.revision < 2) { @@ -1495,34 +2071,38 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) /* Select page 0 */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; hw->phy.addr = 1; ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); hw->phy.ops.release(hw); if (ret_val) - goto out; + return ret_val; - /* - * Configure the K1 Si workaround during phy reset assuming there is + /* Configure the K1 Si workaround during phy reset assuming there is * link so that it disables K1 if link is in 1Gbps. */ ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); if (ret_val) - goto out; + return ret_val; /* Workaround for link disconnects on a busy hub in half duplex */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); if (ret_val) goto release; ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); + if (ret_val) + goto release; + + /* set MSE higher to enable link to stay up when noise is high */ + ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); release: hw->phy.ops.release(hw); -out: + return ret_val; } @@ -1600,19 +2180,18 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); - if (hw->mac.type != e1000_pch2lan) - goto out; + if (hw->mac.type < e1000_pch2lan) + return E1000_SUCCESS; /* disable Rx path while enabling/disabling workaround */ hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); if (ret_val) - goto out; + return ret_val; if (enable) { - /* - * Write Rx addresses (rar_entry_count for RAL/H, +4 for + /* Write Rx addresses (rar_entry_count for RAL/H, +4 for * SHRAL/H) and initial CRC values to the MAC */ for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { @@ -1651,24 +2230,24 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) E1000_KMRNCTRLSTA_CTRL_OFFSET, &data); if (ret_val) - goto out; + return ret_val; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_CTRL_OFFSET, data | (1 << 0)); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, &data); if (ret_val) - goto out; + return ret_val; data &= ~(0xF << 8); data |= (0xB << 8); ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, data); if (ret_val) - goto out; + return ret_val; /* Enable jumbo frame workaround in the PHY */ hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); @@ -1676,26 +2255,26 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) data |= (0x37 << 5); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); data &= ~(1 << 13); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); data &= ~(0x3FF << 2); data |= (0x1A << 2); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10)); if (ret_val) - goto out; + return ret_val; } else { /* Write MAC register values back to h/w defaults */ mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); @@ -1710,58 +2289,55 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) E1000_KMRNCTRLSTA_CTRL_OFFSET, &data); if (ret_val) - goto out; + return ret_val; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_CTRL_OFFSET, data & ~(1 << 0)); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, &data); if (ret_val) - goto out; + return ret_val; data &= ~(0xF << 8); data |= (0xB << 8); ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, data); if (ret_val) - goto out; + return ret_val; /* Write PHY register values back to h/w defaults */ hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); data &= ~(0x7F << 5); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); data |= (1 << 13); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); data &= ~(0x3FF << 2); data |= (0x8 << 2); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10)); if (ret_val) - goto out; + return ret_val; } /* re-enable Rx path after enabling/disabling workaround */ - ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & - ~(1 << 14)); - -out: - return ret_val; + return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & + ~(1 << 14)); } /** @@ -1775,34 +2351,25 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); if (hw->mac.type != e1000_pch2lan) - goto out; + return E1000_SUCCESS; /* Set MDIO slow mode before any other MDIO access */ ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (ret_val) + return ret_val; ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_MSE_THRESHOLD); - if (ret_val) - goto release; + return ret_val; /* set MSE higher to enable link to stay up when noise is high */ - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x0034); - if (ret_val) - goto release; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_MSE_LINK_DOWN); + ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); if (ret_val) goto release; /* drop link after 5 times MSE threshold was reached */ - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x0005); + ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); release: hw->phy.ops.release(hw); -out: return ret_val; } @@ -1822,12 +2389,12 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) DEBUGFUNC("e1000_k1_workaround_lv"); if (hw->mac.type != e1000_pch2lan) - goto out; + return E1000_SUCCESS; /* Set K1 beacon duration based on 1Gbps speed or otherwise */ ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); if (ret_val) - goto out; + return ret_val; if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { @@ -1836,11 +2403,23 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); if (ret_val) - goto out; + return ret_val; if (status_reg & HV_M_STATUS_SPEED_1000) { + u16 pm_phy_reg; + mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; + /* LV 1G Packet drop issue wa */ + ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, + &pm_phy_reg); + if (ret_val) + return ret_val; + pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; + ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, + pm_phy_reg); + if (ret_val) + return ret_val; } else { mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; @@ -1849,7 +2428,6 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); } -out: return ret_val; } @@ -1867,7 +2445,7 @@ static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); - if (hw->mac.type != e1000_pch2lan) + if (hw->mac.type < e1000_pch2lan) return; extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); @@ -1878,7 +2456,6 @@ static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); - return; } /** @@ -1901,8 +2478,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) usec_delay(100); } while ((!data) && --loop); - /* - * If basic configuration is incomplete before the above loop + /* If basic configuration is incomplete before the above loop * count reaches 0, loading the configuration from NVM will * leave the PHY in a bad state possibly resulting in no link. */ @@ -1927,7 +2503,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_post_phy_reset_ich8lan"); if (hw->phy.ops.check_reset_block(hw)) - goto out; + return E1000_SUCCESS; /* Allow time for h/w to get to quiescent state after reset */ msec_delay(10); @@ -1937,12 +2513,12 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) case e1000_pchlan: ret_val = e1000_hv_phy_workarounds_ich8lan(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_pch2lan: ret_val = e1000_lv_phy_workarounds_ich8lan(hw); if (ret_val) - goto out; + return ret_val; break; default: break; @@ -1958,7 +2534,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) /* Configure the LCD with the extended configuration region in NVM */ ret_val = e1000_sw_lcd_config_ich8lan(hw); if (ret_val) - goto out; + return ret_val; /* Configure the LCD with the OEM bits in NVM */ ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); @@ -1974,18 +2550,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) /* Set EEE LPI Update Timer to 200usec */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_LPI_UPDATE_TIMER); - if (ret_val) - goto release; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x1387); -release: + return ret_val; + ret_val = e1000_write_emi_reg_locked(hw, + I82579_LPI_UPDATE_TIMER, + 0x1387); hw->phy.ops.release(hw); } -out: return ret_val; } @@ -2010,12 +2581,9 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) ret_val = e1000_phy_hw_reset_generic(hw); if (ret_val) - goto out; + return ret_val; - ret_val = e1000_post_phy_reset_ich8lan(hw); - -out: - return ret_val; + return e1000_post_phy_reset_ich8lan(hw); } /** @@ -2031,14 +2599,14 @@ out: **/ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 oem_reg; DEBUGFUNC("e1000_set_lplu_state_pchlan"); ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); if (ret_val) - goto out; + return ret_val; if (active) oem_reg |= HV_OEM_BITS_LPLU; @@ -2048,10 +2616,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) if (!hw->phy.ops.check_reset_block(hw)) oem_reg |= HV_OEM_BITS_RESTART_AN; - ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); - -out: - return ret_val; + return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); } /** @@ -2077,7 +2642,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); if (phy->type == e1000_phy_ife) - goto out; + return E1000_SUCCESS; phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); @@ -2086,10 +2651,9 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * Call gig speed drop workaround on LPLU before accessing + /* Call gig speed drop workaround on LPLU before accessing * any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -2099,21 +2663,22 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else { phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2123,32 +2688,31 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2180,10 +2744,9 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2193,27 +2756,27 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || @@ -2222,10 +2785,9 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * Call gig speed drop workaround on LPLU before accessing + /* Call gig speed drop workaround on LPLU before accessing * any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -2236,7 +2798,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, @@ -2244,7 +2806,6 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) data); } -out: return ret_val; } @@ -2263,7 +2824,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; u8 sig_byte = 0; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); @@ -2278,7 +2839,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) else *bank = 0; - goto out; + return E1000_SUCCESS; } DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); /* fall-thru */ @@ -2290,11 +2851,11 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, &sig_byte); if (ret_val) - goto out; + return ret_val; if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == E1000_ICH_NVM_SIG_VALUE) { *bank = 0; - goto out; + return E1000_SUCCESS; } /* Check bank 1 */ @@ -2302,19 +2863,16 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) bank1_offset, &sig_byte); if (ret_val) - goto out; + return ret_val; if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == E1000_ICH_NVM_SIG_VALUE) { *bank = 1; - goto out; + return E1000_SUCCESS; } DEBUGOUT("ERROR: No valid NVM bank present\n"); - ret_val = -E1000_ERR_NVM; - break; + return -E1000_ERR_NVM; } -out: - return ret_val; } /** @@ -2396,9 +2954,9 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); /* Check if the flash descriptor is valid */ - if (hsfsts.hsf_status.fldesvalid == 0) { + if (!hsfsts.hsf_status.fldesvalid) { DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); - goto out; + return -E1000_ERR_NVM; } /* Clear FCERR and DAEL in hw status by writing 1 */ @@ -2407,8 +2965,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); - /* - * Either we should have a hardware SPI cycle in progress + /* Either we should have a hardware SPI cycle in progress * bit to check against, in order to start a new cycle or * FDONE bit should be changed in the hardware so that it * is 1 after hardware reset, which can then be used as an @@ -2416,9 +2973,8 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) * completed. */ - if (hsfsts.hsf_status.flcinprog == 0) { - /* - * There is no cycle running at present, + if (!hsfsts.hsf_status.flcinprog) { + /* There is no cycle running at present, * so we can start a cycle. * Begin by setting Flash Cycle Done. */ @@ -2428,22 +2984,20 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) } else { s32 i; - /* - * Otherwise poll for sometime so the current + /* Otherwise poll for sometime so the current * cycle has a chance to end before giving up. */ for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcinprog == 0) { + if (!hsfsts.hsf_status.flcinprog) { ret_val = E1000_SUCCESS; break; } usec_delay(1); } if (ret_val == E1000_SUCCESS) { - /* - * Successful in waiting for previous cycle to timeout, + /* Successful in waiting for previous cycle to timeout, * now set the Flash Cycle Done. */ hsfsts.hsf_status.flcdone = 1; @@ -2454,7 +3008,6 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) } } -out: return ret_val; } @@ -2469,7 +3022,6 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) { union ich8_hws_flash_ctrl hsflctl; union ich8_hws_flash_status hsfsts; - s32 ret_val = -E1000_ERR_NVM; u32 i = 0; DEBUGFUNC("e1000_flash_cycle_ich8lan"); @@ -2482,15 +3034,15 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) /* wait till FDONE bit is set to 1 */ do { hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcdone == 1) + if (hsfsts.hsf_status.flcdone) break; usec_delay(1); } while (i++ < timeout); - if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) - ret_val = E1000_SUCCESS; + if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) + return E1000_SUCCESS; - return ret_val; + return -E1000_ERR_NVM; } /** @@ -2505,22 +3057,15 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data) { - s32 ret_val; - DEBUGFUNC("e1000_read_flash_word_ich8lan"); - if (!data) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (!data) + return -E1000_ERR_NVM; /* Must convert offset into bytes. */ offset <<= 1; - ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); - -out: - return ret_val; + return e1000_read_flash_data_ich8lan(hw, offset, 2, data); } /** @@ -2534,17 +3079,16 @@ out: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 *data) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 word = 0; ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); if (ret_val) - goto out; + return ret_val; *data = (u8)word; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2569,7 +3113,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, DEBUGFUNC("e1000_read_flash_data_ich8lan"); if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) - goto out; + return -E1000_ERR_NVM; flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + hw->nvm.flash_base_addr; @@ -2592,8 +3136,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ret_val = e1000_flash_cycle_ich8lan(hw, ICH_FLASH_READ_COMMAND_TIMEOUT); - /* - * Check if FCERR is set to 1, if set to 1, clear it + /* Check if FCERR is set to 1, if set to 1, clear it * and try the whole sequence a few more times, else * read in (shift in) the Flash Data0, the order is * least significant byte first msb to lsb @@ -2606,25 +3149,23 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, *data = (u16)(flash_data & 0x0000FFFF); break; } else { - /* - * If we've gotten here, then things are probably + /* If we've gotten here, then things are probably * completely hosed, but if the error condition is * detected, it won't hurt to give it another try... * ICH_FLASH_CYCLE_REPEAT_COUNT times. */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) { + if (hsfsts.hsf_status.flcerr) { /* Repeat for some time before giving up. */ continue; - } else if (hsfsts.hsf_status.flcdone == 0) { + } else if (!hsfsts.hsf_status.flcdone) { DEBUGOUT("Timeout error - flash cycle did not complete.\n"); break; } } } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); -out: return ret_val; } @@ -2642,7 +3183,6 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, { struct e1000_nvm_info *nvm = &hw->nvm; struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - s32 ret_val = E1000_SUCCESS; u16 i; DEBUGFUNC("e1000_write_nvm_ich8lan"); @@ -2650,8 +3190,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } nvm->ops.acquire(hw); @@ -2663,8 +3202,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, nvm->ops.release(hw); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2697,8 +3235,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) nvm->ops.acquire(hw); - /* - * We're writing to the opposite bank so if we're on bank 1, + /* We're writing to the opposite bank so if we're on bank 1, * write to bank 0 etc. We also need to erase the segment that * is going to be written */ @@ -2723,8 +3260,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) } for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - /* - * Determine whether to write the value stored + /* Determine whether to write the value stored * in the other NVM bank or a modified value stored * in the shadow RAM */ @@ -2738,8 +3274,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) break; } - /* - * If the word is 0x13, then make sure the signature bits + /* If the word is 0x13, then make sure the signature bits * (15:14) are 11b until the commit has completed. * This will allow us to write 10b which indicates the * signature is valid. We want to do this after the write @@ -2768,8 +3303,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) break; } - /* - * Don't bother writing the segment valid bits if sector + /* Don't bother writing the segment valid bits if sector * programming failed. */ if (ret_val) { @@ -2777,8 +3311,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) goto release; } - /* - * Finally validate the new segment by setting bit 15:14 + /* Finally validate the new segment by setting bit 15:14 * to 10b in word 0x13 , this can be done without an * erase as well since these bits are 11 to start with * and we need to change bit 14 to 0b @@ -2795,8 +3328,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) if (ret_val) goto release; - /* - * And invalidate the previously valid segment by setting + /* And invalidate the previously valid segment by setting * its signature word (0x13) high_byte to 0b. This can be * done without an erase because flash erase sets all bits * to 1's. We can write 1's to 0's without an erase @@ -2815,8 +3347,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) release: nvm->ops.release(hw); - /* - * Reload the EEPROM, or else modifications will not appear + /* Reload the EEPROM, or else modifications will not appear * until after the next adapter reset. */ if (!ret_val) { @@ -2841,35 +3372,44 @@ out: **/ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; + u16 word; + u16 valid_csum_mask; DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); - /* - * Read 0x19 and check bit 6. If this bit is 0, the checksum - * needs to be fixed. This bit is an indication that the NVM - * was prepared by OEM software and did not calculate the - * checksum...a likely scenario. + /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, + * the checksum needs to be fixed. This bit is an indication that + * the NVM was prepared by OEM software and did not calculate + * the checksum...a likely scenario. */ - ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); - if (ret_val) - goto out; - - if ((data & 0x40) == 0) { - data |= 0x40; - ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); - if (ret_val) - goto out; - ret_val = hw->nvm.ops.update(hw); - if (ret_val) - goto out; + switch (hw->mac.type) { + case e1000_pch_lpt: + word = NVM_COMPAT; + valid_csum_mask = NVM_COMPAT_VALID_CSUM; + break; + default: + word = NVM_FUTURE_INIT_WORD1; + valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; + break; } - ret_val = e1000_validate_nvm_checksum_generic(hw); + ret_val = hw->nvm.ops.read(hw, word, 1, &data); + if (ret_val) + return ret_val; -out: - return ret_val; + if (!(data & valid_csum_mask)) { + data |= valid_csum_mask; + ret_val = hw->nvm.ops.write(hw, word, 1, &data); + if (ret_val) + return ret_val; + ret_val = hw->nvm.ops.update(hw); + if (ret_val) + return ret_val; + } + + return e1000_validate_nvm_checksum_generic(hw); } /** @@ -2888,14 +3428,14 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, union ich8_hws_flash_ctrl hsflctl; u32 flash_linear_addr; u32 flash_data = 0; - s32 ret_val = -E1000_ERR_NVM; + s32 ret_val; u8 count = 0; DEBUGFUNC("e1000_write_ich8_data"); if (size < 1 || size > 2 || data > size * 0xff || offset > ICH_FLASH_LINEAR_ADDR_MASK) - goto out; + return -E1000_ERR_NVM; flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + hw->nvm.flash_base_addr; @@ -2922,8 +3462,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); - /* - * check if FCERR is set to 1 , if set to 1, clear it + /* check if FCERR is set to 1 , if set to 1, clear it * and try the whole sequence a few more times else done */ ret_val = e1000_flash_cycle_ich8lan(hw, @@ -2931,23 +3470,21 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, if (ret_val == E1000_SUCCESS) break; - /* - * If we're here, then things are most likely + /* If we're here, then things are most likely * completely hosed, but if the error condition * is detected, it won't hurt to give it another * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) + if (hsfsts.hsf_status.flcerr) /* Repeat for some time before giving up. */ continue; - if (hsfsts.hsf_status.flcdone == 0) { + if (!hsfsts.hsf_status.flcdone) { DEBUGOUT("Timeout error - flash cycle did not complete.\n"); break; } } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); -out: return ret_val; } @@ -2987,8 +3524,8 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); - if (ret_val == E1000_SUCCESS) - goto out; + if (!ret_val) + return ret_val; for (program_retries = 0; program_retries < 100; program_retries++) { DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); @@ -2997,13 +3534,10 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, if (ret_val == E1000_SUCCESS) break; } - if (program_retries == 100) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (program_retries == 100) + return -E1000_ERR_NVM; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3022,7 +3556,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) u32 flash_linear_addr; /* bank size is in 16bit words - adjust to bytes */ u32 flash_bank_size = nvm->flash_bank_size * 2; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; s32 count = 0; s32 j, iteration, sector_size; @@ -3030,8 +3564,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - /* - * Determine HW Sector size: Read BERASE bits of hw flash status + /* Determine HW Sector size: Read BERASE bits of hw flash status * register * 00: The Hw sector is 256 bytes, hence we need to erase 16 * consecutive sectors. The start index for the nth Hw sector @@ -3062,8 +3595,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) iteration = 1; break; default: - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } /* Start with the base address, then add the sector offset. */ @@ -3075,10 +3607,9 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) /* Steps */ ret_val = e1000_flash_cycle_init_ich8lan(hw); if (ret_val) - goto out; + return ret_val; - /* - * Write a value 11 (block Erase) in Flash + /* Write a value 11 (block Erase) in Flash * Cycle field in hw flash control */ hsflctl.regval = E1000_READ_FLASH_REG16(hw, @@ -3087,8 +3618,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - /* - * Write the last 24 bits of an index within the + /* Write the last 24 bits of an index within the * block into Flash Linear address field in Flash * Address. */ @@ -3101,23 +3631,21 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) if (ret_val == E1000_SUCCESS) break; - /* - * Check if FCERR is set to 1. If 1, + /* Check if FCERR is set to 1. If 1, * clear it and try the whole sequence * a few more times else Done */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) + if (hsfsts.hsf_status.flcerr) /* repeat for some time before giving up */ continue; - else if (hsfsts.hsf_status.flcdone == 0) - goto out; + else if (!hsfsts.hsf_status.flcdone) + return ret_val; } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3138,14 +3666,13 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) *data = ID_LED_DEFAULT_ICH8LAN; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3174,7 +3701,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) /* Get default ID LED modes */ ret_val = hw->nvm.ops.valid_led_default(hw, &data); if (ret_val) - goto out; + return ret_val; mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); mac->ledctl_mode1 = mac->ledctl_default; @@ -3219,8 +3746,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3239,8 +3765,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) ret_val = e1000_get_bus_info_pcie_generic(hw); - /* - * ICH devices are "PCI Express"-ish. They have + /* ICH devices are "PCI Express"-ish. They have * a configuration space, but do not contain * PCI Express Capability registers, so bus width * must be hardcoded. @@ -3261,14 +3786,13 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - u16 reg; - u32 ctrl, kab; + u16 kum_cfg; + u32 ctrl, reg; s32 ret_val; DEBUGFUNC("e1000_reset_hw_ich8lan"); - /* - * Prevent the PCI-E bus from sticking if there is no TLP connection + /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); @@ -3278,8 +3802,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - /* - * Disable the Transmit and Receive units. Then delay to allow + /* Disable the Transmit and Receive units. Then delay to allow * any pending transactions to complete before we hit the MAC * with the global reset. */ @@ -3299,11 +3822,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) if (hw->mac.type == e1000_pchlan) { /* Save the NVM K1 bit setting*/ - ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); + ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); if (ret_val) return ret_val; - if (reg & E1000_NVM_K1_ENABLE) + if (kum_cfg & E1000_NVM_K1_ENABLE) dev_spec->nvm_k1_enabled = TRUE; else dev_spec->nvm_k1_enabled = FALSE; @@ -3312,15 +3835,13 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); if (!hw->phy.ops.check_reset_block(hw)) { - /* - * Full-chip reset requires MAC and PHY reset at the same + /* Full-chip reset requires MAC and PHY reset at the same * time to make sure the interface between MAC and the * external PHY is reset. */ ctrl |= E1000_CTRL_PHY_RST; - /* - * Gate automatic PHY configuration by hardware on + /* Gate automatic PHY configuration by hardware on * non-managed 82579 */ if ((hw->mac.type == e1000_pch2lan) && @@ -3333,21 +3854,28 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) /* cannot issue a flush here because it hangs the hardware */ msec_delay(20); + /* Set Phy Config Counter to 50msec */ + if (hw->mac.type == e1000_pch2lan) { + reg = E1000_READ_REG(hw, E1000_FEXTNVM3); + reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); + } + if (!ret_val) E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); if (ctrl & E1000_CTRL_PHY_RST) { ret_val = hw->phy.ops.get_cfg_done(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_post_phy_reset_ich8lan(hw); if (ret_val) - goto out; + return ret_val; } - /* - * For PCH, this write will make sure that any noise + /* For PCH, this write will make sure that any noise * will be detected as a CRC error and be dropped rather than show up * as a bad packet to the DMA engine. */ @@ -3357,12 +3885,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); E1000_READ_REG(hw, E1000_ICR); - kab = E1000_READ_REG(hw, E1000_KABGTXD); - kab |= E1000_KABGTXD_BGSQLBIAS; - E1000_WRITE_REG(hw, E1000_KABGTXD, kab); + reg = E1000_READ_REG(hw, E1000_KABGTXD); + reg |= E1000_KABGTXD_BGSQLBIAS; + E1000_WRITE_REG(hw, E1000_KABGTXD, reg); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3390,9 +3917,9 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); + /* An error is not fatal and we should not stop init due to this */ if (ret_val) DEBUGOUT("Error initializing identification LED\n"); - /* This is not fatal and we should not stop init due to this */ /* Setup the receive address. */ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); @@ -3402,8 +3929,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) for (i = 0; i < mac->mta_reg_count; i++) E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); - /* - * The 82578 Rx buffer will stall if wakeup is enabled in host and + /* The 82578 Rx buffer will stall if wakeup is enabled in host and * the ME. Disable wakeup by clearing the host wakeup bit. * Reset the phy after disabling host wakeup to reset the Rx buffer. */ @@ -3433,8 +3959,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) E1000_TXDCTL_MAX_TX_DESC_PREFETCH; E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); - /* - * ICH8 has opposite polarity of no_snoop bits. + /* ICH8 has opposite polarity of no_snoop bits. * By default, we should use snoop behavior. */ if (mac->type == e1000_ich8lan) @@ -3447,8 +3972,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) ctrl_ext |= E1000_CTRL_EXT_RO_DIS; E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -3457,6 +3981,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) return ret_val; } + /** * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits * @hw: pointer to the HW structure @@ -3511,14 +4036,29 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_STATUS, reg); } - /* - * work-around descriptor data corruption issue during nfs v2 udp + /* work-around descriptor data corruption issue during nfs v2 udp * traffic, just disable the nfs filtering capability */ reg = E1000_READ_REG(hw, E1000_RFCTL); reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); + /* Disable IPv6 extension header parsing because some malformed + * IPv6 headers can hang the Rx. + */ + if (hw->mac.type == e1000_ich8lan) + reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); E1000_WRITE_REG(hw, E1000_RFCTL, reg); + /* Enable ECC on Lynxpoint */ + if (hw->mac.type == e1000_pch_lpt) { + reg = E1000_READ_REG(hw, E1000_PBECCSTS); + reg |= E1000_PBECCSTS_ECC_ENABLE; + E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); + + reg = E1000_READ_REG(hw, E1000_CTRL); + reg |= E1000_CTRL_MEHE; + E1000_WRITE_REG(hw, E1000_CTRL, reg); + } + return; } @@ -3534,23 +4074,21 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) **/ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_setup_link_ich8lan"); if (hw->phy.ops.check_reset_block(hw)) - goto out; + return E1000_SUCCESS; - /* - * ICH parts do not have a word in the NVM to determine + /* ICH parts do not have a word in the NVM to determine * the default flow control setting, so we explicitly * set it to full. */ if (hw->fc.requested_mode == e1000_fc_default) hw->fc.requested_mode = e1000_fc_full; - /* - * Save off the requested flow control mode for use later. Depending + /* Save off the requested flow control mode for use later. Depending * on the link partner's capabilities, we may or may not use this mode. */ hw->fc.current_mode = hw->fc.requested_mode; @@ -3561,11 +4099,12 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) /* Continue to configure the copper link. */ ret_val = hw->mac.ops.setup_physical_interface(hw); if (ret_val) - goto out; + return ret_val; E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); if ((hw->phy.type == e1000_phy_82578) || (hw->phy.type == e1000_phy_82579) || + (hw->phy.type == e1000_phy_i217) || (hw->phy.type == e1000_phy_82577)) { E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); @@ -3573,13 +4112,10 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) PHY_REG(BM_PORT_CTRL_PAGE, 27), hw->fc.pause_time); if (ret_val) - goto out; + return ret_val; } - ret_val = e1000_set_fc_watermarks_generic(hw); - -out: - return ret_val; + return e1000_set_fc_watermarks_generic(hw); } /** @@ -3603,50 +4139,49 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - /* - * Set the mac to wait the maximum time between each iteration + /* Set the mac to wait the maximum time between each iteration * and increase the max iterations when polling the phy; * this fixes erroneous timeouts at 10Mbps. */ ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, ®_data); if (ret_val) - goto out; + return ret_val; reg_data |= 0x3F; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, reg_data); if (ret_val) - goto out; + return ret_val; switch (hw->phy.type) { case e1000_phy_igp_3: ret_val = e1000_copper_link_setup_igp(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_bm: case e1000_phy_82578: ret_val = e1000_copper_link_setup_m88(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_82577: case e1000_phy_82579: ret_val = e1000_copper_link_setup_82577(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_ife: ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, ®_data); if (ret_val) - goto out; + return ret_val; reg_data &= ~IFE_PMC_AUTO_MDIX; @@ -3665,15 +4200,40 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data); if (ret_val) - goto out; + return ret_val; break; default: break; } - ret_val = e1000_setup_copper_link_generic(hw); -out: - return ret_val; + return e1000_setup_copper_link_generic(hw); +} + +/** + * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface + * @hw: pointer to the HW structure + * + * Calls the PHY specific link setup function and then calls the + * generic setup_copper_link to finish configuring the link for + * Lynxpoint PCH devices + **/ +static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + + DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + ret_val = e1000_copper_link_setup_82577(hw); + if (ret_val) + return ret_val; + + return e1000_setup_copper_link_generic(hw); } /** @@ -3695,7 +4255,7 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); if (ret_val) - goto out; + return ret_val; if ((hw->mac.type == e1000_ich8lan) && (hw->phy.type == e1000_phy_igp_3) && @@ -3703,7 +4263,6 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); } -out: return ret_val; } @@ -3726,41 +4285,36 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 phy_ctrl; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 i, data; bool link; DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); if (!dev_spec->kmrn_lock_loss_workaround_enabled) - goto out; + return E1000_SUCCESS; - /* - * Make sure link is up before proceeding. If not just return. + /* Make sure link is up before proceeding. If not just return. * Attempting this while link is negotiating fouled up link * stability */ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); - if (!link) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!link) + return E1000_SUCCESS; for (i = 0; i < 10; i++) { /* read once to clear */ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); if (ret_val) - goto out; + return ret_val; /* and again to get new status */ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); if (ret_val) - goto out; + return ret_val; /* check for PCS lock */ - if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) + return E1000_SUCCESS; /* Issue PHY reset */ hw->phy.ops.reset(hw); @@ -3772,17 +4326,13 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) E1000_PHY_CTRL_NOND0A_GBE_DISABLE); E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); - /* - * Call gig speed drop workaround on Gig disable before accessing + /* Call gig speed drop workaround on Gig disable before accessing * any PHY registers */ e1000_gig_downshift_workaround_ich8lan(hw); /* unable to acquire PCS lock */ - ret_val = -E1000_ERR_PHY; - -out: - return ret_val; + return -E1000_ERR_PHY; } /** @@ -3829,7 +4379,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); if (hw->phy.type != e1000_phy_igp_3) - goto out; + return; /* Try the workaround twice (if needed) */ do { @@ -3839,8 +4389,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) E1000_PHY_CTRL_NOND0A_GBE_DISABLE); E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); - /* - * Call gig speed drop workaround on Gig disable before + /* Call gig speed drop workaround on Gig disable before * accessing any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -3863,9 +4412,6 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); retry++; } while (retry); - -out: - return; } /** @@ -3880,31 +4426,28 @@ out: **/ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 reg_data; DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) - goto out; + return; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ®_data); if (ret_val) - goto out; + return; reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); if (ret_val) - goto out; + return; reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; - ret_val = e1000_write_kmrn_reg_generic(hw, - E1000_KMRNCTRLSTA_DIAG_OFFSET, - reg_data); -out: - return; + e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); } /** @@ -3917,9 +4460,13 @@ out: * the LPLU setting in the NVM or custom setting. For PCH and newer parts, * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also * needs to be written. + * Parts that support (and are linked to a partner which support) EEE in + * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power + * than 10Mbps w/o EEE. **/ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) { + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 phy_ctrl; s32 ret_val; @@ -3927,13 +4474,96 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; + + if (hw->phy.type == e1000_phy_i217) { + u16 phy_reg, device_id = hw->device_id; + + if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || + (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { + u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); + + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); + } + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + goto out; + + if (!dev_spec->eee_disable) { + u16 eee_advert; + + ret_val = + e1000_read_emi_reg_locked(hw, + I217_EEE_ADVERTISEMENT, + &eee_advert); + if (ret_val) + goto release; + + /* Disable LPLU if both link partners support 100BaseT + * EEE and 100Full is advertised on both ends of the + * link. + */ + if ((eee_advert & I82579_EEE_100_SUPPORTED) && + (dev_spec->eee_lp_ability & + I82579_EEE_100_SUPPORTED) && + (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) + phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | + E1000_PHY_CTRL_NOND0A_LPLU); + } + + /* For i217 Intel Rapid Start Technology support, + * when the system is going into Sx and no manageability engine + * is present, the driver must configure proxy to reset only on + * power good. LPI (Low Power Idle) state must also reset only + * on power good, as well as the MTA (Multicast table array). + * The SMBus release must also be disabled on LCD reset. + */ + if (!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID)) { + /* Enable proxy to reset only on power good. */ + hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, + &phy_reg); + phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; + hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, + phy_reg); + + /* Set bit enable LPI (EEE) to reset only on + * power good. + */ + hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); + phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; + hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); + + /* Disable the SMB release on LCD reset. */ + hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); + phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; + hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); + } + + /* Enable MTA to reset for Intel Rapid Start Technology + * Support + */ + hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); + phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; + hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); + +release: + hw->phy.ops.release(hw); + } +out: E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + if (hw->mac.type == e1000_ich8lan) e1000_gig_downshift_workaround_ich8lan(hw); if (hw->mac.type >= e1000_pchlan) { e1000_oem_bits_config_ich8lan(hw, FALSE); - e1000_phy_hw_reset_ich8lan(hw); + + /* Reset PHY to activate OEM bits on 82577/8 */ + if (hw->mac.type == e1000_pchlan) + e1000_phy_hw_reset_generic(hw); + ret_val = hw->phy.ops.acquire(hw); if (ret_val) return; @@ -3952,48 +4582,64 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) * on which PHY resets are not blocked, if the PHY registers cannot be * accessed properly by the s/w toggle the LANPHYPC value to power cycle * the PHY. + * On i217, setup Intel Rapid Start Technology. **/ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) { - u16 phy_id1, phy_id2; s32 ret_val; DEBUGFUNC("e1000_resume_workarounds_pchlan"); - if ((hw->mac.type != e1000_pch2lan) || - hw->phy.ops.check_reset_block(hw)) + if (hw->mac.type < e1000_pch2lan) return; - ret_val = hw->phy.ops.acquire(hw); + ret_val = e1000_init_phy_workarounds_pchlan(hw); if (ret_val) { - DEBUGOUT("Failed to acquire PHY semaphore in resume\n"); + DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); return; } - /* Test access to the PHY registers by reading the ID regs */ - ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1); - if (ret_val) - goto release; - ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2); - if (ret_val) - goto release; + /* For i217 Intel Rapid Start Technology support when the system + * is transitioning from Sx and no manageability engine is present + * configure SMBus to restore on reset, disable proxy, and enable + * the reset on MTA (Multicast table array). + */ + if (hw->phy.type == e1000_phy_i217) { + u16 phy_reg; - if (hw->phy.id == ((u32)(phy_id1 << 16) | - (u32)(phy_id2 & PHY_REVISION_MASK))) - goto release; + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) { + DEBUGOUT("Failed to setup iRST\n"); + return; + } - e1000_toggle_lanphypc_value_ich8lan(hw); - - hw->phy.ops.release(hw); - msec_delay(50); - hw->phy.ops.reset(hw); - msec_delay(50); - return; + if (!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID)) { + /* Restore clear on SMB if no manageability engine + * is present + */ + ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, + &phy_reg); + if (ret_val) + goto release; + phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; + hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); + /* Disable Proxy */ + hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); + } + /* Enable reset on MTA */ + ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, + &phy_reg); + if (ret_val) + goto release; + phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; + hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); release: - hw->phy.ops.release(hw); - - return; + if (ret_val) + DEBUGOUT1("Error %d in resume workarounds\n", ret_val); + hw->phy.ops.release(hw); + } } /** @@ -4091,8 +4737,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw) DEBUGFUNC("e1000_led_on_pchlan"); - /* - * If no link, then turn LED on by setting the invert bit + /* If no link, then turn LED on by setting the invert bit * for each LED that's mode is "link_up" in ledctl_mode2. */ if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { @@ -4124,8 +4769,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw) DEBUGFUNC("e1000_led_off_pchlan"); - /* - * If no link, then turn LED off by clearing the invert bit + /* If no link, then turn LED off by clearing the invert bit * for each LED that's mode is "link_up" in ledctl_mode1. */ if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { @@ -4172,8 +4816,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) } else { ret_val = e1000_get_auto_rd_done_generic(hw); if (ret_val) { - /* - * When auto config read does not complete, do not + /* When auto config read does not complete, do not * return with an error. This can happen in situations * where there is no eeprom and prevents getting link. */ @@ -4191,7 +4834,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) /* If EEPROM is not marked present, init the IGP 3 PHY manually */ if (hw->mac.type <= e1000_ich9lan) { - if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && (hw->phy.type == e1000_phy_igp_3)) { e1000_phy_init_script_igp3(hw); } @@ -4256,6 +4899,7 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) /* Clear PHY statistics registers */ if ((hw->phy.type == e1000_phy_82578) || (hw->phy.type == e1000_phy_82579) || + (hw->phy.type == e1000_phy_i217) || (hw->phy.type == e1000_phy_82577)) { ret_val = hw->phy.ops.acquire(hw); if (ret_val) diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.h index 2eccb30046..bf92898170 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_ich8lan.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -59,12 +59,8 @@ #define ICH_FLASH_SEG_SIZE_4K 4096 #define ICH_FLASH_SEG_SIZE_8K 8192 #define ICH_FLASH_SEG_SIZE_64K 65536 -#define ICH_FLASH_SECTOR_SIZE 4096 - -#define ICH_FLASH_REG_MAPSIZE 0x00A0 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ -#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ /* FW established a valid mode */ #define E1000_ICH_FWSM_FW_VALID 0x00008000 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ @@ -72,23 +68,12 @@ #define E1000_ICH_MNG_IAMT_MODE 0x2 -#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */ -#define E1000_FWSM_MEMC 0x00000010 /* ME Messaging capable */ +#define E1000_FWSM_WLOCK_MAC_MASK 0x0380 +#define E1000_FWSM_WLOCK_MAC_SHIFT 7 /* Shared Receive Address Registers */ -#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) -#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) -#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */ -#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */ - -#define E1000_H2ME 0x05B50 /* Host to ME */ -#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */ -#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */ -#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */ -#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */ -#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */ -#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */ -#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */ +#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) +#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ @@ -105,27 +90,30 @@ #define E1000_FEXTNVM_SW_CONFIG 1 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 + #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 +#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 + #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL #define E1000_ICH_RAR_ENTRIES 7 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ +#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ #define PHY_PAGE_SHIFT 5 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ ((reg) & MAX_PHY_REG_ADDRESS)) #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ -#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ -#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 -#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 /* PHY Wakeup Registers and defines */ #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) @@ -138,14 +126,6 @@ #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) -#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64)) -#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2))) -#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2))) - -#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4))) -#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4))) -#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4))) -#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4))) #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ @@ -177,28 +157,28 @@ #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ -/* - * For ICH, the name used for NVM word 17h is LED1 Config. - * For PCH, the word was re-named to OEM Config. - */ -#define E1000_NVM_LED1_CONFIG 0x17 /* NVM LED1/LPLU Config Word */ -#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */ -#define E1000_NVM_OEM_CONFIG E1000_NVM_LED1_CONFIG -#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA - #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ +/* SMBus Control Phy Register */ +#define CV_SMB_CTRL PHY_REG(769, 23) +#define CV_SMB_CTRL_FORCE_SMBUS 0x0001 + /* SMBus Address Phy Register */ #define HV_SMB_ADDR PHY_REG(768, 26) #define HV_SMB_ADDR_MASK 0x007F #define HV_SMB_ADDR_PEC_EN 0x0200 #define HV_SMB_ADDR_VALID 0x0080 +#define HV_SMB_ADDR_FREQ_MASK 0x1100 +#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 +#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 /* Strapping Option Register - RO */ #define E1000_STRAP 0x0000C #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 +#define E1000_STRAP_SMT_FREQ_MASK 0x00003000 +#define E1000_STRAP_SMT_FREQ_SHIFT 12 /* OEM Bits Phy Register */ #define HV_OEM_BITS PHY_REG(768, 25) @@ -206,8 +186,6 @@ #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ -#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy addr bit from LCD Config word */ - /* KMRN Mode Control */ #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) #define HV_KMRN_MDIO_SLOW 0x0400 @@ -219,47 +197,73 @@ /* PHY Power Management Control */ #define HV_PM_CTRL PHY_REG(770, 17) +#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ /* PHY Low Power Idle Control */ #define I82579_LPI_CTRL PHY_REG(772, 20) +#define I82579_LPI_CTRL_100_ENABLE 0x2000 +#define I82579_LPI_CTRL_1000_ENABLE 0x4000 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 -/* EMI Registers */ +/* Extended Management Interface (EMI) Registers */ #define I82579_EMI_ADDR 0x10 #define I82579_EMI_DATA 0x11 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ -#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ +#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ +#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ +#define I82579_RX_CONFIG 0x3412 /* Receive configuration */ +#define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */ +#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ +#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ +#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ +#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ +#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */ +#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ +#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ +#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ +#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ -/* - * Additional interrupts need to be handled for ICH family: - * DSW = The FW changed the status of the DISSW bit in FWSM - * PHYINT = The LAN connected device generates an interrupt - * EPRST = Manageability reset event - */ -#define IMS_ICH_ENABLE_MASK (\ - E1000_IMS_DSW | \ - E1000_IMS_PHYINT | \ - E1000_IMS_EPRST) +#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ +#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ -/* Additional interrupt register bit definitions */ -#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ -#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ -#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ - -/* Security Processing bit Indication */ -#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 -#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 -#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 -#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 -#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 +/* Intel Rapid Start Technology Support */ +#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) +#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 +#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) +#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 +#define I217_CGFREG PHY_REG(772, 29) +#define I217_CGFREG_ENABLE_MTA_RESET 0x0002 +#define I217_MEMPWR PHY_REG(772, 26) +#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 /* Receive Address Initial CRC Calculation */ #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) +/* Latency Tolerance Reporting */ +#define E1000_LTRV 0x000F8 +#define E1000_LTRV_VALUE_MASK 0x000003FF +#define E1000_LTRV_SCALE_MAX 5 +#define E1000_LTRV_SCALE_FACTOR 5 +#define E1000_LTRV_SCALE_SHIFT 10 +#define E1000_LTRV_SCALE_MASK 0x00001C00 +#define E1000_LTRV_REQ_SHIFT 15 +#define E1000_LTRV_NOSNOOP_SHIFT 16 +#define E1000_LTRV_SEND (1 << 30) + +/* Proprietary Latency Tolerance Reporting PCI Capability */ +#define E1000_PCI_LTR_CAP_LPT 0xA8 + +/* OBFF Control & Threshold Defines */ +#define E1000_SVCR_OFF_EN 0x00000001 +#define E1000_SVCR_OFF_MASKINT 0x00001000 +#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 +#define E1000_SVCR_OFF_TIMER_SHIFT 16 +#define E1000_SVT_OFF_HWM_MASK 0x0000001F + void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state); void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); @@ -269,4 +273,5 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); -#endif +s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); +#endif /* _E1000_ICH8LAN_H_ */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.c index 95d6873b13..9e6b30c49f 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -70,12 +70,9 @@ void e1000_init_mac_ops_generic(struct e1000_hw *hw) mac->ops.setup_link = e1000_null_ops_generic; mac->ops.get_link_up_info = e1000_null_link_info; mac->ops.check_for_link = e1000_null_ops_generic; - mac->ops.wait_autoneg = e1000_wait_autoneg_generic; + mac->ops.set_obff_timer = e1000_null_set_obff_timer; /* Management */ mac->ops.check_mng_mode = e1000_null_mng_mode; - mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; - mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; - mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; /* VLAN, MC, etc. */ mac->ops.update_mc_addr_list = e1000_null_update_mc; mac->ops.clear_vfta = e1000_null_mac_generic; @@ -118,8 +115,7 @@ s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) * e1000_null_mng_mode - No-op function, return FALSE * @hw: pointer to the HW structure **/ -bool e1000_null_mng_mode(struct e1000_hw *hw) -{ +bool e1000_null_mng_mode(struct e1000_hw *hw) { DEBUGFUNC("e1000_null_mng_mode"); return FALSE; } @@ -154,6 +150,16 @@ void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) return; } +/** + * e1000_null_set_obff_timer - No-op function, return 0 + * @hw: pointer to the HW structure + **/ +s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a) +{ + DEBUGFUNC("e1000_null_set_obff_timer"); + return E1000_SUCCESS; +} + /** * e1000_get_bus_info_pci_generic - Get PCI(x) bus information * @hw: pointer to the HW structure @@ -268,8 +274,7 @@ static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) struct e1000_bus_info *bus = &hw->bus; u32 reg; - /* - * The status register reports the correct function number + /* The status register reports the correct function number * for the device regardless of function swap state. */ reg = E1000_READ_REG(hw, E1000_STATUS); @@ -389,7 +394,7 @@ void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) { u32 i; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 offset, nvm_alt_mac_addr_offset, nvm_data; u8 alt_mac_addr[ETH_ADDR_LEN]; @@ -403,8 +408,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) return E1000_SUCCESS; - /* - * Alternate MAC address is handled by the option ROM for 82580 + /* Alternate MAC address is handled by the option ROM for 82580 * and newer. SW support not required. */ if (hw->mac.type >= e1000_82580) @@ -447,8 +451,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) return E1000_SUCCESS; } - /* - * We have a valid alternate MAC address, and we want to treat it the + /* We have a valid alternate MAC address, and we want to treat it the * same as the normal permanent MAC address stored by the HW into the * RAR. Do this by mapping this address into RAR0. */ @@ -472,8 +475,7 @@ static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) DEBUGFUNC("e1000_rar_set_generic"); - /* - * HW expects these in little endian so we reverse the byte order + /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | @@ -485,8 +487,7 @@ static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) if (rar_low || rar_high) rar_high |= E1000_RAH_AV; - /* - * Some bridges will combine consecutive 32-bit writes into + /* Some bridges will combine consecutive 32-bit writes into * a single burst write, which will malfunction on some parts. * The flushes avoid this. */ @@ -514,15 +515,13 @@ u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) /* Register count multiplied by bits per register */ hash_mask = (hw->mac.mta_reg_count * 32) - 1; - /* - * For a mc_filter_type of 0, bit_shift is the number of left-shifts + /* For a mc_filter_type of 0, bit_shift is the number of left-shifts * where 0xFF would still fall within the hash mask. */ while (hash_mask >> bit_shift != 0xFF) bit_shift++; - /* - * The portion of the address that is used for the hash table + /* The portion of the address that is used for the hash table * is determined by the mc_filter_type setting. * The algorithm is such that there is a total of 8 bits of shifting. * The bit_shift for a mc_filter_type of 0 represents the number of @@ -707,8 +706,7 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_check_for_copper_link"); - /* - * We only want to go out to the PHY registers to see if Auto-Neg + /* We only want to go out to the PHY registers to see if Auto-Neg * has completed and/or if our link status has changed. The * get_link_status flag is set upon receiving a Link Status * Change or Rx Sequence Error interrupt. @@ -716,8 +714,7 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) if (!mac->get_link_status) return E1000_SUCCESS; - /* - * First we want to see if the MII Status Register reports + /* First we want to see if the MII Status Register reports * link. If so, then we want to get the current speed/duplex * of the PHY. */ @@ -730,28 +727,24 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) mac->get_link_status = FALSE; - /* - * Check if there was DownShift, must be checked + /* Check if there was DownShift, must be checked * immediately after link-up */ e1000_check_downshift_generic(hw); - /* - * If we are forcing speed/duplex, then we simply return since + /* If we are forcing speed/duplex, then we simply return since * we have already determined whether we have link or not. */ if (!mac->autoneg) return -E1000_ERR_CONFIG; - /* - * Auto-Neg is enabled. Auto Speed Detection takes care + /* Auto-Neg is enabled. Auto Speed Detection takes care * of MAC speed/duplex configuration. So we only need to * configure Collision Distance in the MAC. */ mac->ops.config_collision_dist(hw); - /* - * Configure Flow Control now that Auto-Neg has completed. + /* Configure Flow Control now that Auto-Neg has completed. * First, we need to restore the desired flow control * settings because we may have had to re-autoneg with a * different link partner. @@ -784,8 +777,7 @@ s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) status = E1000_READ_REG(hw, E1000_STATUS); rxcw = E1000_READ_REG(hw, E1000_RXCW); - /* - * If we don't have link (auto-negotiation failed or link partner + /* If we don't have link (auto-negotiation failed or link partner * cannot auto-negotiate), the cable is plugged in (we have signal), * and our link partner is not trying to auto-negotiate with us (we * are receiving idles or data), we need to force link up. We also @@ -816,8 +808,7 @@ s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) return ret_val; } } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { - /* - * If we are forcing link and we are receiving /C/ ordered + /* If we are forcing link and we are receiving /C/ ordered * sets, re-enable auto-negotiation in the TXCW register * and disable forced link in the Device Control register * in an attempt to auto-negotiate with our link partner. @@ -853,8 +844,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) status = E1000_READ_REG(hw, E1000_STATUS); rxcw = E1000_READ_REG(hw, E1000_RXCW); - /* - * If we don't have link (auto-negotiation failed or link partner + /* If we don't have link (auto-negotiation failed or link partner * cannot auto-negotiate), and our link partner is not trying to * auto-negotiate with us (we are receiving idles or data), * we need to force link up. We also need to give auto-negotiation @@ -883,8 +873,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) return ret_val; } } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { - /* - * If we are forcing link and we are receiving /C/ ordered + /* If we are forcing link and we are receiving /C/ ordered * sets, re-enable auto-negotiation in the TXCW register * and disable forced link in the Device Control register * in an attempt to auto-negotiate with our link partner. @@ -895,8 +884,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) mac->serdes_has_link = TRUE; } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { - /* - * If we force link for non-auto-negotiation switch, check + /* If we force link for non-auto-negotiation switch, check * link status based on MAC synchronization for internal * serdes media type. */ @@ -955,8 +943,7 @@ s32 e1000_set_default_fc_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_set_default_fc_generic"); - /* - * Read and store word 0x0F of the EEPROM. This word contains bits + /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or * disabling auto-negotiation, and the direction of the @@ -998,15 +985,13 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_setup_link_generic"); - /* - * In the case of the phy reset being blocked, we already have a link. + /* In the case of the phy reset being blocked, we already have a link. * We do not need to set it up again. */ if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) return E1000_SUCCESS; - /* - * If requested flow control is set to default, set flow control + /* If requested flow control is set to default, set flow control * based on the EEPROM flow control settings. */ if (hw->fc.requested_mode == e1000_fc_default) { @@ -1015,8 +1000,7 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) return ret_val; } - /* - * Save off the requested flow control mode for use later. Depending + /* Save off the requested flow control mode for use later. Depending * on the link partner's capabilities, we may or may not use this mode. */ hw->fc.current_mode = hw->fc.requested_mode; @@ -1029,8 +1013,7 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Initialize the flow control address, type, and PAUSE timer + /* Initialize the flow control address, type, and PAUSE timer * registers to their default values. This is done even if flow * control is disabled, because it does not hurt anything to * initialize these registers. @@ -1059,8 +1042,7 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_commit_fc_settings_generic"); - /* - * Check for a software override of the flow control settings, and + /* Check for a software override of the flow control settings, and * setup the device accordingly. If auto-negotiation is enabled, then * software will have to set the "PAUSE" bits to the correct value in * the Transmit Config Word Register (TXCW) and re-start auto- @@ -1082,8 +1064,7 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); break; case e1000_fc_rx_pause: - /* - * Rx Flow control is enabled and Tx Flow control is disabled + /* Rx Flow control is enabled and Tx Flow control is disabled * by a software over-ride. Since there really isn't a way to * advertise that we are capable of Rx Pause ONLY, we will * advertise that we support both symmetric and asymmetric Rx @@ -1093,15 +1074,13 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case e1000_fc_tx_pause: - /* - * Tx Flow control is enabled, and Rx Flow control is disabled, + /* Tx Flow control is enabled, and Rx Flow control is disabled, * by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); break; case e1000_fc_full: - /* - * Flow control (both Rx and Tx) is enabled by a software + /* Flow control (both Rx and Tx) is enabled by a software * over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); @@ -1133,8 +1112,7 @@ s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); - /* - * If we have a signal (the cable is plugged in, or assumed TRUE for + /* If we have a signal (the cable is plugged in, or assumed TRUE for * serdes media) then poll for a "Link-Up" indication in the Device * Status Register. Time-out if a link isn't seen in 500 milliseconds * seconds (Auto-negotiation should complete in less than 500 @@ -1149,8 +1127,7 @@ s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) if (i == FIBER_LINK_UP_LIMIT) { DEBUGOUT("Never got a valid link from auto-neg!!!\n"); mac->autoneg_failed = TRUE; - /* - * AutoNeg failed to achieve a link, so we'll call + /* AutoNeg failed to achieve a link, so we'll call * mac->check_for_link. This routine will force the * link up if we detect a signal. This will allow us to * communicate with non-autonegotiating link partners. @@ -1194,8 +1171,7 @@ s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Since auto-negotiation is enabled, take the link out of reset (the + /* Since auto-negotiation is enabled, take the link out of reset (the * link will be in reset, because we previously reset the chip). This * will restart auto-negotiation. If auto-negotiation is successful * then the link-up status bit will be set and the flow control enable @@ -1207,8 +1183,7 @@ s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); msec_delay(1); - /* - * For these adapters, the SW definable pin 1 is set when the optics + /* For these adapters, the SW definable pin 1 is set when the optics * detect a signal. If we have a signal, then poll for a "Link-Up" * indication. */ @@ -1258,16 +1233,14 @@ s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_set_fc_watermarks_generic"); - /* - * Set the flow control receive threshold registers. Normally, + /* Set the flow control receive threshold registers. Normally, * these registers will be set to a default threshold that may be * adjusted later by the driver's runtime code. However, if the * ability to transmit pause frames is not enabled, then these * registers will be set to 0. */ if (hw->fc.current_mode & e1000_fc_tx_pause) { - /* - * We need to set up the Receive Threshold high and low water + /* We need to set up the Receive Threshold high and low water * marks as well as (optionally) enabling the transmission of * XON frames. */ @@ -1301,8 +1274,7 @@ s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); - /* - * Because we didn't get link via the internal auto-negotiation + /* Because we didn't get link via the internal auto-negotiation * mechanism (we either forced link or we got link via PHY * auto-neg), we have to manually enable/disable transmit an * receive flow control. @@ -1360,13 +1332,13 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; s32 ret_val = E1000_SUCCESS; + u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; u16 speed, duplex; DEBUGFUNC("e1000_config_fc_after_link_up_generic"); - /* - * Check for the case where we have fiber media and auto-neg failed + /* Check for the case where we have fiber media and auto-neg failed * so we had to force link. In this case, we need to force the * configuration of the MAC to match the "fc" parameter. */ @@ -1384,15 +1356,13 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) return ret_val; } - /* - * Check for the case where we have copper media and auto-neg is + /* Check for the case where we have copper media and auto-neg is * enabled. In this case, we need to check and see if Auto-Neg * has completed, and if so, how the PHY and link partner has * flow control configured. */ if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { - /* - * Read the MII Status Register and check to see if AutoNeg + /* Read the MII Status Register and check to see if AutoNeg * has completed. We read this twice because this reg has * some "sticky" (latched) bits. */ @@ -1408,8 +1378,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) return ret_val; } - /* - * The AutoNeg process has completed, so we now need to + /* The AutoNeg process has completed, so we now need to * read both the Auto Negotiation Advertisement * Register (Address 4) and the Auto_Negotiation Base * Page Ability Register (Address 5) to determine how @@ -1424,8 +1393,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Two bits in the Auto Negotiation Advertisement Register + /* Two bits in the Auto Negotiation Advertisement Register * (Address 4) and two bits in the Auto Negotiation Base * Page Ability Register (Address 5) determine flow control * for both the PHY and the link partner. The following @@ -1460,8 +1428,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) */ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { - /* - * Now we need to check if the user selected Rx ONLY + /* Now we need to check if the user selected Rx ONLY * of pause frames. In this case, we had to advertise * FULL flow control because we could not advertise Rx * ONLY. Hence, we must now check to see if we need to @@ -1475,8 +1442,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } } - /* - * For receiving PAUSE frames ONLY. + /* For receiving PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result @@ -1490,8 +1456,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) hw->fc.current_mode = e1000_fc_tx_pause; DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); } - /* - * For transmitting PAUSE frames ONLY. + /* For transmitting PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result @@ -1505,16 +1470,14 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) hw->fc.current_mode = e1000_fc_rx_pause; DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } else { - /* - * Per the IEEE spec, at this point flow control + /* Per the IEEE spec, at this point flow control * should be disabled. */ hw->fc.current_mode = e1000_fc_none; DEBUGOUT("Flow Control = NONE.\n"); } - /* - * Now we need to do one last check... If we auto- + /* Now we need to do one last check... If we auto- * negotiated to HALF DUPLEX, flow control should not be * enabled per IEEE 802.3 spec. */ @@ -1527,8 +1490,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) if (duplex == HALF_DUPLEX) hw->fc.current_mode = e1000_fc_none; - /* - * Now we call a subroutine to actually force the MAC + /* Now we call a subroutine to actually force the MAC * controller to use the correct flow control settings. */ ret_val = e1000_force_mac_fc_generic(hw); @@ -1538,6 +1500,130 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) } } + /* Check for the case where we have SerDes media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if ((hw->phy.media_type == e1000_media_type_internal_serdes) && + mac->autoneg) { + /* Read the PCS_LSTS and check to see if AutoNeg + * has completed. + */ + pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); + + if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { + DEBUGOUT("PCS Auto Neg has not completed.\n"); + return ret_val; + } + + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement + * Register (PCS_ANADV) and the Auto_Negotiation Base + * Page Ability Register (PCS_LPAB) to determine how + * flow control was negotiated. + */ + pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); + pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); + + /* Two bits in the Auto Negotiation Advertisement Register + * (PCS_ANADV) and two bits in the Auto Negotiation Base + * Page Ability Register (PCS_LPAB) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + * Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { + /* Now we need to check if the user selected Rx ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise Rx + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->fc.requested_mode == e1000_fc_full) { + hw->fc.current_mode = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\n"); + } else { + hw->fc.current_mode = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + */ + else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_adv_reg & E1000_TXCW_ASM_DIR) && + (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { + hw->fc.current_mode = e1000_fc_tx_pause; + DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + */ + else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_adv_reg & E1000_TXCW_ASM_DIR) && + !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { + hw->fc.current_mode = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); + } else { + /* Per the IEEE spec, at this point flow control + * should be disabled. + */ + hw->fc.current_mode = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\n"); + } + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); + pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; + E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); + + ret_val = e1000_force_mac_fc_generic(hw); + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + return E1000_SUCCESS; } @@ -1854,16 +1940,28 @@ s32 e1000_blink_led_generic(struct e1000_hw *hw) ledctl_blink = E1000_LEDCTL_LED0_BLINK | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); } else { - /* - * set the blink bit for each LED that's "on" (0x0E) - * in ledctl_mode2 + /* Set the blink bit for each LED that's "on" (0x0E) + * (or "off" if inverted) in ledctl_mode2. The blink + * logic in hardware only works when mode is set to "on" + * so it must be changed accordingly when the mode is + * "off" and inverted. */ ledctl_blink = hw->mac.ledctl_mode2; - for (i = 0; i < 4; i++) - if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == - E1000_LEDCTL_MODE_LED_ON) - ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << - (i * 8)); + for (i = 0; i < 32; i += 8) { + u32 mode = (hw->mac.ledctl_mode2 >> i) & + E1000_LEDCTL_LED0_MODE_MASK; + u32 led_default = hw->mac.ledctl_default >> i; + + if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && + (mode == E1000_LEDCTL_MODE_LED_ON)) || + ((led_default & E1000_LEDCTL_LED0_IVRT) && + (mode == E1000_LEDCTL_MODE_LED_OFF))) { + ledctl_blink &= + ~(E1000_LEDCTL_LED0_MODE_MASK << i); + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | + E1000_LEDCTL_MODE_LED_ON) << i; + } + } } E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); @@ -2082,6 +2180,20 @@ static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) return E1000_SUCCESS; } +/** + * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings + * @hw: pointer to the HW structure + * + * Validate the MDI/MDIx setting, allowing for auto-crossover during forced + * operation. + **/ +s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); + + return E1000_SUCCESS; +} + /** * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register * @hw: pointer to the HW structure diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.h index c18a7ec129..3e2ccdedb1 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_mac.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,10 +35,6 @@ #ifndef _E1000_MAC_H_ #define _E1000_MAC_H_ -/* - * Functions that should not be called directly from drivers but can be used - * by other files in this 'shared code' - */ void e1000_init_mac_ops_generic(struct e1000_hw *hw); void e1000_null_mac_generic(struct e1000_hw *hw); s32 e1000_null_ops_generic(struct e1000_hw *hw); @@ -47,6 +43,7 @@ bool e1000_null_mng_mode(struct e1000_hw *hw); void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a); void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b); void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a); +s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a); s32 e1000_blink_led_generic(struct e1000_hw *hw); s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw); s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); @@ -77,6 +74,7 @@ s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw); s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw); s32 e1000_setup_led_generic(struct e1000_hw *hw); s32 e1000_setup_link_generic(struct e1000_hw *hw); +s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw); s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, u32 offset, u8 data); diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_manage.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_manage.c index f11b18d20e..c58d32d16b 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_manage.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_manage.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -145,11 +145,10 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) return hw->mac.tx_pkt_filtering; } - /* - * If we can't read from the host interface for whatever + /* If we can't read from the host interface for whatever * reason, disable filtering. */ - ret_val = hw->mac.ops.mng_enable_host_if(hw); + ret_val = e1000_mng_enable_host_if_generic(hw); if (ret_val != E1000_SUCCESS) { hw->mac.tx_pkt_filtering = FALSE; return hw->mac.tx_pkt_filtering; @@ -165,8 +164,7 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) hdr->checksum = 0; csum = e1000_calculate_checksum((u8 *)hdr, E1000_MNG_DHCP_COOKIE_LENGTH); - /* - * If either the checksums or signature don't match, then + /* If either the checksums or signature don't match, then * the cookie area isn't considered valid, in which case we * take the safe route of assuming Tx filtering is enabled. */ @@ -259,8 +257,7 @@ s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant command block into the + /* The device driver writes the relevant command block into the * ram area. */ for (i = 0; i < length; i++) { @@ -312,18 +309,18 @@ s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer, hdr.checksum = 0; /* Enable the host interface */ - ret_val = hw->mac.ops.mng_enable_host_if(hw); + ret_val = e1000_mng_enable_host_if_generic(hw); if (ret_val) return ret_val; /* Populate the host interface with the contents of "buffer". */ - ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length, - sizeof(hdr), &(hdr.checksum)); + ret_val = e1000_mng_host_if_write_generic(hw, buffer, length, + sizeof(hdr), &(hdr.checksum)); if (ret_val) return ret_val; /* Write the manageability command header */ - ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr); + ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr); if (ret_val) return ret_val; @@ -424,8 +421,7 @@ s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length) /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant command block + /* The device driver writes the relevant command block * into the ram area. */ for (i = 0; i < length; i++) @@ -537,8 +533,7 @@ s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length) /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant FW code block + /* The device driver writes the relevant FW code block * into the ram area in DWORDs via 1kB ram addressing window. */ for (i = 0; i < length; i++) { diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.c index d8df089efe..a39b847815 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -227,7 +227,6 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) { u32 attempts = 100000; u32 i, reg = 0; - s32 ret_val = -E1000_ERR_NVM; DEBUGFUNC("e1000_poll_eerd_eewr_done"); @@ -237,15 +236,13 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) else reg = E1000_READ_REG(hw, E1000_EEWR); - if (reg & E1000_NVM_RW_REG_DONE) { - ret_val = E1000_SUCCESS; - break; - } + if (reg & E1000_NVM_RW_REG_DONE) + return E1000_SUCCESS; usec_delay(5); } - return ret_val; + return -E1000_ERR_NVM; } /** @@ -260,7 +257,6 @@ s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) { u32 eecd = E1000_READ_REG(hw, E1000_EECD); s32 timeout = E1000_NVM_GRANT_ATTEMPTS; - s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_acquire_nvm_generic"); @@ -279,10 +275,10 @@ s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) eecd &= ~E1000_EECD_REQ; E1000_WRITE_REG(hw, E1000_EECD, eecd); DEBUGOUT("Could not acquire NVM grant\n"); - ret_val = -E1000_ERR_NVM; + return -E1000_ERR_NVM; } - return ret_val; + return E1000_SUCCESS; } /** @@ -381,7 +377,6 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; u32 eecd = E1000_READ_REG(hw, E1000_EECD); - s32 ret_val = E1000_SUCCESS; u8 spi_stat_reg; DEBUGFUNC("e1000_ready_nvm_eeprom"); @@ -402,8 +397,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); usec_delay(1); - /* - * Read "Status Register" repeatedly until the LSB is cleared. + /* Read "Status Register" repeatedly until the LSB is cleared. * The EEPROM will signal that the command has been completed * by clearing bit 0 of the internal status register. If it's * not cleared within 'timeout', then error out. @@ -422,13 +416,11 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) if (!timeout) { DEBUGOUT("SPI NVM Status error\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -450,20 +442,18 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) DEBUGFUNC("e1000_read_nvm_spi"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -478,8 +468,7 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); - /* - * Read the data. SPI NVMs increment the address with each byte + /* Read the data. SPI NVMs increment the address with each byte * read and will roll over if reading beyond the end. This allows * us to read the whole NVM from any offset */ @@ -491,7 +480,6 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) release: nvm->ops.release(hw); -out: return ret_val; } @@ -514,20 +502,18 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, DEBUGFUNC("e1000_read_nvm_microwire"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -539,8 +525,7 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, e1000_shift_out_eec_bits(hw, (u16)(offset + i), nvm->address_bits); - /* - * Read the data. For microwire, each word requires the + /* Read the data. For microwire, each word requires the * overhead of setup and tear-down. */ data[i] = e1000_shift_in_eec_bits(hw, 16); @@ -550,7 +535,6 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, release: nvm->ops.release(hw); -out: return ret_val; } @@ -571,15 +555,13 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) DEBUGFUNC("e1000_read_nvm_eerd"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * too many words for the offset, and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } for (i = 0; i < words; i++) { @@ -595,7 +577,6 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) E1000_NVM_RW_REG_DATA); } -out: return ret_val; } @@ -614,32 +595,32 @@ out: s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { struct e1000_nvm_info *nvm = &hw->nvm; - s32 ret_val; + s32 ret_val = -E1000_ERR_NVM; u16 widx = 0; DEBUGFUNC("e1000_write_nvm_spi"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } - ret_val = nvm->ops.acquire(hw); - if (ret_val) - goto out; - while (widx < words) { u8 write_opcode = NVM_WRITE_OPCODE_SPI; - ret_val = e1000_ready_nvm_eeprom(hw); + ret_val = nvm->ops.acquire(hw); if (ret_val) - goto release; + return ret_val; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) { + nvm->ops.release(hw); + return ret_val; + } e1000_standby_nvm(hw); @@ -649,8 +630,7 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_standby_nvm(hw); - /* - * Some SPI eeproms use the 8th address bit embedded in the + /* Some SPI eeproms use the 8th address bit embedded in the * opcode */ if ((nvm->address_bits == 8) && (offset >= 128)) @@ -673,13 +653,10 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) break; } } + msec_delay(10); + nvm->ops.release(hw); } - msec_delay(10); -release: - nvm->ops.release(hw); - -out: return ret_val; } @@ -706,20 +683,18 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, DEBUGFUNC("e1000_write_nvm_microwire"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -769,7 +744,6 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, release: nvm->ops.release(hw); -out: return ret_val; } @@ -795,32 +769,30 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, if (pba_num == NULL) { DEBUGOUT("PBA string buffer was null\n"); - ret_val = E1000_ERR_INVALID_ARGUMENT; - goto out; + return -E1000_ERR_INVALID_ARGUMENT; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } - /* - * if nvm_data is not ptr guard the PBA must be in legacy format which + /* if nvm_data is not ptr guard the PBA must be in legacy format which * means pba_ptr is actually our second data word for the PBA number * and we can decode it into an ascii string */ if (nvm_data != NVM_PBA_PTR_GUARD) { DEBUGOUT("NVM PBA number is not stored as string\n"); - /* we will need 11 characters to store the PBA */ - if (pba_num_size < 11) { + /* make sure callers buffer is big enough to store the PBA */ + if (pba_num_size < E1000_PBANUM_LENGTH) { DEBUGOUT("PBA string buffer too small\n"); return E1000_ERR_NO_SPACE; } @@ -848,25 +820,23 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, pba_num[offset] += 'A' - 0xA; } - goto out; + return E1000_SUCCESS; } ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (length == 0xFFFF || length == 0) { DEBUGOUT("NVM PBA number section invalid length\n"); - ret_val = E1000_ERR_NVM_PBA_SECTION; - goto out; + return -E1000_ERR_NVM_PBA_SECTION; } /* check if pba_num buffer is big enough */ if (pba_num_size < (((u32)length * 2) - 1)) { DEBUGOUT("PBA string buffer too small\n"); - ret_val = E1000_ERR_NO_SPACE; - goto out; + return -E1000_ERR_NO_SPACE; } /* trim pba length from start of string */ @@ -877,15 +847,14 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } pba_num[offset * 2] = (u8)(nvm_data >> 8); pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); } pba_num[offset * 2] = '\0'; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -907,48 +876,233 @@ s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) if (pba_num_size == NULL) { DEBUGOUT("PBA buffer size was null\n"); - ret_val = E1000_ERR_INVALID_ARGUMENT; - goto out; + return -E1000_ERR_INVALID_ARGUMENT; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } /* if data is not ptr guard the PBA must be in legacy format */ if (nvm_data != NVM_PBA_PTR_GUARD) { - *pba_num_size = 11; - goto out; + *pba_num_size = E1000_PBANUM_LENGTH; + return E1000_SUCCESS; } ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (length == 0xFFFF || length == 0) { DEBUGOUT("NVM PBA number section invalid length\n"); - ret_val = E1000_ERR_NVM_PBA_SECTION; - goto out; + return -E1000_ERR_NVM_PBA_SECTION; } - /* - * Convert from length in u16 values to u8 chars, add 1 for NULL, + /* Convert from length in u16 values to u8 chars, add 1 for NULL, * and subtract 2 because length field is included in length. */ *pba_num_size = ((u32)length * 2) - 1; -out: - return ret_val; + return E1000_SUCCESS; +} + + +/** + * e1000_read_pba_raw + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @max_pba_block_size: PBA block size limit + * @pba: pointer to output PBA structure + * + * Reads PBA from EEPROM image when eeprom_buf is not NULL. + * Reads PBA from physical EEPROM device when eeprom_buf is NULL. + * + **/ +s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 max_pba_block_size, + struct e1000_pba *pba) +{ + s32 ret_val; + u16 pba_block_size; + + if (pba == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, + &pba->word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; + pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba->word[0] == NVM_PBA_PTR_GUARD) { + if (pba->pba_block == NULL) + return -E1000_ERR_PARAM; + + ret_val = e1000_get_pba_block_size(hw, eeprom_buf, + eeprom_buf_size, + &pba_block_size); + if (ret_val) + return ret_val; + + if (pba_block_size > max_pba_block_size) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, pba->word[1], + pba_block_size, + pba->pba_block); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > (u32)(pba->word[1] + + pba->pba_block[0])) { + memcpy(pba->pba_block, + &eeprom_buf[pba->word[1]], + pba_block_size * sizeof(u16)); + } else { + return -E1000_ERR_PARAM; + } + } + } + + return E1000_SUCCESS; +} + +/** + * e1000_write_pba_raw + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @pba: pointer to PBA structure + * + * Writes PBA to EEPROM image when eeprom_buf is not NULL. + * Writes PBA to physical EEPROM device when eeprom_buf is NULL. + * + **/ +s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, struct e1000_pba *pba) +{ + s32 ret_val; + + if (pba == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, + &pba->word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; + eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba->word[0] == NVM_PBA_PTR_GUARD) { + if (pba->pba_block == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_write_nvm(hw, pba->word[1], + pba->pba_block[0], + pba->pba_block); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > (u32)(pba->word[1] + + pba->pba_block[0])) { + memcpy(&eeprom_buf[pba->word[1]], + pba->pba_block, + pba->pba_block[0] * sizeof(u16)); + } else { + return -E1000_ERR_PARAM; + } + } + } + + return E1000_SUCCESS; +} + +/** + * e1000_get_pba_block_size + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @pba_data_size: pointer to output variable + * + * Returns the size of the PBA block in words. Function operates on EEPROM + * image if the eeprom_buf pointer is not NULL otherwise it accesses physical + * EEPROM device. + * + **/ +s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 *pba_block_size) +{ + s32 ret_val; + u16 pba_word[2]; + u16 length; + + DEBUGFUNC("e1000_get_pba_block_size"); + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; + pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba_word[0] == NVM_PBA_PTR_GUARD) { + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, + &length); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > pba_word[1]) + length = eeprom_buf[pba_word[1] + 0]; + else + return -E1000_ERR_PARAM; + } + + if (length == 0xFFFF || length == 0) + return -E1000_ERR_NVM_PBA_SECTION; + } else { + /* PBA number in legacy format, there is no PBA Block. */ + length = 0; + } + + if (pba_block_size != NULL) + *pba_block_size = length; + + return E1000_SUCCESS; } /** @@ -989,7 +1143,7 @@ s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) **/ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 checksum = 0; u16 i, nvm_data; @@ -999,19 +1153,17 @@ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } checksum += nvm_data; } if (checksum != (u16) NVM_SUM) { DEBUGOUT("NVM Checksum Invalid\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1034,7 +1186,7 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error while updating checksum.\n"); - goto out; + return ret_val; } checksum += nvm_data; } @@ -1043,7 +1195,6 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) if (ret_val) DEBUGOUT("NVM Write Error while updating checksum.\n"); -out: return ret_val; } @@ -1067,3 +1218,4 @@ static void e1000_reload_nvm_generic(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } + diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.h index ed23eb3e37..34077b2498 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_nvm.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,6 +35,14 @@ #ifndef _E1000_NVM_H_ #define _E1000_NVM_H_ +#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW) +struct e1000_pba { + u16 word[2]; + u16 *pba_block; +}; +#endif + + void e1000_init_nvm_ops_generic(struct e1000_hw *hw); s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c); void e1000_null_nvm_generic(struct e1000_hw *hw); @@ -47,6 +55,13 @@ s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size); s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size); +s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 max_pba_block_size, + struct e1000_pba *pba); +s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, struct e1000_pba *pba); +s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 *pba_block_size); s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_osdep.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_osdep.h index e6d131a52e..dd19613e0b 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_osdep.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -66,7 +66,8 @@ #define MSGOUT(S, A, B) printf(S "\n", A, B) #define DEBUGFUNC(F) DEBUGOUT(F); #define DEBUGOUT(S) do {} while (0) -#define DEBUGOUT1(S,A) do {} while (0) +/* This define is needed or shared code will not build */ +#define DEBUGOUT1(S,A) if (0) printf(S,A); #define DEBUGOUT2(S,A,B) do {} while (0) #define DEBUGOUT3(S,A,B,C) do {} while (0) #define DEBUGOUT7(S,A,B,C,D,E,F,G) do {} while (0) diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.c index fd253ba92f..241c1d5d30 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ #include "e1000_api.h" -static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); +static s32 e1000_wait_autoneg(struct e1000_hw *hw); static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data, bool read, bool page_set); static u32 e1000_get_phy_addr_for_hv_page(u32 page); @@ -173,8 +173,10 @@ s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, * @data: data value to write * **/ -s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, - u8 dev_addr, u8 data) +s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, + u8 byte_offset, + u8 dev_addr, + u8 data) { DEBUGFUNC("e1000_write_i2c_byte_null"); return E1000_SUCCESS; @@ -285,8 +287,7 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) return -E1000_ERR_PARAM; } - /* - * Set up Op-code, Phy Address, and register offset in the MDI + /* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -296,8 +297,7 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) E1000_WRITE_REG(hw, E1000_MDIC, mdic); - /* - * Poll the ready bit to see if the MDI read completed + /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out */ @@ -315,10 +315,15 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } + if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { + DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", + offset, + (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); + return -E1000_ERR_PHY; + } *data = (u16) mdic; - /* - * Allow some time after each MDIC transaction to avoid + /* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction. */ if (hw->mac.type == e1000_pch2lan) @@ -347,8 +352,7 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) return -E1000_ERR_PARAM; } - /* - * Set up Op-code, Phy Address, and register offset in the MDI + /* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -359,8 +363,7 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) E1000_WRITE_REG(hw, E1000_MDIC, mdic); - /* - * Poll the ready bit to see if the MDI read completed + /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out */ @@ -378,9 +381,14 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } + if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { + DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", + offset, + (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); + return -E1000_ERR_PHY; + } - /* - * Allow some time after each MDIC transaction to avoid + /* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction. */ if (hw->mac.type == e1000_pch2lan) @@ -405,8 +413,7 @@ s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) DEBUGFUNC("e1000_read_phy_reg_i2c"); - /* - * Set up Op-code, Phy Address, and register address in the I2CCMD + /* Set up Op-code, Phy Address, and register address in the I2CCMD * register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -464,8 +471,7 @@ s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) /* Swap the data bytes for the I2C interface */ phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); - /* - * Set up Op-code, Phy Address, and register address in the I2CCMD + /* Set up Op-code, Phy Address, and register address in the I2CCMD * register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -521,8 +527,7 @@ s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) return -E1000_ERR_PHY; } - /* - * Set up Op-code, EEPROM Address,in the I2CCMD + /* Set up Op-code, EEPROM Address,in the I2CCMD * register. The MAC will take care of interfacing with the * EEPROM to retrieve the desired data. */ @@ -576,14 +581,12 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) DEBUGOUT("I2CCMD command address exceeds upper limit\n"); return -E1000_ERR_PHY; } - /* - * The programming interface is 16 bits wide + /* The programming interface is 16 bits wide * so we need to read the whole word first * then update appropriate byte lane and write * the updated word back. */ - /* - * Set up Op-code, EEPROM Address,in the I2CCMD + /* Set up Op-code, EEPROM Address,in the I2CCMD * register. The MAC will take care of interfacing * with an EEPROM to write the data given. */ @@ -593,8 +596,7 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { usec_delay(50); - /* - * Poll the ready bit to see if lastly + /* Poll the ready bit to see if lastly * launched I2C operation completed */ i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); @@ -602,8 +604,7 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) /* Check if this is READ or WRITE phase */ if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == E1000_I2CCMD_OPCODE_READ) { - /* - * Write the selected byte + /* Write the selected byte * lane and update whole word */ data_local = i2ccmd & 0xFF00; @@ -1053,12 +1054,16 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) } } - /* Enable CRS on Tx. This must be set for half-duplex operation. */ + /* Enable CRS on Tx. This must be set for half-duplex operation. + * Not required on some PHYs. + */ ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); if (ret_val) return ret_val; - phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; + if ((hw->phy.type != e1000_phy_82579) && + (hw->phy.type != e1000_phy_i217)) + phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; /* Enable downshift */ phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; @@ -1072,8 +1077,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) if (ret_val) return ret_val; phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; - /* - * Options: + /* Options: * 0 - Auto (default) * 1 - MDI mode * 2 - MDI-X mode @@ -1121,8 +1125,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) if (phy->type != e1000_phy_bm) phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; - /* - * Options: + /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode @@ -1147,8 +1150,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) break; } - /* - * Options: + /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled @@ -1185,8 +1187,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) if ((phy->type == e1000_phy_m88) && (phy->revision < E1000_REVISION_4) && (phy->id != BME1000_E_PHY_ID_R2)) { - /* - * Force TX_CLK in the Extended PHY Specific Control Register + /* Force TX_CLK in the Extended PHY Specific Control Register * to 25MHz clock. */ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, @@ -1278,8 +1279,7 @@ s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Options: + /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode @@ -1307,8 +1307,7 @@ s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) break; } - /* - * Options: + /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled @@ -1359,14 +1358,12 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) return ret_val; } - /* - * Wait 100ms for MAC to configure PHY from NVM settings, to avoid + /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid * timeout issues when LFS is enabled. */ msec_delay(100); - /* - * The NVM settings will configure LPLU in D3 for + /* The NVM settings will configure LPLU in D3 for * non-IGP1 PHYs. */ if (phy->type == e1000_phy_igp) { @@ -1411,8 +1408,7 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) /* set auto-master slave resolution settings */ if (hw->mac.autoneg) { - /* - * when autonegotiation advertisement is only 1000Mbps then we + /* when autonegotiation advertisement is only 1000Mbps then we * should disable SmartSpeed and enable Auto MasterSlave * resolution as hardware default. */ @@ -1481,16 +1477,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) return ret_val; } - /* - * Need to parse both autoneg_advertised and fc and set up + /* Need to parse both autoneg_advertised and fc and set up * the appropriate PHY registers. First we will parse for * autoneg_advertised software override. Since we can advertise * a plethora of combinations, we need to check each bit * individually. */ - /* - * First we clear all the 10/100 mb speed bits in the Auto-Neg + /* First we clear all the 10/100 mb speed bits in the Auto-Neg * Advertisement Register (Address 4) and the 1000 mb speed bits in * the 1000Base-T Control Register (Address 9). */ @@ -1536,8 +1530,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; } - /* - * Check for a software override of the flow control settings, and + /* Check for a software override of the flow control settings, and * setup the PHY advertisement registers accordingly. If * auto-negotiation is enabled, then software will have to set the * "PAUSE" bits to the correct value in the Auto-Negotiation @@ -1556,15 +1549,13 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) */ switch (hw->fc.current_mode) { case e1000_fc_none: - /* - * Flow control (Rx & Tx) is completely disabled by a + /* Flow control (Rx & Tx) is completely disabled by a * software over-ride. */ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case e1000_fc_rx_pause: - /* - * Rx Flow control is enabled, and Tx Flow control is + /* Rx Flow control is enabled, and Tx Flow control is * disabled, by a software over-ride. * * Since there really isn't a way to advertise that we are @@ -1576,16 +1567,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case e1000_fc_tx_pause: - /* - * Tx Flow control is enabled, and Rx Flow control is + /* Tx Flow control is enabled, and Rx Flow control is * disabled, by a software over-ride. */ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; break; case e1000_fc_full: - /* - * Flow control (both Rx and Tx) is enabled by a software + /* Flow control (both Rx and Tx) is enabled by a software * over-ride. */ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); @@ -1625,14 +1614,12 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) DEBUGFUNC("e1000_copper_link_autoneg"); - /* - * Perform some bounds checking on the autoneg advertisement + /* Perform some bounds checking on the autoneg advertisement * parameter. */ phy->autoneg_advertised &= phy->autoneg_mask; - /* - * If autoneg_advertised is zero, we assume it was not defaulted + /* If autoneg_advertised is zero, we assume it was not defaulted * by the calling code so we set to advertise full capability. */ if (!phy->autoneg_advertised) @@ -1646,8 +1633,7 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) } DEBUGOUT("Restarting Auto-Neg\n"); - /* - * Restart auto-negotiation by setting the Auto Neg Enable bit and + /* Restart auto-negotiation by setting the Auto Neg Enable bit and * the Auto Neg Restart bit in the PHY control register. */ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); @@ -1659,12 +1645,11 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Does the user want to wait for Auto-Neg to complete here, or + /* Does the user want to wait for Auto-Neg to complete here, or * check at a later time (for example, callback routine). */ if (phy->autoneg_wait_to_complete) { - ret_val = hw->mac.ops.wait_autoneg(hw); + ret_val = e1000_wait_autoneg(hw); if (ret_val) { DEBUGOUT("Error while waiting for autoneg to complete\n"); return ret_val; @@ -1693,16 +1678,14 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_setup_copper_link_generic"); if (hw->mac.autoneg) { - /* - * Setup autoneg and flow control advertisement and perform + /* Setup autoneg and flow control advertisement and perform * autonegotiation. */ ret_val = e1000_copper_link_autoneg(hw); if (ret_val) return ret_val; } else { - /* - * PHY will be set to 10H, 10F, 100H or 100F + /* PHY will be set to 10H, 10F, 100H or 100F * depending on user settings. */ DEBUGOUT("Forcing Speed and Duplex\n"); @@ -1713,8 +1696,7 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) } } - /* - * Check link status. Wait up to 100 microseconds for link to become + /* Check link status. Wait up to 100 microseconds for link to become * valid. */ ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, @@ -1760,8 +1742,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Clear Auto-Crossover to force MDI manually. IGP requires MDI + /* Clear Auto-Crossover to force MDI manually. IGP requires MDI * forced whenever speed and duplex are forced. */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); @@ -1817,18 +1798,22 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); - /* - * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI - * forced whenever speed and duplex are forced. - */ - ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; + /* I210 and I211 devices support Auto-Crossover in forced operation. */ + if (phy->type != e1000_phy_i210) { + /* Clear Auto-Crossover to force MDI manually. M88E1000 + * requires MDI forced whenever speed and duplex are forced. + */ + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, + &phy_data); + if (ret_val) + return ret_val; - phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; - ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, + phy_data); + if (ret_val) + return ret_val; + } DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); @@ -1874,8 +1859,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (!reset_dsp) { DEBUGOUT("Link taking longer than expected.\n"); } else { - /* - * We didn't get link. + /* We didn't get link. * Reset the DSP and cross our fingers. */ ret_val = phy->ops.write_reg(hw, @@ -1909,8 +1893,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Resetting the phy means we need to re-force TX_CLK in the + /* Resetting the phy means we need to re-force TX_CLK in the * Extended PHY Specific Control Register to 25MHz clock from * the reset value of 2.5MHz. */ @@ -1919,8 +1902,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * In addition, we must re-enable CRS on Tx for both half and full + /* In addition, we must re-enable CRS on Tx for both half and full * duplex. */ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); @@ -2045,11 +2027,10 @@ void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { ctrl |= E1000_CTRL_SPD_100; *phy_ctrl |= MII_CR_SPEED_100; - *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); + *phy_ctrl &= ~MII_CR_SPEED_1000; DEBUGOUT("Forcing 100mb\n"); } else { ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); - *phy_ctrl |= MII_CR_SPEED_10; *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); DEBUGOUT("Forcing 10mb\n"); } @@ -2094,8 +2075,7 @@ s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) data); if (ret_val) return ret_val; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2238,8 +2218,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw) DEBUGFUNC("e1000_check_polarity_igp"); - /* - * Polarity is determined based on the speed of + /* Polarity is determined based on the speed of * our connection. */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); @@ -2251,8 +2230,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw) offset = IGP01E1000_PHY_PCS_INIT_REG; mask = IGP01E1000_PHY_POLARITY_MASK; } else { - /* - * This really only applies to 10Mbps since + /* This really only applies to 10Mbps since * there is no polarity for 100Mbps (always 0). */ offset = IGP01E1000_PHY_PORT_STATUS; @@ -2283,8 +2261,7 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw) DEBUGFUNC("e1000_check_polarity_ife"); - /* - * Polarity is determined based on the reversal feature being enabled. + /* Polarity is determined based on the reversal feature being enabled. */ if (phy->polarity_correction) { offset = IFE_PHY_EXTENDED_STATUS_CONTROL; @@ -2305,18 +2282,18 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw) } /** - * e1000_wait_autoneg_generic - Wait for auto-neg completion + * e1000_wait_autoneg - Wait for auto-neg completion * @hw: pointer to the HW structure * * Waits for auto-negotiation to complete or for the auto-negotiation time * limit to expire, which ever happens first. **/ -s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) +static s32 e1000_wait_autoneg(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u16 i, phy_status; - DEBUGFUNC("e1000_wait_autoneg_generic"); + DEBUGFUNC("e1000_wait_autoneg"); if (!hw->phy.ops.read_reg) return E1000_SUCCESS; @@ -2334,8 +2311,7 @@ s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) msec_delay(100); } - /* - * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation + /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation * has completed. */ return ret_val; @@ -2362,15 +2338,13 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, return E1000_SUCCESS; for (i = 0; i < iterations; i++) { - /* - * Some PHYs require the PHY_STATUS register to be read + /* Some PHYs require the PHY_STATUS register to be read * twice due to the link bit being sticky. No harm doing * it across the board. */ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); if (ret_val) - /* - * If the first read fails, another entity may have + /* If the first read fails, another entity may have * ownership of the resources, wait and try again to * see if they have relinquished the resources yet. */ @@ -2436,7 +2410,8 @@ s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; - u16 phy_data, phy_data2, index, default_page, is_cm; + u16 phy_data, phy_data2, is_cm; + u16 index, default_page; DEBUGFUNC("e1000_get_cable_length_m88_gen2"); @@ -2574,8 +2549,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Getting bits 15:9, which represent the combination of + /* Getting bits 15:9, which represent the combination of * coarse and fine gain values. The result is a number * that can be put into the lookup table to obtain the * approximate cable length. @@ -2961,15 +2935,13 @@ s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) hw->phy.ops.write_reg(hw, 0x1796, 0x0008); /* Change cg_icount + enable integbp for channels BCD */ hw->phy.ops.write_reg(hw, 0x1798, 0xD008); - /* - * Change cg_icount + enable integbp + change prop_factor_master + /* Change cg_icount + enable integbp + change prop_factor_master * to 8 for channel A */ hw->phy.ops.write_reg(hw, 0x1898, 0xD918); /* Disable AHT in Slave mode on channel A */ hw->phy.ops.write_reg(hw, 0x187A, 0x0800); - /* - * Enable LPLU and disable AN to 1000 in non-D0a states, + /* Enable LPLU and disable AN to 1000 in non-D0a states, * Enable SPD+B2B */ hw->phy.ops.write_reg(hw, 0x0019, 0x008D); @@ -3030,6 +3002,9 @@ enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) case I82579_E_PHY_ID: phy_type = e1000_phy_82579; break; + case I217_E_PHY_ID: + phy_type = e1000_phy_i217; + break; case I82580_I_PHY_ID: phy_type = e1000_phy_82580; break; @@ -3067,8 +3042,7 @@ s32 e1000_determine_phy_address(struct e1000_hw *hw) e1000_get_phy_id(hw); phy_type = e1000_get_phy_type_from_id(hw->phy.id); - /* - * If phy_type is valid, break - we found our + /* If phy_type is valid, break - we found our * PHY address */ if (phy_type != e1000_phy_unknown) @@ -3130,8 +3104,7 @@ s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) if (offset > MAX_PHY_MULTI_PAGE_REG) { u32 page_shift, page_select; - /* - * Page select is register 31 for phy address 1 and 22 for + /* Page select is register 31 for phy address 1 and 22 for * phy address 2 and 3. Page select is shifted only for * phy address 1. */ @@ -3191,8 +3164,7 @@ s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) if (offset > MAX_PHY_MULTI_PAGE_REG) { u32 page_shift, page_select; - /* - * Page select is register 31 for phy address 1 and 22 for + /* Page select is register 31 for phy address 1 and 22 for * phy address 2 and 3. Page select is shifted only for * phy address 1. */ @@ -3249,7 +3221,6 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) hw->phy.addr = 1; if (offset > MAX_PHY_MULTI_PAGE_REG) { - /* Page is shifted left, PHY expects (page x 32) */ ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, page); @@ -3346,8 +3317,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) return ret_val; } - /* - * Enable both PHY wakeup mode and Wakeup register page writes. + /* Enable both PHY wakeup mode and Wakeup register page writes. * Prevent a power state change by disabling ME and Host PHY wakeup. */ temp = *phy_reg; @@ -3361,8 +3331,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) return ret_val; } - /* - * Select Host Wakeup Registers page - caller now able to write + /* Select Host Wakeup Registers page - caller now able to write * registers on the Wakeup registers page */ return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); @@ -3381,7 +3350,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) **/ s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); @@ -3434,6 +3403,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, { s32 ret_val; u16 reg = BM_PHY_REG_NUM(offset); + u16 page = BM_PHY_REG_PAGE(offset); u16 phy_reg = 0; DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); @@ -3687,8 +3657,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, if (page == HV_INTC_FC_PAGE_START) page = 0; - /* - * Workaround MDIO accesses being disabled after entering IEEE + /* Workaround MDIO accesses being disabled after entering IEEE * Power Down (when bit 11 of the PHY Control register is set) */ if ((hw->phy.type == e1000_phy_82578) && @@ -3801,8 +3770,8 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, u16 *data, bool read) { s32 ret_val; - u32 addr_reg = 0; - u32 data_reg = 0; + u32 addr_reg; + u32 data_reg; DEBUGFUNC("e1000_access_phy_debug_regs_hv"); @@ -3875,8 +3844,8 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) /* flush the packets in the fifo buffer */ ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, - HV_MUX_DATA_CTRL_GEN_TO_MAC | - HV_MUX_DATA_CTRL_FORCE_SPEED); + (HV_MUX_DATA_CTRL_GEN_TO_MAC | + HV_MUX_DATA_CTRL_FORCE_SPEED)); if (ret_val) return ret_val; @@ -4044,7 +4013,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw) I82577_DSTATUS_CABLE_LENGTH_SHIFT; if (length == E1000_CABLE_LENGTH_UNDEFINED) - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; phy->cable_length = length; @@ -4113,3 +4082,4 @@ release: hw->phy.ops.release(hw); return ret_val; } + diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.h index edcbcabe44..9911df772d 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_phy.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -78,13 +78,11 @@ s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); -s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); -s32 e1000_phy_reset_dsp(struct e1000_hw *hw); s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success); s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); @@ -127,7 +125,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ -#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ @@ -147,7 +144,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); /* BM/HV Specific Registers */ #define BM_PORT_CTRL_PAGE 769 -#define BM_PCIE_PAGE 770 #define BM_WUC_PAGE 800 #define BM_WUC_ADDRESS_OPCODE 0x11 #define BM_WUC_DATA_OPCODE 0x12 @@ -188,7 +184,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define I82577_PHY_STATUS2_MDIX 0x0800 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 -#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 /* I82577 PHY Control 2 */ #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 @@ -204,14 +199,13 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ +#define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ /* BM PHY Copper Specific Control 1 */ #define BM_CS_CTRL1 16 -#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */ /* BM PHY Copper Specific Status */ #define BM_CS_STATUS 17 -#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */ #define BM_CS_STATUS_LINK_UP 0x0400 #define BM_CS_STATUS_RESOLVED 0x0800 #define BM_CS_STATUS_SPEED_MASK 0xC000 @@ -257,9 +251,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define IGP02E1000_AGC_LENGTH_MASK 0x7F #define IGP02E1000_AGC_RANGE 15 -#define IGP03E1000_PHY_MISC_CTRL 0x1B -#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ - #define E1000_CABLE_LENGTH_UNDEFINED 0xFF #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 @@ -272,7 +263,7 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 -#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 +#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 @@ -286,7 +277,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); /* IFE PHY Special Control */ #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 #define IFE_PSC_FORCE_POLARITY 0x0020 -#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* IFE PHY Special Control and LED Control */ #define IFE_PSCL_PROBE_MODE 0x0020 diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_regs.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_regs.h index 8c4e4afd13..516d377af4 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_regs.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/e1000_regs.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -55,9 +55,11 @@ #define E1000_SCTL 0x00024 /* SerDes Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ -#define E1000_FEXT 0x0002C /* Future Extended - RW */ -#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ +#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ +#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ +#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ +#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ #define E1000_FCT 0x00030 /* Flow Control Type - RW */ #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ @@ -70,6 +72,7 @@ #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ #define E1000_SVCR 0x000F0 #define E1000_SVT 0x000F4 +#define E1000_LPIC 0x000FC /* Low Power IDLE control */ #define E1000_RCTL 0x00100 /* Rx Control - RW */ #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ @@ -97,6 +100,7 @@ #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ #define E1000_PBS 0x01008 /* Packet Buffer Size */ +#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ @@ -129,7 +133,11 @@ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ -#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) +#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ +#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ +#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ +#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ +#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ /* Split and Replication Rx Control - RW */ @@ -200,8 +208,7 @@ /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n)) -/* - * Convenience macros +/* Convenience macros * * Note: "_n" is the queue number of the register to be written to. * @@ -413,8 +420,7 @@ #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ -/* - * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit +/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit * key - RW. */ #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) @@ -454,7 +460,6 @@ #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ -#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */ #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ @@ -489,7 +494,6 @@ #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ -#define E1000_MDPHYA 0x0003C /* PHY address - RW */ #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ /* Management Decision Filters */ #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) @@ -522,15 +526,6 @@ #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ -/* MSI-X Table entry addr low reg - RW */ -#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) -/* MSI-X Table entry addr upper reg - RW */ -#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) -/* MSI-X Table entry message reg - RW */ -#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) -/* MSI-X Table entry vector ctrl reg - RW */ -#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) -#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ @@ -580,8 +575,12 @@ #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ +#define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */ +#define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */ #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ +#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ +#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ @@ -671,8 +670,6 @@ #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ -#define E1000_LTRMINV 0x5BB0 /* LTR Minimum Value */ -#define E1000_LTRMAXV 0x5BB4 /* LTR Maximum Value */ #define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */ diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c index b58abd330f..ae10d953d8 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,10 +32,11 @@ ******************************************************************************/ /*$FreeBSD$*/ -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" #include "opt_inet.h" #include "opt_inet6.h" + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" #endif #include diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.h index fc83147089..392d603e41 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_em.h @@ -431,6 +431,7 @@ struct adapter { struct em_int_delay_info tx_abs_int_delay; struct em_int_delay_info rx_int_delay; struct em_int_delay_info rx_abs_int_delay; + struct em_int_delay_info tx_itr; /* Misc stats maintained by the driver */ unsigned long dropped_pkts; diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c index 26d0903586..6887bcf355 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -33,16 +33,17 @@ /*$FreeBSD$*/ -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" #include "opt_inet.h" #include "opt_inet6.h" + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" #include "opt_altq.h" #endif #include #include -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX #include #endif #include @@ -100,7 +101,7 @@ int igb_display_debug_stats = 0; /********************************************************************* * Driver version: *********************************************************************/ -char igb_driver_version[] = "version - 2.3.4"; +char igb_driver_version[] = "version - 2.3.10"; /********************************************************************* @@ -179,10 +180,9 @@ static int igb_detach(device_t); static int igb_shutdown(device_t); static int igb_suspend(device_t); static int igb_resume(device_t); -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX static int igb_mq_start(struct ifnet *, struct mbuf *); -static int igb_mq_start_locked(struct ifnet *, - struct tx_ring *, struct mbuf *); +static int igb_mq_start_locked(struct ifnet *, struct tx_ring *); static void igb_qflush(struct ifnet *); static void igb_deferred_mq_start(void *, int); #else @@ -295,7 +295,7 @@ static device_method_t igb_methods[] = { DEVMETHOD(device_shutdown, igb_shutdown), DEVMETHOD(device_suspend, igb_suspend), DEVMETHOD(device_resume, igb_resume), - {0, 0} + DEVMETHOD_END }; static driver_t igb_driver = { @@ -351,6 +351,16 @@ TUNABLE_INT("hw.igb.max_interrupt_rate", &igb_max_interrupt_rate); SYSCTL_INT(_hw_igb, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, &igb_max_interrupt_rate, 0, "Maximum interrupts per second"); +#if __FreeBSD_version >= 800000 +/* +** Tuneable number of buffers in the buf-ring (drbr_xxx) +*/ +static int igb_buf_ring_size = IGB_BR_SIZE; +TUNABLE_INT("hw.igb.buf_ring_size", &igb_buf_ring_size); +SYSCTL_INT(_hw_igb, OID_AUTO, buf_ring_size, CTLFLAG_RDTUN, + &igb_buf_ring_size, 0, "Size of the bufring"); +#endif + /* ** Header split causes the packet header to ** be dma'd to a seperate mbuf from the payload. @@ -365,8 +375,9 @@ SYSCTL_INT(_hw_igb, OID_AUTO, header_split, CTLFLAG_RDTUN, &igb_header_split, 0, "Enable receive mbuf header split"); /* -** This will autoconfigure based on -** the number of CPUs if left at 0. +** This will autoconfigure based on the +** number of CPUs and max supported +** MSIX messages if left at 0. */ static int igb_num_queues = 0; TUNABLE_INT("hw.igb.num_queues", &igb_num_queues); @@ -841,11 +852,11 @@ igb_resume(device_t dev) (ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) { for (int i = 0; i < adapter->num_queues; i++, txr++) { IGB_TX_LOCK(txr); -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX /* Process the stack queue only if not depleted */ if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && !drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_mq_start_locked(ifp, txr); #else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) igb_start_locked(txr, ifp); @@ -859,7 +870,7 @@ igb_resume(device_t dev) } -#if __FreeBSD_version < 800000 +#ifdef IGB_LEGACY_TX /********************************************************************* * Transmit entry point @@ -937,10 +948,11 @@ igb_start(struct ifnet *ifp) return; } -#else /* __FreeBSD_version >= 800000 */ +#else /* ~IGB_LEGACY_TX */ /* -** Multiqueue Transmit driver +** Multiqueue Transmit Entry: +** quick turnaround to the stack ** */ static int @@ -956,23 +968,23 @@ igb_mq_start(struct ifnet *ifp, struct mbuf *m) i = m->m_pkthdr.flowid % adapter->num_queues; else i = curcpu % adapter->num_queues; - txr = &adapter->tx_rings[i]; que = &adapter->queues[i]; - if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && - IGB_TX_TRYLOCK(txr)) { - err = igb_mq_start_locked(ifp, txr, m); + + err = drbr_enqueue(ifp, txr->br, m); + if (err) + return (err); + if (IGB_TX_TRYLOCK(txr)) { + err = igb_mq_start_locked(ifp, txr); IGB_TX_UNLOCK(txr); - } else { - err = drbr_enqueue(ifp, txr->br, m); + } else taskqueue_enqueue(que->tq, &txr->txq_task); - } return (err); } static int -igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m) +igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr) { struct adapter *adapter = txr->adapter; struct mbuf *next; @@ -981,36 +993,35 @@ igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m) IGB_TX_LOCK_ASSERT(txr); if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) || - (txr->queue_status == IGB_QUEUE_DEPLETED) || - adapter->link_active == 0) { - if (m != NULL) - err = drbr_enqueue(ifp, txr->br, m); - return (err); - } + adapter->link_active == 0) + return (ENETDOWN); enq = 0; - if (m == NULL) { - next = drbr_dequeue(ifp, txr->br); - } else if (drbr_needs_enqueue(ifp, txr->br)) { - if ((err = drbr_enqueue(ifp, txr->br, m)) != 0) - return (err); - next = drbr_dequeue(ifp, txr->br); - } else - next = m; /* Process the queue */ - while (next != NULL) { + while ((next = drbr_peek(ifp, txr->br)) != NULL) { if ((err = igb_xmit(txr, &next)) != 0) { - if (next != NULL) - err = drbr_enqueue(ifp, txr->br, next); + if (next == NULL) { + /* It was freed, move forward */ + drbr_advance(ifp, txr->br); + } else { + /* + * Still have one left, it may not be + * the same since the transmit function + * may have changed it. + */ + drbr_putback(ifp, txr->br, next); + } break; } + drbr_advance(ifp, txr->br); enq++; - drbr_stats_update(ifp, next->m_pkthdr.len, next->m_flags); + ifp->if_obytes += next->m_pkthdr.len; + if (next->m_flags & M_MCAST) + ifp->if_omcasts++; ETHER_BPF_MTAP(ifp, next); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) break; - next = drbr_dequeue(ifp, txr->br); } if (enq > 0) { /* Set the watchdog */ @@ -1036,7 +1047,7 @@ igb_deferred_mq_start(void *arg, int pending) IGB_TX_LOCK(txr); if (!drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_mq_start_locked(ifp, txr); IGB_TX_UNLOCK(txr); } @@ -1058,7 +1069,7 @@ igb_qflush(struct ifnet *ifp) } if_qflush(ifp); } -#endif /* __FreeBSD_version >= 800000 */ +#endif /* ~IGB_LEGACY_TX */ /********************************************************************* * Ioctl entry point @@ -1384,11 +1395,11 @@ igb_handle_que(void *context, int pending) IGB_TX_LOCK(txr); igb_txeof(txr); -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX /* Process the stack queue only if not depleted */ if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && !drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_mq_start_locked(ifp, txr); #else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) igb_start_locked(txr, ifp); @@ -1435,11 +1446,11 @@ igb_handle_link_locked(struct adapter *adapter) if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) { for (int i = 0; i < adapter->num_queues; i++, txr++) { IGB_TX_LOCK(txr); -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX /* Process the stack queue only if not depleted */ if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && !drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_mq_start_locked(ifp, txr); #else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) igb_start_locked(txr, ifp); @@ -1494,12 +1505,6 @@ igb_irq_fast(void *arg) } #ifdef DEVICE_POLLING -/********************************************************************* - * - * Legacy polling routine : if using this code you MUST be sure that - * multiqueue is not defined, ie, set igb_num_queues to 1. - * - *********************************************************************/ #if __FreeBSD_version >= 800000 #define POLL_RETURN_COUNT(a) (a) static int @@ -1510,8 +1515,8 @@ static void igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct adapter *adapter = ifp->if_softc; - struct igb_queue *que = adapter->queues; - struct tx_ring *txr = adapter->tx_rings; + struct igb_queue *que; + struct tx_ring *txr; u32 reg_icr, rx_done = 0; u32 loop = IGB_MAX_LOOP; bool more; @@ -1533,20 +1538,26 @@ igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) } IGB_CORE_UNLOCK(adapter); - igb_rxeof(que, count, &rx_done); + for (int i = 0; i < adapter->num_queues; i++) { + que = &adapter->queues[i]; + txr = que->txr; - IGB_TX_LOCK(txr); - do { - more = igb_txeof(txr); - } while (loop-- && more); -#if __FreeBSD_version >= 800000 - if (!drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_rxeof(que, count, &rx_done); + + IGB_TX_LOCK(txr); + do { + more = igb_txeof(txr); + } while (loop-- && more); +#ifndef IGB_LEGACY_TX + if (!drbr_empty(ifp, txr->br)) + igb_mq_start_locked(ifp, txr); #else - if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) - igb_start_locked(txr, ifp); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + igb_start_locked(txr, ifp); #endif - IGB_TX_UNLOCK(txr); + IGB_TX_UNLOCK(txr); + } + return POLL_RETURN_COUNT(rx_done); } #endif /* DEVICE_POLLING */ @@ -1567,16 +1578,20 @@ igb_msix_que(void *arg) u32 newitr = 0; bool more_rx; + /* Ignore spurious interrupts */ + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) + return; + E1000_WRITE_REG(&adapter->hw, E1000_EIMC, que->eims); ++que->irqs; IGB_TX_LOCK(txr); igb_txeof(txr); -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX /* Process the stack queue only if not depleted */ if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && !drbr_empty(ifp, txr->br)) - igb_mq_start_locked(ifp, txr, NULL); + igb_mq_start_locked(ifp, txr); #else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) igb_start_locked(txr, ifp); @@ -1685,7 +1700,6 @@ static void igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct adapter *adapter = ifp->if_softc; - u_char fiber_type = IFM_1000_SX; INIT_DEBUGOUT("igb_media_status: begin"); @@ -1702,26 +1716,31 @@ igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) ifmr->ifm_status |= IFM_ACTIVE; - if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || - (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) - ifmr->ifm_active |= fiber_type | IFM_FDX; - else { - switch (adapter->link_speed) { - case 10: - ifmr->ifm_active |= IFM_10_T; - break; - case 100: - ifmr->ifm_active |= IFM_100_TX; - break; - case 1000: - ifmr->ifm_active |= IFM_1000_T; - break; - } - if (adapter->link_duplex == FULL_DUPLEX) - ifmr->ifm_active |= IFM_FDX; + switch (adapter->link_speed) { + case 10: + ifmr->ifm_active |= IFM_10_T; + break; + case 100: + /* + ** Support for 100Mb SFP - these are Fiber + ** but the media type appears as serdes + */ + if (adapter->hw.phy.media_type == + e1000_media_type_internal_serdes) + ifmr->ifm_active |= IFM_100_FX; else - ifmr->ifm_active |= IFM_HDX; + ifmr->ifm_active |= IFM_100_TX; + break; + case 1000: + ifmr->ifm_active |= IFM_1000_T; + break; } + + if (adapter->link_duplex == FULL_DUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + IGB_CORE_UNLOCK(adapter); } @@ -1834,7 +1853,7 @@ retry: if (do_tso || (m_head->m_next != NULL && m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD)) { if (M_WRITABLE(*m_headp) == 0) { - m_head = m_dup(*m_headp, M_DONTWAIT); + m_head = m_dup(*m_headp, M_NOWAIT); m_freem(*m_headp); if (m_head == NULL) { *m_headp = NULL; @@ -1939,7 +1958,7 @@ retry: if (error == EFBIG && remap) { struct mbuf *m; - m = m_defrag(*m_headp, M_DONTWAIT); + m = m_defrag(*m_headp, M_NOWAIT); if (m == NULL) { adapter->mbuf_defrag_failed++; m_freem(*m_headp); @@ -2088,7 +2107,9 @@ static void igb_disable_promisc(struct adapter *adapter) { struct e1000_hw *hw = &adapter->hw; + struct ifnet *ifp = adapter->ifp; u32 reg; + int mcnt = 0; if (adapter->vf_ifp) { e1000_promisc_set_vf(hw, e1000_promisc_disabled); @@ -2096,7 +2117,31 @@ igb_disable_promisc(struct adapter *adapter) } reg = E1000_READ_REG(hw, E1000_RCTL); reg &= (~E1000_RCTL_UPE); - reg &= (~E1000_RCTL_MPE); + if (ifp->if_flags & IFF_ALLMULTI) + mcnt = MAX_NUM_MULTICAST_ADDRESSES; + else { + struct ifmultiaddr *ifma; +#if __FreeBSD_version < 800000 + IF_ADDR_LOCK(ifp); +#else + if_maddr_rlock(ifp); +#endif + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) + break; + mcnt++; + } +#if __FreeBSD_version < 800000 + IF_ADDR_UNLOCK(ifp); +#else + if_maddr_runlock(ifp); +#endif + } + /* Don't disable if in MAX groups */ + if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) + reg &= (~E1000_RCTL_MPE); E1000_WRITE_REG(hw, E1000_RCTL, reg); } @@ -2224,11 +2269,13 @@ timeout: static void igb_update_link_status(struct adapter *adapter) { - struct e1000_hw *hw = &adapter->hw; - struct ifnet *ifp = adapter->ifp; - device_t dev = adapter->dev; - struct tx_ring *txr = adapter->tx_rings; - u32 link_check, thstat, ctrl; + struct e1000_hw *hw = &adapter->hw; + struct e1000_fc_info *fc = &hw->fc; + struct ifnet *ifp = adapter->ifp; + device_t dev = adapter->dev; + struct tx_ring *txr = adapter->tx_rings; + u32 link_check, thstat, ctrl; + char *flowctl = NULL; link_check = thstat = ctrl = 0; @@ -2266,15 +2313,33 @@ igb_update_link_status(struct adapter *adapter) ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); } + /* Get the flow control for display */ + switch (fc->current_mode) { + case e1000_fc_rx_pause: + flowctl = "RX"; + break; + case e1000_fc_tx_pause: + flowctl = "TX"; + break; + case e1000_fc_full: + flowctl = "Full"; + break; + case e1000_fc_none: + default: + flowctl = "None"; + break; + } + /* Now we check if a transition has happened */ if (link_check && (adapter->link_active == 0)) { e1000_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); if (bootverbose) - device_printf(dev, "Link is up %d Mbps %s\n", + device_printf(dev, "Link is up %d Mbps %s," + " Flow Control: %s\n", adapter->link_speed, ((adapter->link_duplex == FULL_DUPLEX) ? - "Full Duplex" : "Half Duplex")); + "Full Duplex" : "Half Duplex"), flowctl); adapter->link_active = 1; ifp->if_baudrate = adapter->link_speed * 1000000; if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && @@ -2351,16 +2416,8 @@ igb_identify_hardware(struct adapter *adapter) device_t dev = adapter->dev; /* Make sure our PCI config space has the necessary stuff set */ + pci_enable_busmaster(dev); adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); - if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && - (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) { - INIT_DEBUGOUT("Memory Access and/or Bus Master " - "bits were not set!\n"); - adapter->hw.bus.pci_cmd_word |= - (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); - pci_write_config(dev, PCIR_COMMAND, - adapter->hw.bus.pci_cmd_word, 2); - } /* Save off the information about this board */ adapter->hw.vendor_id = pci_get_vendor(dev); @@ -2420,7 +2477,6 @@ igb_allocate_legacy(struct adapter *adapter) { device_t dev = adapter->dev; struct igb_queue *que = adapter->queues; - struct tx_ring *txr = adapter->tx_rings; int error, rid = 0; /* Turn off all interrupts */ @@ -2439,8 +2495,8 @@ igb_allocate_legacy(struct adapter *adapter) return (ENXIO); } -#if __FreeBSD_version >= 800000 - TASK_INIT(&txr->txq_task, 0, igb_deferred_mq_start, txr); +#ifndef IGB_LEGACY_TX + TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start, que->txr); #endif /* @@ -2522,9 +2578,8 @@ igb_allocate_msix(struct adapter *adapter) "Bound queue %d to cpu %d\n", i,igb_last_bind_cpu); igb_last_bind_cpu = CPU_NEXT(igb_last_bind_cpu); - igb_last_bind_cpu = igb_last_bind_cpu % mp_ncpus; } -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start, que->txr); #endif @@ -2750,7 +2805,7 @@ igb_free_pci_resources(struct adapter *adapter) for (int i = 0; i < adapter->num_queues; i++, que++) { if (que->tq != NULL) { -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX taskqueue_drain(que->tq, &que->txr->txq_task); #endif taskqueue_drain(que->tq, &que->que_task); @@ -2785,24 +2840,19 @@ igb_setup_msix(struct adapter *adapter) goto msi; /* First try MSI/X */ + msgs = pci_msix_count(dev); + if (msgs == 0) + goto msi; rid = PCIR_BAR(IGB_MSIX_BAR); adapter->msix_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (!adapter->msix_mem) { + if (adapter->msix_mem == NULL) { /* May not be enabled */ device_printf(adapter->dev, "Unable to map MSIX table \n"); goto msi; } - msgs = pci_msix_count(dev); - if (msgs == 0) { /* system has msix disabled */ - bus_release_resource(dev, SYS_RES_MEMORY, - PCIR_BAR(IGB_MSIX_BAR), adapter->msix_mem); - adapter->msix_mem = NULL; - goto msi; - } - /* Figure out a reasonable auto config value */ queues = (mp_ncpus > (msgs-1)) ? (msgs-1) : mp_ncpus; @@ -2845,20 +2895,32 @@ igb_setup_msix(struct adapter *adapter) "MSIX Configuration Problem, " "%d vectors configured, but %d queues wanted!\n", msgs, want); - return (0); + goto msi; } - if ((msgs) && pci_alloc_msix(dev, &msgs) == 0) { + if ((pci_alloc_msix(dev, &msgs) == 0) && (msgs == want)) { device_printf(adapter->dev, "Using MSIX interrupts with %d vectors\n", msgs); adapter->num_queues = queues; return (msgs); } + /* + ** If MSIX alloc failed or provided us with + ** less than needed, free and fall through to MSI + */ + pci_release_msi(dev); + msi: - msgs = pci_msi_count(dev); - if (msgs == 1 && pci_alloc_msi(dev, &msgs) == 0) { - device_printf(adapter->dev," Using MSI interrupt\n"); + if (adapter->msix_mem != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + PCIR_BAR(IGB_MSIX_BAR), adapter->msix_mem); + adapter->msix_mem = NULL; + } + msgs = 1; + if (pci_alloc_msi(dev, &msgs) == 0) { + device_printf(adapter->dev," Using an MSI interrupt\n"); return (msgs); } + device_printf(adapter->dev," Using a Legacy interrupt\n"); return (0); } @@ -3060,7 +3122,7 @@ igb_setup_interface(device_t dev, struct adapter *adapter) ifp->if_softc = adapter; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = igb_ioctl; -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX ifp->if_transmit = igb_mq_start; ifp->if_qflush = igb_qflush; #else @@ -3304,9 +3366,9 @@ igb_allocate_queues(struct adapter *adapter) error = ENOMEM; goto err_tx_desc; } -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX /* Allocate a buf ring */ - txr->br = buf_ring_alloc(IGB_BR_SIZE, M_DEVBUF, + txr->br = buf_ring_alloc(igb_buf_ring_size, M_DEVBUF, M_WAITOK, &txr->tx_mtx); #endif } @@ -3365,7 +3427,7 @@ err_tx_desc: igb_dma_free(adapter, &txr->txdma); free(adapter->rx_rings, M_DEVBUF); rx_fail: -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX buf_ring_free(txr->br, M_DEVBUF); #endif free(adapter->tx_rings, M_DEVBUF); @@ -3623,7 +3685,7 @@ igb_free_transmit_buffers(struct tx_ring *txr) tx_buffer->map = NULL; } } -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX if (txr->br != NULL) buf_ring_free(txr->br, M_DEVBUF); #endif @@ -3845,17 +3907,9 @@ igb_txeof(struct tx_ring *txr) IGB_TX_LOCK_ASSERT(txr); #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - struct netmap_adapter *na = NA(ifp); - - selwakeuppri(&na->tx_rings[txr->me].si, PI_NET); - IGB_TX_UNLOCK(txr); - IGB_CORE_LOCK(adapter); - selwakeuppri(&na->tx_si, PI_NET); - IGB_CORE_UNLOCK(adapter); - IGB_TX_LOCK(txr); - return FALSE; - } + if (netmap_tx_irq(ifp, txr->me | + (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT))) + return (FALSE); #endif /* DEV_NETMAP */ if (txr->tx_avail == adapter->num_tx_desc) { txr->queue_status = IGB_QUEUE_IDLE; @@ -3988,7 +4042,7 @@ igb_refresh_mbufs(struct rx_ring *rxr, int limit) if (rxr->hdr_split == FALSE) goto no_split; if (rxbuf->m_head == NULL) { - mh = m_gethdr(M_DONTWAIT, MT_DATA); + mh = m_gethdr(M_NOWAIT, MT_DATA); if (mh == NULL) goto update; } else @@ -4014,7 +4068,7 @@ igb_refresh_mbufs(struct rx_ring *rxr, int limit) htole64(hseg[0].ds_addr); no_split: if (rxbuf->m_pack == NULL) { - mp = m_getjcl(M_DONTWAIT, MT_DATA, + mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, adapter->rx_mbuf_sz); if (mp == NULL) goto update; @@ -4230,7 +4284,7 @@ igb_setup_receive_ring(struct rx_ring *rxr) goto skip_head; /* First the header */ - rxbuf->m_head = m_gethdr(M_DONTWAIT, MT_DATA); + rxbuf->m_head = m_gethdr(M_NOWAIT, MT_DATA); if (rxbuf->m_head == NULL) { error = ENOBUFS; goto fail; @@ -4252,7 +4306,7 @@ igb_setup_receive_ring(struct rx_ring *rxr) skip_head: /* Now the payload cluster */ - rxbuf->m_pack = m_getjcl(M_DONTWAIT, MT_DATA, + rxbuf->m_pack = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, adapter->rx_mbuf_sz); if (rxbuf->m_pack == NULL) { error = ENOBUFS; @@ -4335,8 +4389,8 @@ fail: * the rings that completed, the failing case will have * cleaned up for itself. 'i' is the endpoint. */ - for (int j = 0; j > i; ++j) { - rxr = &adapter->rx_rings[i]; + for (int j = 0; j < i; ++j) { + rxr = &adapter->rx_rings[j]; IGB_RX_LOCK(rxr); igb_free_receive_ring(rxr); IGB_RX_UNLOCK(rxr); @@ -4709,17 +4763,8 @@ igb_rxeof(struct igb_queue *que, int count, int *done) BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - struct netmap_adapter *na = NA(ifp); - - na->rx_rings[rxr->me].nr_kflags |= NKR_PENDINTR; - selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET); - IGB_RX_UNLOCK(rxr); - IGB_CORE_LOCK(adapter); - selwakeuppri(&na->rx_si, PI_NET); - IGB_CORE_UNLOCK(adapter); - return (0); - } + if (netmap_rx_irq(ifp, rxr->me | NETMAP_LOCKED_ENTER, &processed)) + return (FALSE); #endif /* DEV_NETMAP */ /* Main clean loop */ @@ -4752,7 +4797,7 @@ igb_rxeof(struct igb_queue *que, int count, int *done) /* Make sure all segments of a bad packet are discarded */ if (((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0) || (rxr->discard)) { - ifp->if_ierrors++; + adapter->dropped_pkts++; ++rxr->rx_discarded; if (!eop) /* Catch subsequent segs */ rxr->discard = TRUE; @@ -4844,7 +4889,7 @@ igb_rxeof(struct igb_queue *que, int count, int *done) rxr->fmp->m_pkthdr.ether_vtag = vtag; rxr->fmp->m_flags |= M_VLANTAG; } -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX rxr->fmp->m_pkthdr.flowid = que->msix; rxr->fmp->m_flags |= M_FLOWID; #endif @@ -4894,7 +4939,7 @@ next_desc: } if (done != NULL) - *done = rxdone; + *done += rxdone; IGB_RX_UNLOCK(rxr); return ((staterr & E1000_RXD_STAT_DD) ? TRUE : FALSE); diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.h index 2be0b08736..6f3a3a54ef 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_igb.h @@ -297,11 +297,11 @@ struct tx_ring { u32 next_to_clean; volatile u16 tx_avail; struct igb_tx_buffer *tx_buffers; -#if __FreeBSD_version >= 800000 +#ifndef IGB_LEGACY_TX struct buf_ring *br; + struct task txq_task; #endif bus_dma_tag_t txtag; - struct task txq_task; u32 bytes; u32 packets; diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c index ce863d3300..ac4a68f9f4 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2012, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,10 +32,11 @@ ******************************************************************************/ /*$FreeBSD$*/ -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" #include "opt_inet.h" #include "opt_inet6.h" + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" #endif #include @@ -87,7 +88,7 @@ /********************************************************************* * Legacy Em Driver version: *********************************************************************/ -char lem_driver_version[] = "1.0.4"; +char lem_driver_version[] = "1.0.6"; /********************************************************************* * PCI Device ID Table @@ -241,15 +242,12 @@ static void lem_enable_wakeup(device_t); static int lem_enable_phy_wakeup(struct adapter *); static void lem_led_func(void *, int); -#ifdef EM_LEGACY_IRQ static void lem_intr(void *); -#else /* FAST IRQ */ static int lem_irq_fast(void *); static void lem_handle_rxtx(void *context, int pending); static void lem_handle_link(void *context, int pending); static void lem_add_rx_process_limit(struct adapter *, const char *, const char *, int *, int); -#endif /* ~EM_LEGACY_IRQ */ #ifdef DEVICE_POLLING static poll_handler_t lem_poll; @@ -267,7 +265,7 @@ static device_method_t lem_methods[] = { DEVMETHOD(device_shutdown, lem_shutdown), DEVMETHOD(device_suspend, lem_suspend), DEVMETHOD(device_resume, lem_resume), - {0, 0} + DEVMETHOD_END }; #ifndef __HAIKU__ @@ -295,6 +293,9 @@ MODULE_DEPEND(lem, ether, 1, 1, 1); #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) +#define MAX_INTS_PER_SEC 8000 +#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) + static int lem_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); static int lem_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); static int lem_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); @@ -315,11 +316,13 @@ TUNABLE_INT("hw.em.txd", &lem_txd); TUNABLE_INT("hw.em.smart_pwr_down", &lem_smart_pwr_down); TUNABLE_INT("hw.em.sbp", &lem_debug_sbp); -#ifndef EM_LEGACY_IRQ +/* Interrupt style - default to fast */ +static int lem_use_legacy_irq = 0; +TUNABLE_INT("hw.em.use_legacy_irq", &lem_use_legacy_irq); + /* How many packets rxeof tries to clean at a time */ static int lem_rx_process_limit = 100; TUNABLE_INT("hw.em.rx_process_limit", &lem_rx_process_limit); -#endif /* Flow control setting - default to FULL */ static int lem_fc_setting = e1000_fc_full; @@ -461,14 +464,17 @@ lem_attach(device_t dev) &adapter->tx_abs_int_delay, E1000_REGISTER(&adapter->hw, E1000_TADV), lem_tx_abs_int_delay_dflt); + lem_add_int_delay_sysctl(adapter, "itr", + "interrupt delay limit in usecs/4", + &adapter->tx_itr, + E1000_REGISTER(&adapter->hw, E1000_ITR), + DEFAULT_ITR); } -#ifndef EM_LEGACY_IRQ /* Sysctls for limiting the amount of work done in the taskqueue */ lem_add_rx_process_limit(adapter, "rx_processing_limit", "max number of rx packets to process", &adapter->rx_process_limit, lem_rx_process_limit); -#endif /* Sysctl for setting the interface flow control */ lem_set_flow_cntrl(adapter, "flow_control", @@ -1214,22 +1220,6 @@ lem_init_locked(struct adapter *adapter) callout_reset(&adapter->timer, hz, lem_local_timer, adapter); e1000_clear_hw_cntrs_base_generic(&adapter->hw); - /* MSI/X configuration for 82574 */ - if (adapter->hw.mac.type == e1000_82574) { - int tmp; - tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); - tmp |= E1000_CTRL_EXT_PBA_CLR; - E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); - /* - ** Set the IVAR - interrupt vector routing. - ** Each nibble represents a vector, high bit - ** is enable, other 3 bits are the MSIX table - ** entry, we map RXQ0 to 0, TXQ0 to 1, and - ** Link (other) to 2, hence the magic number. - */ - E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); - } - #ifdef DEVICE_POLLING /* * Only enable interrupts if we are not polling, make sure @@ -1298,7 +1288,6 @@ lem_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) } #endif /* DEVICE_POLLING */ -#ifdef EM_LEGACY_IRQ /********************************************************************* * * Legacy Interrupt Service routine @@ -1312,7 +1301,8 @@ lem_intr(void *arg) u32 reg_icr; - if (ifp->if_capenable & IFCAP_POLLING) + if ((ifp->if_capenable & IFCAP_POLLING) || + ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)) return; EM_CORE_LOCK(adapter); @@ -1320,11 +1310,10 @@ lem_intr(void *arg) if (reg_icr & E1000_ICR_RXO) adapter->rx_overruns++; - if ((reg_icr == 0xffffffff) || (reg_icr == 0)) - goto out; - - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) - goto out; + if ((reg_icr == 0xffffffff) || (reg_icr == 0)) { + EM_CORE_UNLOCK(adapter); + return; + } if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { callout_stop(&adapter->timer); @@ -1334,23 +1323,22 @@ lem_intr(void *arg) lem_tx_purge(adapter); callout_reset(&adapter->timer, hz, lem_local_timer, adapter); - goto out; + EM_CORE_UNLOCK(adapter); + return; } - EM_TX_LOCK(adapter); + EM_CORE_UNLOCK(adapter); lem_rxeof(adapter, -1, NULL); + + EM_TX_LOCK(adapter); lem_txeof(adapter); if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) lem_start_locked(ifp); EM_TX_UNLOCK(adapter); - -out: - EM_CORE_UNLOCK(adapter); return; } -#else /* EM_FAST_IRQ, then fast interrupt routines only */ static void lem_handle_link(void *context, int pending) @@ -1380,12 +1368,16 @@ lem_handle_rxtx(void *context, int pending) if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - lem_rxeof(adapter, adapter->rx_process_limit, NULL); + bool more = lem_rxeof(adapter, adapter->rx_process_limit, NULL); EM_TX_LOCK(adapter); lem_txeof(adapter); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) lem_start_locked(ifp); EM_TX_UNLOCK(adapter); + if (more) { + taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); + return; + } } if (ifp->if_drv_flags & IFF_DRV_RUNNING) @@ -1434,7 +1426,6 @@ lem_irq_fast(void *arg) adapter->rx_overruns++; return FILTER_HANDLED; } -#endif /* ~EM_LEGACY_IRQ */ /********************************************************************* @@ -1610,7 +1601,7 @@ lem_xmit(struct adapter *adapter, struct mbuf **m_headp) if (error == EFBIG) { struct mbuf *m; - m = m_defrag(*m_headp, M_DONTWAIT); + m = m_defrag(*m_headp, M_NOWAIT); if (m == NULL) { adapter->mbuf_alloc_failed++; m_freem(*m_headp); @@ -1900,12 +1891,37 @@ lem_set_promisc(struct adapter *adapter) static void lem_disable_promisc(struct adapter *adapter) { - u32 reg_rctl; + struct ifnet *ifp = adapter->ifp; + u32 reg_rctl; + int mcnt = 0; reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); - reg_rctl &= (~E1000_RCTL_UPE); - reg_rctl &= (~E1000_RCTL_MPE); + if (ifp->if_flags & IFF_ALLMULTI) + mcnt = MAX_NUM_MULTICAST_ADDRESSES; + else { + struct ifmultiaddr *ifma; +#if __FreeBSD_version < 800000 + IF_ADDR_LOCK(ifp); +#else + if_maddr_rlock(ifp); +#endif + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) + break; + mcnt++; + } +#if __FreeBSD_version < 800000 + IF_ADDR_UNLOCK(ifp); +#else + if_maddr_runlock(ifp); +#endif + } + /* Don't disable if in MAX groups */ + if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) + reg_rctl &= (~E1000_RCTL_MPE); reg_rctl &= (~E1000_RCTL_SBP); E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); } @@ -2125,16 +2141,8 @@ lem_identify_hardware(struct adapter *adapter) device_t dev = adapter->dev; /* Make sure our PCI config space has the necessary stuff set */ + pci_enable_busmaster(dev); adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); - if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && - (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) { - device_printf(dev, "Memory Access and/or Bus Master bits " - "were not set!\n"); - adapter->hw.bus.pci_cmd_word |= - (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); - pci_write_config(dev, PCIR_COMMAND, - adapter->hw.bus.pci_cmd_word, 2); - } /* Save off the information about this board */ adapter->hw.vendor_id = pci_get_vendor(dev); @@ -2231,19 +2239,21 @@ lem_allocate_irq(struct adapter *adapter) return (ENXIO); } -#ifdef EM_LEGACY_IRQ - /* We do Legacy setup */ - if ((error = bus_setup_intr(dev, adapter->res[0], - INTR_TYPE_NET | INTR_MPSAFE, NULL, lem_intr, adapter, - &adapter->tag[0])) != 0) { - device_printf(dev, "Failed to register interrupt handler"); - return (error); + /* Do Legacy setup? */ + if (lem_use_legacy_irq) { + if ((error = bus_setup_intr(dev, adapter->res[0], + INTR_TYPE_NET | INTR_MPSAFE, NULL, lem_intr, adapter, + &adapter->tag[0])) != 0) { + device_printf(dev, + "Failed to register interrupt handler"); + return (error); + } + return (0); } -#else /* FAST_IRQ */ /* - * Try allocating a fast interrupt and the associated deferred - * processing contexts. + * Use a Fast interrupt and the associated + * deferred processing contexts. */ TASK_INIT(&adapter->rxtx_task, 0, lem_handle_rxtx, adapter); TASK_INIT(&adapter->link_task, 0, lem_handle_link, adapter); @@ -2260,7 +2270,6 @@ lem_allocate_irq(struct adapter *adapter) adapter->tq = NULL; return (error); } -#endif /* EM_LEGACY_IRQ */ return (0); } @@ -2608,7 +2617,6 @@ lem_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) static int lem_allocate_transmit_structures(struct adapter *adapter) { - int i; device_t dev = adapter->dev; struct em_buffer *tx_buffer; int error; @@ -2641,7 +2649,7 @@ lem_allocate_transmit_structures(struct adapter *adapter) } /* Create the descriptor buffer dma maps */ - for (i = 0; i < adapter->num_tx_desc; i++) { + for (int i = 0; i < adapter->num_tx_desc; i++) { tx_buffer = &adapter->tx_buffer_area[i]; error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); if (error != 0) { @@ -2665,7 +2673,6 @@ fail: static void lem_setup_transmit_structures(struct adapter *adapter) { - int i; struct em_buffer *tx_buffer; #ifdef DEV_NETMAP /* we are already locked */ @@ -2678,7 +2685,7 @@ lem_setup_transmit_structures(struct adapter *adapter) (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); /* Free any existing TX buffers */ - for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { + for (int i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { tx_buffer = &adapter->tx_buffer_area[i]; bus_dmamap_sync(adapter->txtag, tx_buffer->map, BUS_DMASYNC_POSTWRITE); @@ -2794,8 +2801,7 @@ lem_free_transmit_structures(struct adapter *adapter) INIT_DEBUGOUT("free_transmit_structures: begin"); if (adapter->tx_buffer_area != NULL) { - int i; - for (i = 0; i < adapter->num_tx_desc; i++) { + for (int i = 0; i < adapter->num_tx_desc; i++) { tx_buffer = &adapter->tx_buffer_area[i]; if (tx_buffer->m_head != NULL) { bus_dmamap_sync(adapter->txtag, tx_buffer->map, @@ -3003,10 +3009,8 @@ lem_txeof(struct adapter *adapter) EM_TX_LOCK_ASSERT(adapter); #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); + if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT))) return; - } #endif /* DEV_NETMAP */ if (adapter->num_tx_desc_avail == adapter->num_tx_desc) return; @@ -3123,7 +3127,7 @@ lem_get_buf(struct adapter *adapter, int i) struct em_buffer *rx_buffer; int error, nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { adapter->mbuf_cluster_failed++; return (ENOBUFS); @@ -3294,13 +3298,10 @@ lem_setup_receive_structures(struct adapter *adapter) * Enable receive unit. * **********************************************************************/ -#define MAX_INTS_PER_SEC 8000 -#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) static void lem_initialize_receive_unit(struct adapter *adapter) { - int i; struct ifnet *ifp = adapter->ifp; u64 bus_addr; u32 rctl, rxcsum; @@ -3324,20 +3325,6 @@ lem_initialize_receive_unit(struct adapter *adapter) E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); } - /* - ** When using MSIX interrupts we need to throttle - ** using the EITR register (82574 only) - */ - if (adapter->msix) - for (i = 0; i < 4; i++) - E1000_WRITE_REG(&adapter->hw, - E1000_EITR_82574(i), DEFAULT_ITR); - - /* Disable accelerated ackknowledge */ - if (adapter->hw.mac.type == e1000_82574) - E1000_WRITE_REG(&adapter->hw, - E1000_RFCTL, E1000_RFCTL_ACK_DIS); - /* Setup the Base and Length of the Rx Descriptor Ring */ bus_addr = adapter->rxdma.dma_paddr; E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), @@ -3401,19 +3388,13 @@ lem_initialize_receive_unit(struct adapter *adapter) * Tail Descriptor Pointers */ E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); + rctl = adapter->num_rx_desc - 1; /* default RDT value */ #ifdef DEV_NETMAP /* preserve buffers already made available to clients */ - if (ifp->if_capenable & IFCAP_NETMAP) { - struct netmap_adapter *na = NA(adapter->ifp); - struct netmap_kring *kring = &na->rx_rings[0]; - int t = na->num_rx_desc - 1 - kring->nr_hwavail; - - if (t >= na->num_rx_desc) - t -= na->num_rx_desc; - E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), t); - } else + if (ifp->if_capenable & IFCAP_NETMAP) + rctl -= NA(adapter->ifp)->rx_rings[0].nr_hwavail; #endif /* DEV_NETMAP */ - E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); + E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), rctl); return; } @@ -3497,13 +3478,8 @@ lem_rxeof(struct adapter *adapter, int count, int *done) BUS_DMASYNC_POSTREAD); #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - struct netmap_adapter *na = NA(ifp); - na->rx_rings[0].nr_kflags |= NKR_PENDINTR; - selwakeuppri(&na->rx_rings[0].si, PI_NET); - EM_RX_UNLOCK(adapter); - return (0); - } + if (netmap_rx_irq(ifp, 0 | NETMAP_LOCKED_ENTER, &rx_sent)) + return (FALSE); #endif /* DEV_NETMAP */ if (!((current_desc->status) & E1000_RXD_STAT_DD)) { @@ -3620,7 +3596,7 @@ skip: adapter->lmp = NULL; } } else { - ifp->if_ierrors++; + adapter->dropped_pkts++; discard: /* Reuse loaded DMA map and just update mbuf chain */ mp = adapter->rx_buffer_area[i].m_head; @@ -3696,7 +3672,7 @@ lem_fixup_rx(struct adapter *adapter) bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); m->m_data += ETHER_HDR_LEN; } else { - MGETHDR(n, M_DONTWAIT, MT_DATA); + MGETHDR(n, M_NOWAIT, MT_DATA); if (n != NULL) { bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); m->m_data += ETHER_HDR_LEN; @@ -3815,7 +3791,6 @@ lem_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) static void lem_setup_vlan_hw_support(struct adapter *adapter) { - int i; struct e1000_hw *hw = &adapter->hw; u32 reg; @@ -3832,7 +3807,7 @@ lem_setup_vlan_hw_support(struct adapter *adapter) ** A soft reset zero's out the VFTA, so ** we need to repopulate it now. */ - for (i = 0; i < EM_VFTA_SIZE; i++) + for (int i = 0; i < EM_VFTA_SIZE; i++) if (adapter->shadow_vfta[i] != 0) E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, adapter->shadow_vfta[i]); @@ -3846,10 +3821,6 @@ lem_setup_vlan_hw_support(struct adapter *adapter) reg &= ~E1000_RCTL_CFIEN; reg |= E1000_RCTL_VFE; E1000_WRITE_REG(hw, E1000_RCTL, reg); - - /* Update the frame size */ - E1000_WRITE_REG(&adapter->hw, E1000_RLPML, - adapter->max_frame_size + VLAN_TAG_SIZE); } static void @@ -3858,10 +3829,6 @@ lem_enable_intr(struct adapter *adapter) struct e1000_hw *hw = &adapter->hw; u32 ims_mask = IMS_ENABLE_MASK; - if (adapter->msix) { - E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); - ims_mask |= EM_MSIX_MASK; - } E1000_WRITE_REG(hw, E1000_IMS, ims_mask); } @@ -3870,9 +3837,7 @@ lem_disable_intr(struct adapter *adapter) { struct e1000_hw *hw = &adapter->hw; - if (adapter->msix) - E1000_WRITE_REG(hw, EM_EIAC, 0); - E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); + E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); } /* @@ -4097,13 +4062,12 @@ lem_enable_wakeup(device_t dev) static int lem_enable_phy_wakeup(struct adapter *adapter) { - int i; struct e1000_hw *hw = &adapter->hw; u32 mreg, ret = 0; u16 preg; /* copy MAC RARs to PHY RARs */ - for (i = 0; i < adapter->hw.mac.rar_entry_count; i++) { + for (int i = 0; i < adapter->hw.mac.rar_entry_count; i++) { mreg = E1000_READ_REG(hw, E1000_RAL(i)); e1000_write_phy_reg(hw, BM_RAR_L(i), (u16)(mreg & 0xFFFF)); e1000_write_phy_reg(hw, BM_RAR_M(i), @@ -4115,7 +4079,7 @@ lem_enable_phy_wakeup(struct adapter *adapter) } /* copy MAC MTA to PHY MTA */ - for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { + for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); e1000_write_phy_reg(hw, BM_MTA(i) + 1, @@ -4661,6 +4625,8 @@ lem_sysctl_int_delay(SYSCTL_HANDLER_ARGS) return (EINVAL); info->value = usecs; ticks = EM_USECS_TO_TICKS(usecs); + if (info->offset == E1000_ITR) /* units are 256ns here */ + ticks *= 4; adapter = info->adapter; @@ -4709,7 +4675,6 @@ lem_set_flow_cntrl(struct adapter *adapter, const char *name, OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); } -#ifndef EM_LEGACY_IRQ static void lem_add_rx_process_limit(struct adapter *adapter, const char *name, const char *description, int *limit, int value) @@ -4719,4 +4684,3 @@ lem_add_rx_process_limit(struct adapter *adapter, const char *name, SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); } -#endif diff --git a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.h b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.h index 787efb9cb2..e125557a57 100644 --- a/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.h +++ b/src/add-ons/kernel/drivers/network/ipro1000/dev/e1000/if_lem.h @@ -365,6 +365,7 @@ struct adapter { struct em_int_delay_info tx_abs_int_delay; struct em_int_delay_info rx_int_delay; struct em_int_delay_info rx_abs_int_delay; + struct em_int_delay_info tx_itr; /* * Transmit definitions diff --git a/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jme.c b/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jme.c index 7f0f9174f8..832acef0e5 100644 --- a/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jme.c +++ b/src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jme.c @@ -778,7 +778,7 @@ jme_attach(device_t dev) /* Set max allowable DMA size. */ if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->jme_flags |= JME_FLAG_PCIE; - burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); + burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); if (bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); @@ -1712,7 +1712,7 @@ jme_encap(struct jme_softc *sc, struct mbuf **m_head) if (M_WRITABLE(*m_head) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; @@ -1774,7 +1774,7 @@ jme_encap(struct jme_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -3181,7 +3181,7 @@ jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); /* diff --git a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c index a675456142..4c26fc8528 100644 --- a/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c +++ b/src/add-ons/kernel/drivers/network/marvell_yukon/dev/msk/if_msk.c @@ -162,7 +162,7 @@ TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); /* * Devices supported by this driver. */ -static struct msk_product { +static const struct msk_product { uint16_t msk_vendorid; uint16_t msk_deviceid; const char *msk_name; @@ -257,6 +257,7 @@ static int mskc_shutdown(device_t); static int mskc_setup_rambuffer(struct msk_softc *); static int mskc_suspend(device_t); static int mskc_resume(device_t); +static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); static void mskc_reset(struct msk_softc *); static int msk_probe(device_t); @@ -334,6 +335,8 @@ static device_method_t mskc_methods[] = { DEVMETHOD(device_resume, mskc_resume), DEVMETHOD(device_shutdown, mskc_shutdown), + DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), + DEVMETHOD_END }; @@ -368,9 +371,9 @@ static driver_t msk_driver = { static devclass_t msk_devclass; -DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); -DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); -DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); +DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, NULL, NULL); +DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, NULL, NULL); +DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL); static struct resource_spec msk_res_spec_io[] = { { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, @@ -648,8 +651,8 @@ msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { /* Wait until controller executes OP_TCPSTART command. */ - for (i = 10; i > 0; i--) { - DELAY(10); + for (i = 100; i > 0; i--) { + DELAY(100); idx = CSR_READ_2(sc_if->msk_softc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_GET_IDX_REG)); @@ -897,7 +900,7 @@ msk_newbuf(struct msk_if_softc *sc_if, int idx) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); @@ -955,7 +958,7 @@ msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) bus_dmamap_t map; int nsegs; - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); if (m == NULL) return (ENOBUFS); if ((m->m_flags & M_EXT) == 0) { @@ -1180,15 +1183,14 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) static int mskc_probe(device_t dev) { - struct msk_product *mp; + const struct msk_product *mp; uint16_t vendor, devid; int i; vendor = pci_get_vendor(dev); devid = pci_get_device(dev); mp = msk_products; - for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); - i++, mp++) { + for (i = 0; i < nitems(msk_products); i++, mp++) { if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { device_set_desc(dev, mp->msk_name); return (BUS_PROBE_DEFAULT); @@ -1696,6 +1698,12 @@ msk_attach(device_t dev) ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; } ifp->if_capenable = ifp->if_capabilities; + /* + * Disable RX checksum offloading on controllers that don't use + * new descriptor format but give chance to enable it. + */ + if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) + ifp->if_capenable &= ~IFCAP_RXCSUM; /* * Tell the upper layer(s) we support long frames. @@ -2113,6 +2121,13 @@ mskc_detach(device_t dev) return (0); } +static bus_dma_tag_t +mskc_get_dma_tag(device_t bus, device_t child __unused) +{ + + return (bus_get_dma_tag(bus)); +} + struct msk_dmamap_arg { bus_addr_t msk_busaddr; }; @@ -2658,7 +2673,7 @@ msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; @@ -2737,7 +2752,7 @@ msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c index f4c5bed419..04aeb06dda 100644 --- a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c @@ -1976,7 +1976,7 @@ nfe_newbuf(struct nfe_softc *sc, int idx) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); @@ -2032,7 +2032,7 @@ nfe_jnewbuf(struct nfe_softc *sc, int idx) bus_dmamap_t map; int nsegs; - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); if (m == NULL) return (ENOBUFS); if ((m->m_flags & M_EXT) == 0) { @@ -2401,7 +2401,7 @@ nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, NFE_MAX_SCATTER); + m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); if (m == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c index 8700aa2cd4..e2cc30e237 100644 --- a/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c +++ b/src/add-ons/kernel/drivers/network/pcnet/dev/le/lance.c @@ -394,7 +394,7 @@ lance_get(struct lance_softc *sc, int boff, int totlen) return (NULL); } - MGETHDR(m0, M_DONTWAIT, MT_DATA); + MGETHDR(m0, M_NOWAIT, MT_DATA); if (m0 == NULL) return (NULL); m0->m_pkthdr.rcvif = ifp; @@ -404,7 +404,7 @@ lance_get(struct lance_softc *sc, int boff, int totlen) while (totlen > 0) { if (totlen >= MINCLSIZE) { - MCLGET(m, M_DONTWAIT); + MCLGET(m, M_NOWAIT); if ((m->m_flags & M_EXT) == 0) goto bad; len = MCLBYTES; @@ -423,7 +423,7 @@ lance_get(struct lance_softc *sc, int boff, int totlen) totlen -= len; if (totlen > 0) { - MGET(newm, M_DONTWAIT, MT_DATA); + MGET(newm, M_NOWAIT, MT_DATA); if (newm == 0) goto bad; len = MLEN; diff --git a/src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vte.c b/src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vte.c index 7865ff23b9..dfc06e5360 100644 --- a/src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vte.c +++ b/src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vte.c @@ -1034,7 +1034,7 @@ vte_encap(struct vte_softc *sc, struct mbuf **m_head) if (M_WRITABLE(m) == 0) { if (m->m_next != NULL || padlen > 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); /* Release original mbuf chains. */ m_freem(*m_head); if (m == NULL) { @@ -1046,7 +1046,7 @@ vte_encap(struct vte_softc *sc, struct mbuf **m_head) } if (m->m_next != NULL) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1057,7 +1057,7 @@ vte_encap(struct vte_softc *sc, struct mbuf **m_head) if (padlen > 0) { if (M_TRAILINGSPACE(m) < padlen) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1422,7 +1422,7 @@ vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; @@ -1870,7 +1870,7 @@ vte_init_tx_ring(struct vte_softc *sc) /* Pre-allocate TX mbufs for deep copy. */ if (tx_deep_copy != 0) { for (i = 0; i < VTE_TX_RING_CNT; i++) { - sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, + sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (sc->vte_cdata.vte_txmbufs[i] == NULL) return (ENOBUFS); diff --git a/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c b/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c index 9a502674eb..582000cae9 100644 --- a/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c +++ b/src/add-ons/kernel/drivers/network/rtl8139/dev/mii/rlphy.c @@ -31,7 +31,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/rlphy.c,v 1.32.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $"); +__FBSDID("$FreeBSD$"); /* * driver for RealTek 8139 internal PHYs @@ -66,7 +66,7 @@ static device_method_t rlphy_methods[] = { DEVMETHOD(device_attach, rlphy_attach), DEVMETHOD(device_detach, mii_phy_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), - { 0, 0 } + DEVMETHOD_END }; static devclass_t rlphy_devclass; diff --git a/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephy.c b/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephy.c index aadc6fd967..aa919f5346 100644 --- a/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephy.c +++ b/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephy.c @@ -488,7 +488,7 @@ rgephy_load_dspcode(struct mii_softc *sc) static void rgephy_reset(struct mii_softc *sc) { - uint16_t ssr; + uint16_t pcr, ssr; if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { /* RTL8211C(L) */ @@ -499,6 +499,15 @@ rgephy_reset(struct mii_softc *sc) } } + if (sc->mii_mpd_rev >= 2) { + pcr = PHY_READ(sc, RGEPHY_MII_PCR); + if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { + pcr &= ~RGEPHY_PCR_MDI_MASK; + pcr |= RGEPHY_PCR_MDIX_AUTO; + PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); + } + } + mii_phy_reset(sc); DELAY(1000); rgephy_load_dspcode(sc); diff --git a/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephyreg.h b/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephyreg.h index caf86cd983..fb02ae6a5b 100644 --- a/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephyreg.h +++ b/src/add-ons/kernel/drivers/network/rtl81xx/dev/mii/rgephyreg.h @@ -137,6 +137,17 @@ #define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ #define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ +/* RTL8211B(L)/RTL8211C(L) */ +#define RGEPHY_MII_PCR 0x10 /* PHY Specific control register */ +#define RGEPHY_PCR_ASSERT_CRS 0x0800 +#define RGEPHY_PCR_FORCE_LINK 0x0400 +#define RGEPHY_PCR_MDI_MASK 0x0060 +#define RGEPHY_PCR_MDIX_AUTO 0x0040 +#define RGEPHY_PCR_MDIX_MANUAL 0x0020 +#define RGEPHY_PCR_MDI_MANUAL 0x0000 +#define RGEPHY_PCR_CLK125_DIS 0x0010 +#define RGEPHY_PCR_JABBER_DIS 0x0001 + /* RTL8211B(L)/RTL8211C(L) */ #define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */ #define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */ diff --git a/src/add-ons/kernel/drivers/network/rtl81xx/dev/re/if_re.c b/src/add-ons/kernel/drivers/network/rtl81xx/dev/re/if_re.c index a056ea7705..4aada1678b 100644 --- a/src/add-ons/kernel/drivers/network/rtl81xx/dev/re/if_re.c +++ b/src/add-ons/kernel/drivers/network/rtl81xx/dev/re/if_re.c @@ -171,7 +171,7 @@ TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); /* * Various supported device vendors/types and their names. */ -static const struct rl_type const re_devs[] = { +static const struct rl_type re_devs[] = { { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, @@ -194,7 +194,7 @@ static const struct rl_type const re_devs[] = { "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } }; -static const struct rl_hwrev const re_hwrevs[] = { +static const struct rl_hwrev re_hwrevs[] = { { RL_HWREV_8139, RL_8139, "", RL_MTU }, { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, @@ -758,7 +758,7 @@ re_diag(struct rl_softc *sc) u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; /* Allocate a single mbuf */ - MGETHDR(m0, M_DONTWAIT, MT_DATA); + MGETHDR(m0, M_NOWAIT, MT_DATA); if (m0 == NULL) return (ENOBUFS); @@ -1343,14 +1343,14 @@ re_attach(device_t dev) /* Disable ASPM L0S/L1. */ if (sc->rl_expcap != 0) { cap = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CAP, 2); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { + PCIER_LINK_CAP, 2); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { ctl = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, 2); + PCIER_LINK_CTL, 2); if ((ctl & 0x0003) != 0) { ctl &= ~0x0003; pci_write_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, ctl, 2); + PCIER_LINK_CTL, ctl, 2); device_printf(dev, "ASPM disabled\n"); } } else @@ -1587,7 +1587,8 @@ re_attach(device_t dev) * packet has IP options so disable TX IP checksum offloading. */ if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || - sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) + sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || + sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) ifp->if_hwassist = CSUM_TCP | CSUM_UDP; else ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; @@ -1753,8 +1754,12 @@ re_detach(device_t dev) bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); sc->rl_intrhand[0] = NULL; } - if (ifp != NULL) + if (ifp != NULL) { +#ifdef DEV_NETMAP + netmap_detach(ifp); +#endif /* DEV_NETMAP */ if_free(ifp); + } if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) rid = 0; else @@ -1843,9 +1848,6 @@ re_detach(device_t dev) bus_dma_tag_destroy(sc->rl_ldata.rl_stag); } -#ifdef DEV_NETMAP - netmap_detach(ifp); -#endif /* DEV_NETMAP */ if (sc->rl_parent_tag) bus_dma_tag_destroy(sc->rl_parent_tag); @@ -1885,7 +1887,7 @@ re_newbuf(struct rl_softc *sc, int idx) uint32_t cmdstat; int error, nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); @@ -1949,7 +1951,7 @@ re_jumbo_newbuf(struct rl_softc *sc, int idx) uint32_t cmdstat; int error, nsegs; - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MJUM9BYTES; @@ -2110,11 +2112,9 @@ re_rxeof(struct rl_softc *sc, int *rx_npktsp) ifp = sc->rl_ifp; #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - NA(ifp)->rx_rings->nr_kflags |= NKR_PENDINTR; - selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET); + if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT), + &rx_npkts)) return 0; - } #endif /* DEV_NETMAP */ if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) jumbo = 1; @@ -2358,10 +2358,8 @@ re_txeof(struct rl_softc *sc) ifp = sc->rl_ifp; #ifdef DEV_NETMAP - if (ifp->if_capenable & IFCAP_NETMAP) { - selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); + if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT))) return; - } #endif /* DEV_NETMAP */ /* Invalidate the TX descriptor list */ bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, @@ -2699,7 +2697,7 @@ re_encap(struct rl_softc *sc, struct mbuf **m_head) padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; if (M_WRITABLE(*m_head) == 0) { /* Get a writable copy. */ - m_new = m_dup(*m_head, M_DONTWAIT); + m_new = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m_new == NULL) { *m_head = NULL; @@ -2709,7 +2707,7 @@ re_encap(struct rl_softc *sc, struct mbuf **m_head) } if ((*m_head)->m_next != NULL || M_TRAILINGSPACE(*m_head) < padlen) { - m_new = m_defrag(*m_head, M_DONTWAIT); + m_new = m_defrag(*m_head, M_NOWAIT); if (m_new == NULL) { m_freem(*m_head); *m_head = NULL; @@ -2733,7 +2731,7 @@ re_encap(struct rl_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); if (error == EFBIG) { - m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); + m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); if (m_new == NULL) { m_freem(*m_head); *m_head = NULL; @@ -3418,7 +3416,8 @@ re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { rev = sc->rl_hwrev->rl_rev; if (rev == RL_HWREV_8168C || - rev == RL_HWREV_8168C_SPIN2) + rev == RL_HWREV_8168C_SPIN2 || + rev == RL_HWREV_8168CP) ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; else ifp->if_hwassist |= RE_CSUM_FEATURES; diff --git a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c index 4b24465928..e0394ae4aa 100644 --- a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c +++ b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_sk.c @@ -143,7 +143,7 @@ static const char rcsid[] = "$FreeBSD$"; #endif -static struct sk_type sk_devs[] = { +static const struct sk_type sk_devs[] = { { VENDORID_SK, DEVICEID_SK_V1, @@ -193,6 +193,7 @@ static int skc_detach(device_t); static int skc_shutdown(device_t); static int skc_suspend(device_t); static int skc_resume(device_t); +static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); static int sk_detach(device_t); static int sk_probe(device_t); static int sk_attach(device_t); @@ -300,6 +301,8 @@ static device_method_t skc_methods[] = { DEVMETHOD(device_resume, skc_resume), DEVMETHOD(device_shutdown, skc_shutdown), + DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), + DEVMETHOD_END }; @@ -334,9 +337,9 @@ static driver_t sk_driver = { static devclass_t sk_devclass; -DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); -DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); -DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); +DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL); +DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL); +DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL); static struct resource_spec sk_res_spec_io[] = { { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, @@ -982,7 +985,7 @@ sk_newbuf(sc_if, idx) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; @@ -1027,7 +1030,7 @@ sk_jumbo_newbuf(sc_if, idx) bus_dmamap_t map; int nsegs; - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); if (m == NULL) return (ENOBUFS); if ((m->m_flags & M_EXT) == 0) { @@ -1203,7 +1206,7 @@ static int skc_probe(dev) device_t dev; { - struct sk_type *t = sk_devs; + const struct sk_type *t = sk_devs; while(t->sk_name != NULL) { if ((pci_get_vendor(dev) == t->sk_vid) && @@ -1906,6 +1909,13 @@ skc_detach(dev) return(0); } +static bus_dma_tag_t +skc_get_dma_tag(device_t bus, device_t child __unused) +{ + + return (bus_get_dma_tag(bus)); +} + struct sk_dmamap_arg { bus_addr_t sk_busaddr; }; @@ -2411,7 +2421,7 @@ sk_encap(sc_if, m_head) error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nseg, 0); if (error == EFBIG) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -3221,7 +3231,7 @@ sk_init_xmac(sc_if) struct sk_softc *sc; struct ifnet *ifp; u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; - struct sk_bcom_hack bhack[] = { + static const struct sk_bcom_hack bhack[] = { { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, diff --git a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_skreg.h b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_skreg.h index d164ffcdc0..edeff66e37 100644 --- a/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_skreg.h +++ b/src/add-ons/kernel/drivers/network/syskonnect/dev/sk/if_skreg.h @@ -1289,7 +1289,7 @@ struct sk_type { u_int16_t sk_vid; u_int16_t sk_did; - char *sk_name; + const char *sk_name; }; #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) @@ -1450,7 +1450,9 @@ struct sk_softc { u_int32_t sk_pmd; /* physical media type */ u_int32_t sk_coppertype; u_int32_t sk_intrmask; +#ifdef __HAIKU__ u_int32_t sk_intstatus; +#endif int sk_int_mod; int sk_int_ticks; int sk_suspended; diff --git a/src/add-ons/kernel/drivers/network/via_rhine/dev/vr/if_vr.c b/src/add-ons/kernel/drivers/network/via_rhine/dev/vr/if_vr.c index 737084972a..2ab34e219f 100644 --- a/src/add-ons/kernel/drivers/network/via_rhine/dev/vr/if_vr.c +++ b/src/add-ons/kernel/drivers/network/via_rhine/dev/vr/if_vr.c @@ -119,7 +119,7 @@ static const struct vr_type { u_int16_t vr_did; int vr_quirks; const char *vr_name; -} const vr_devs[] = { +} vr_devs[] = { { VIA_VENDORID, VIA_DEVICEID_RHINE, VR_Q_NEEDALIGN, "VIA VT3043 Rhine I 10/100BaseTX" }, @@ -199,7 +199,7 @@ static const struct vr_tx_threshold_table { int tx_cfg; int bcr_cfg; int value; -} const vr_tx_threshold_tables[] = { +} vr_tx_threshold_tables[] = { { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, @@ -1245,7 +1245,7 @@ vr_newbuf(struct vr_softc *sc, int idx) bus_dmamap_t map; int nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); m->m_len = m->m_pkthdr.len = MCLBYTES; @@ -1806,7 +1806,7 @@ vr_encap(struct vr_softc *sc, struct mbuf **m_head) * to copy, just do it all the time. */ if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { - m = m_defrag(*m_head, M_DONTWAIT); + m = m_defrag(*m_head, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1825,7 +1825,7 @@ vr_encap(struct vr_softc *sc, struct mbuf **m_head) padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; @@ -1834,7 +1834,7 @@ vr_encap(struct vr_softc *sc, struct mbuf **m_head) *m_head = m; } if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { - m = m_defrag(m, M_DONTWAIT); + m = m_defrag(m, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1856,7 +1856,7 @@ vr_encap(struct vr_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); + m = m_collapse(*m_head, M_NOWAIT, VR_MAXFRAGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vge.c b/src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vge.c index a49af277f5..f891cf2a2e 100644 --- a/src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vge.c +++ b/src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vge.c @@ -1239,7 +1239,7 @@ vge_newbuf(struct vge_softc *sc, int prod) bus_dmamap_t map; int i, nsegs; - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); /* @@ -1827,7 +1827,7 @@ vge_encap(struct vge_softc *sc, struct mbuf **m_head) padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ - m = m_dup(*m_head, M_DONTWAIT); + m = m_dup(*m_head, M_NOWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; @@ -1836,7 +1836,7 @@ vge_encap(struct vge_softc *sc, struct mbuf **m_head) *m_head = m; } if (M_TRAILINGSPACE(m) < padlen) { - m = m_defrag(m, M_DONTWAIT); + m = m_defrag(m, M_NOWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; @@ -1858,7 +1858,7 @@ vge_encap(struct vge_softc *sc, struct mbuf **m_head) error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { - m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); + m = m_collapse(*m_head, M_NOWAIT, VGE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; diff --git a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c index ef729932d2..0a195a6983 100644 --- a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c +++ b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an.c @@ -203,7 +203,8 @@ static char an_conf_cache[256]; /* sysctl vars */ -SYSCTL_NODE(_hw, OID_AUTO, an, CTLFLAG_RD, 0, "Wireless driver parameters"); +static SYSCTL_NODE(_hw, OID_AUTO, an, CTLFLAG_RD, 0, + "Wireless driver parameters"); /* XXX violate ethernet/netgraph callback hooks */ extern void (*ng_ether_attach_p)(struct ifnet *ifp); @@ -946,12 +947,12 @@ an_rxeof(struct an_softc *sc) /* dump raw 802.11 packet to bpf and skip ip stack */ BPF_TAP(ifp, bpf_buf, len); } else { - MGETHDR(m, M_DONTWAIT, MT_DATA); + MGETHDR(m, M_NOWAIT, MT_DATA); if (m == NULL) { ifp->if_ierrors++; return; } - MCLGET(m, M_DONTWAIT); + MCLGET(m, M_NOWAIT); if (!(m->m_flags & M_EXT)) { m_freem(m); ifp->if_ierrors++; @@ -1037,12 +1038,12 @@ an_rxeof(struct an_softc *sc) if (an_rx_desc.an_done && !an_rx_desc.an_valid) { buf = sc->an_rx_buffer[count].an_dma_vaddr; - MGETHDR(m, M_DONTWAIT, MT_DATA); + MGETHDR(m, M_NOWAIT, MT_DATA); if (m == NULL) { ifp->if_ierrors++; return; } - MCLGET(m, M_DONTWAIT); + MCLGET(m, M_NOWAIT); if (!(m->m_flags & M_EXT)) { m_freem(m); ifp->if_ierrors++; diff --git a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pci.c b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pci.c index fe3467d83e..1c3032c942 100644 --- a/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pci.c +++ b/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/if_an_pci.c @@ -141,7 +141,6 @@ static int an_attach_pci(dev) device_t dev; { - u_int32_t command; struct an_softc *sc; int flags, error = 0; @@ -153,19 +152,6 @@ an_attach_pci(dev) sc->mpi350 = 1; sc->port_rid = PCIR_BAR(0); } else { - /* - * Map control/status registers. - */ - command = pci_read_config(dev, PCIR_COMMAND, 4); - command |= PCIM_CMD_PORTEN; - pci_write_config(dev, PCIR_COMMAND, command, 4); - command = pci_read_config(dev, PCIR_COMMAND, 4); - - if (!(command & PCIM_CMD_PORTEN)) { - device_printf(dev, "failed to enable I/O ports!\n"); - error = ENXIO; - goto fail; - } sc->port_rid = AN_PCI_LOIO; } error = an_alloc_port(dev, sc->port_rid, 1); diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c index cceb9a4a4c..c9a7a261af 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c @@ -76,7 +76,8 @@ extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...); /* NB: put this here instead of the driver to avoid circular references */ SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters"); -SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters"); +static SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, + "Atheros HAL parameters"); #ifdef AH_DEBUG int ath_hal_debug = 0; @@ -85,7 +86,7 @@ SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug, TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug); #endif /* AH_DEBUG */ -MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data"); +static MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data"); void* ath_hal_malloc(size_t size) diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c index 927f08e394..12cb67e437 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c @@ -298,12 +298,12 @@ ath_hal_v4kEepromAttach(struct ath_hal *ah) "%s Error reading Eeprom MAGIC\n", __func__); return HAL_EEREAD; } - } - HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n", - __func__, magic); - if (magic != AR5416_EEPROM_MAGIC) { - HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n"); - return HAL_EEMAGIC; + HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n", + __func__, magic); + if (magic != AR5416_EEPROM_MAGIC) { + HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n"); + return HAL_EEMAGIC; + } } ee = ath_hal_malloc(sizeof(HAL_EEPROM_v4k)); diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h index 40e718e467..8c4a1bb59e 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h @@ -143,7 +143,7 @@ typedef struct RfHalFuncs { int16_t *minPower, int16_t *maxPower, const struct ieee80211_channel *, uint16_t *rfXpdGain); HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, - const const struct ieee80211_channel *, + const struct ieee80211_channel *, int16_t *maxPow, int16_t *minPow); int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); } RF_HAL_FUNCS; diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_ani.c b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_ani.c index 5af6b240b6..82e00ed977 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_ani.c +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_ani.c @@ -342,11 +342,6 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); - /* Only set the ext channel cycpwr_thr1 field for ht/40 */ - if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) - OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, - AR_PHY_EXT_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); - if (level > aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath.c b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath.c index de6e49eaae..1afc34ec84 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath.c +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath.c @@ -258,7 +258,7 @@ static int ath_bstuck_threshold = 4; /* max missed beacons */ SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 0, "max missed beacon xmits before chip reset"); -MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); +static MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) #define HAL_MODE_HT40 \ diff --git a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath_tx.c b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath_tx.c index f4cee6d1de..618c932e1e 100644 --- a/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath_tx.c +++ b/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/if_ath_tx.c @@ -195,7 +195,7 @@ ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) */ if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ sc->sc_stats.ast_tx_linear++; - m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); + m = m_collapse(m0, M_NOWAIT, ATH_TXDESC); if (m == NULL) { ath_freetx(m0); sc->sc_stats.ast_tx_nombuf++; diff --git a/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/if_bwi.c b/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/if_bwi.c index 3e0f294e98..bd53240585 100644 --- a/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/if_bwi.c +++ b/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/if_bwi.c @@ -2539,7 +2539,7 @@ bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { error = ENOBUFS; @@ -3020,7 +3020,7 @@ bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, /* * Setup the embedded TX header */ - M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); + M_PREPEND(m, sizeof(*hdr), M_NOWAIT); if (m == NULL) { if_printf(ifp, "%s: prepend TX header failed\n", __func__); return ENOBUFS; @@ -3079,7 +3079,7 @@ bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, if (error) { /* error == EFBIG */ struct mbuf *m_new; - m_new = m_defrag(m, M_DONTWAIT); + m_new = m_defrag(m, M_NOWAIT); if (m_new == NULL) { if_printf(ifp, "%s: can't defrag TX buffer\n", __func__); @@ -3200,7 +3200,7 @@ bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, /* * Setup the embedded TX header */ - M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); + M_PREPEND(m, sizeof(*hdr), M_NOWAIT); if (m == NULL) { if_printf(ifp, "%s: prepend TX header failed\n", __func__); return ENOBUFS; @@ -3254,7 +3254,7 @@ bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, __func__, error); goto back; } - m_new = m_defrag(m, M_DONTWAIT); + m_new = m_defrag(m, M_NOWAIT); if (m_new == NULL) { if_printf(ifp, "%s: can't defrag TX buffer\n", __func__); diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/if_ipw.c b/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/if_ipw.c index 24f0a1f36e..4ffba3d826 100644 --- a/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/if_ipw.c +++ b/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/if_ipw.c @@ -709,7 +709,7 @@ ipw_dma_alloc(struct ipw_softc *sc) sbuf = &sc->rx_sbuf_list[i]; sbd->bd = &sc->rbd_list[i]; - sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + sbuf->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (sbuf->m == NULL) { device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); @@ -1207,7 +1207,7 @@ ipw_rx_data_intr(struct ipw_softc *sc, struct ipw_status *status, * drop the received packet and reuse the old mbuf. In the unlikely * case that the old mbuf can't be reloaded either, explicitly panic. */ - mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (mnew == NULL) { ifp->if_ierrors++; return; @@ -1661,7 +1661,7 @@ ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) return error; } if (error != 0) { - mnew = m_defrag(m0, M_DONTWAIT); + mnew = m_defrag(m0, M_NOWAIT); if (mnew == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi3945/dev/wpi/if_wpi.c b/src/add-ons/kernel/drivers/network/wlan/iprowifi3945/dev/wpi/if_wpi.c index d35ab79086..b50d067d07 100644 --- a/src/add-ons/kernel/drivers/network/wlan/iprowifi3945/dev/wpi/if_wpi.c +++ b/src/add-ons/kernel/drivers/network/wlan/iprowifi3945/dev/wpi/if_wpi.c @@ -987,7 +987,7 @@ wpi_alloc_rx_ring(struct wpi_softc *sc, struct wpi_rx_ring *ring) __func__, error); goto fail; } - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (m == NULL) { device_printf(sc->sc_dev, "%s: could not allocate rx mbuf\n", __func__); @@ -1491,7 +1491,7 @@ wpi_rx_intr(struct wpi_softc *sc, struct wpi_rx_desc *desc, } /* XXX don't need mbuf, just dma buffer */ - mnew = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (mnew == NULL) { DPRINTFN(WPI_DEBUG_RX, ("%s: no mbuf to restock ring\n", __func__)); @@ -1978,7 +1978,7 @@ wpi_tx_data(struct wpi_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, } if (error != 0) { /* XXX use m_collapse */ - mnew = m_defrag(m0, M_DONTWAIT); + mnew = m_defrag(m0, M_NOWAIT); if (mnew == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); @@ -2578,7 +2578,7 @@ wpi_scan(struct wpi_softc *sc) desc = &ring->desc[ring->cur]; data = &ring->data[ring->cur]; - data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (data->m == NULL) { device_printf(sc->sc_dev, "could not allocate mbuf for scan command\n"); diff --git a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c index 53efcb5077..fb8da59cf6 100644 --- a/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c +++ b/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/if_iwn.c @@ -89,7 +89,6 @@ static const struct iwn_ident iwn_ident_table[] = { { 0x8086, 0x008b, "Intel Centrino Wireless-N 1030" }, { 0x8086, 0x0090, "Intel Centrino Advanced-N 6230" }, { 0x8086, 0x0091, "Intel Centrino Advanced-N 6230" }, - { 0x8086, 0x088e, "Intel Centrino Advanced-N 6235" }, { 0x8086, 0x0885, "Intel Centrino Wireless-N + WiMAX 6150" }, { 0x8086, 0x0886, "Intel Centrino Wireless-N + WiMAX 6150" }, { 0x8086, 0x0896, "Intel Centrino Wireless-N 130" }, @@ -456,12 +455,12 @@ iwn_attach(device_t dev) pci_write_config(dev, 0x41, 0, 1); /* Hardware bug workaround. */ - reg = pci_read_config(dev, PCIR_COMMAND, 1); + reg = pci_read_config(dev, PCIR_COMMAND, 2); if (reg & PCIM_CMD_INTxDIS) { DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", __func__); reg &= ~PCIM_CMD_INTxDIS; - pci_write_config(dev, PCIR_COMMAND, reg, 1); + pci_write_config(dev, PCIR_COMMAND, reg, 2); } /* Enable bus-mastering. */ @@ -1376,7 +1375,7 @@ iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) goto fail; } - data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, + data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); if (data->m == NULL) { device_printf(sc->sc_dev, @@ -2333,7 +2332,7 @@ iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, return; } - m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); + m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); if (m1 == NULL) { DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", __func__); @@ -3543,7 +3542,7 @@ iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) return error; } /* Too many DMA segments, linearize mbuf. */ - m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); + m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER); if (m1 == NULL) { device_printf(sc->sc_dev, "%s: could not defrag mbuf\n", __func__); @@ -3747,7 +3746,7 @@ iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, return error; } /* Too many DMA segments, linearize mbuf. */ - m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); + m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER); if (m1 == NULL) { device_printf(sc->sc_dev, "%s: could not defrag mbuf\n", __func__); @@ -3980,7 +3979,7 @@ iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) /* Command is too large to fit in a descriptor. */ if (totlen > MCLBYTES) return EINVAL; - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (m == NULL) return ENOMEM; cmd = mtod(m, struct iwn_tx_cmd *); diff --git a/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo.c b/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo.c index dbb4f385be..9f298de0d7 100644 --- a/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo.c +++ b/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo.c @@ -123,7 +123,7 @@ enum { } while (0) #endif -MALLOC_DEFINE(M_MALODEV, "malodev", "malo driver dma buffers"); +static MALLOC_DEFINE(M_MALODEV, "malodev", "malo driver dma buffers"); static struct ieee80211vap *malo_vap_create(struct ieee80211com *, const char [IFNAMSIZ], int, enum ieee80211_opmode, int, @@ -854,7 +854,7 @@ malo_tx_dmasetup(struct malo_softc *sc, struct malo_txbuf *bf, struct mbuf *m0) */ if (error == EFBIG) { /* too many desc's, linearize */ sc->malo_stats.mst_tx_linear++; - m = m_defrag(m0, M_DONTWAIT); + m = m_defrag(m0, M_NOWAIT); if (m == NULL) { m_freem(m0); sc->malo_stats.mst_tx_nombuf++; @@ -1396,7 +1396,7 @@ malo_getrxmbuf(struct malo_softc *sc, struct malo_rxbuf *bf) int error; /* XXX don't need mbuf, just dma buffer */ - m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); if (m == NULL) { sc->malo_stats.mst_rx_nombuf++; /* XXX */ return NULL; diff --git a/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo_pci.c b/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo_pci.c index 9c2027b924..de9c39d01a 100644 --- a/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo_pci.c +++ b/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/if_malo_pci.c @@ -79,7 +79,7 @@ struct malo_pci_softc { * Tunable variables. */ SYSCTL_DECL(_hw_malo); -SYSCTL_NODE(_hw_malo, OID_AUTO, pci, CTLFLAG_RD, 0, +static SYSCTL_NODE(_hw_malo, OID_AUTO, pci, CTLFLAG_RD, 0, "Marvell 88W8335 driver PCI parameters"); static int msi_disable = 0; /* MSI disabled */ diff --git a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl.c b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl.c index f42a45d3a2..1ad63f643d 100644 --- a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl.c +++ b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl.c @@ -262,7 +262,7 @@ static void mwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix); } while (0) #endif -MALLOC_DEFINE(M_MWLDEV, "mwldev", "mwl driver dma buffers"); +static MALLOC_DEFINE(M_MWLDEV, "mwldev", "mwl driver dma buffers"); /* * Each packet has fixed front matter: a 2-byte length @@ -2807,7 +2807,7 @@ mwl_rx_proc(void *arg, int npending) * be a net loss. The tradeoff might be system * dependent (cache architecture is important). */ - MGETHDR(m, M_DONTWAIT, MT_DATA); + MGETHDR(m, M_NOWAIT, MT_DATA); if (m == NULL) { DPRINTF(sc, MWL_DEBUG_ANY, "%s: no rx mbuf\n", __func__); @@ -3084,9 +3084,9 @@ mwl_tx_dmasetup(struct mwl_softc *sc, struct mwl_txbuf *bf, struct mbuf *m0) if (error == EFBIG) { /* too many desc's, linearize */ sc->sc_stats.mst_tx_linear++; #if MWL_TXDESC > 1 - m = m_collapse(m0, M_DONTWAIT, MWL_TXDESC); + m = m_collapse(m0, M_NOWAIT, MWL_TXDESC); #else - m = m_defrag(m0, M_DONTWAIT); + m = m_defrag(m0, M_NOWAIT); #endif if (m == NULL) { m_freem(m0); diff --git a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl_pci.c b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl_pci.c index d800a5470c..d4d00dc95f 100644 --- a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl_pci.c +++ b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/if_mwl_pci.c @@ -120,29 +120,6 @@ mwl_pci_probe(device_t dev) return ENXIO; } -static u_int32_t -mwl_pci_setup(device_t dev) -{ - u_int32_t cmd; - - /* - * Enable memory mapping and bus mastering. - */ - cmd = pci_read_config(dev, PCIR_COMMAND, 4); - cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; - pci_write_config(dev, PCIR_COMMAND, cmd, 4); - cmd = pci_read_config(dev, PCIR_COMMAND, 4); - if ((cmd & PCIM_CMD_MEMEN) == 0) { - device_printf(dev, "failed to enable memory mapping\n"); - return 0; - } - if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) { - device_printf(dev, "failed to enable bus mastering\n"); - return 0; - } - return 1; -} - static int mwl_pci_attach(device_t dev) { @@ -152,11 +129,8 @@ mwl_pci_attach(device_t dev) sc->sc_dev = dev; - /* - * Enable memory mapping and bus mastering. - */ - if (!mwl_pci_setup(dev)) - return 0; + pci_enable_busmaster(dev); + /* * Setup memory-mapping of PCI registers. */ @@ -285,8 +259,7 @@ mwl_pci_resume(device_t dev) { struct mwl_pci_softc *psc = device_get_softc(dev); - if (!mwl_pci_setup(dev)) - return ENXIO; + pci_enable_busmaster(dev); mwl_resume(&psc->sc_sc); diff --git a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c index 3b8f27e2d3..55870afafc 100644 --- a/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c +++ b/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c @@ -190,7 +190,8 @@ static void dumpresult(struct mwl_hal_priv *, int showresult); #endif /* MWLHAL_DEBUG */ SYSCTL_DECL(_hw_mwl); -SYSCTL_NODE(_hw_mwl, OID_AUTO, hal, CTLFLAG_RD, 0, "Marvell HAL parameters"); +static SYSCTL_NODE(_hw_mwl, OID_AUTO, hal, CTLFLAG_RD, 0, + "Marvell HAL parameters"); static __inline void MWL_HAL_LOCK(struct mwl_hal_priv *mh) diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c index 815794cae6..0c3a00361f 100644 --- a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c @@ -673,7 +673,7 @@ rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring, goto fail; } - data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (data->m == NULL) { device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); @@ -1160,7 +1160,7 @@ rt2560_decryption_intr(struct rt2560_softc *sc) * mbuf. In the unlikely case that the old mbuf can't be * reloaded either, explicitly panic. */ - mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (mnew == NULL) { ifp->if_ierrors++; goto skip; @@ -1846,7 +1846,7 @@ rt2560_tx_data(struct rt2560_softc *sc, struct mbuf *m0, return error; } if (error != 0) { - mnew = m_defrag(m0, M_DONTWAIT); + mnew = m_defrag(m0, M_NOWAIT); if (mnew == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c index 63ab1d1c70..5210969dbe 100644 --- a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c @@ -682,7 +682,7 @@ rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, goto fail; } - data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (data->m == NULL) { device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); @@ -1030,7 +1030,7 @@ rt2661_rx_intr(struct rt2661_softc *sc) * mbuf. In the unlikely case that the old mbuf can't be * reloaded either, explicitly panic. */ - mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (mnew == NULL) { ifp->if_ierrors++; goto skip; @@ -1536,7 +1536,7 @@ rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, return error; } if (error != 0) { - mnew = m_defrag(m0, M_DONTWAIT); + mnew = m_defrag(m0, M_NOWAIT); if (mnew == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2860.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2860.c index f3a6bd64c9..138fbc0ba1 100644 --- a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2860.c +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2860.c @@ -743,7 +743,7 @@ rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) goto fail; } - data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (data->m == NULL) { device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); @@ -1237,7 +1237,7 @@ rt2860_rx_intr(struct rt2860_softc *sc) } #endif - m1 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (__predict_false(m1 == NULL)) { ifp->if_ierrors++; goto skip; @@ -1629,7 +1629,7 @@ rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) } } if (__predict_false(error != 0)) { - m1 = m_defrag(m, M_DONTWAIT); + m1 = m_defrag(m, M_NOWAIT); if (m1 == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); @@ -1881,7 +1881,7 @@ rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, } } if (__predict_false(error != 0)) { - m1 = m_defrag(m, M_DONTWAIT); + m1 = m_defrag(m, M_NOWAIT); if (m1 == NULL) { device_printf(sc->sc_dev, "could not defragment mbuf\n"); diff --git a/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi.c b/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi.c index 70574ff5d0..bc107336c0 100644 --- a/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi.c +++ b/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi.c @@ -166,7 +166,8 @@ wi_write_val(struct wi_softc *sc, int rid, u_int16_t val) return wi_write_rid(sc, rid, &val, sizeof(val)); } -SYSCTL_NODE(_hw, OID_AUTO, wi, CTLFLAG_RD, 0, "Wireless driver parameters"); +static SYSCTL_NODE(_hw, OID_AUTO, wi, CTLFLAG_RD, 0, + "Wireless driver parameters"); static struct timeval lasttxerror; /* time of last tx error msg */ static int curtxeps; /* current tx error msgs/sec */ @@ -1359,9 +1360,9 @@ wi_rx_intr(struct wi_softc *sc) } if (off + len > MHLEN) - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); else - m = m_gethdr(M_DONTWAIT, MT_DATA); + m = m_gethdr(M_NOWAIT, MT_DATA); if (m == NULL) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); ifp->if_ierrors++; diff --git a/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi_pci.c b/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi_pci.c index 958ba7ef49..30cdbc40ed 100644 --- a/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi_pci.c +++ b/src/add-ons/kernel/drivers/network/wlan/wavelanwifi/dev/wi/if_wi_pci.c @@ -137,23 +137,13 @@ static int wi_pci_attach(device_t dev) { struct wi_softc *sc; - u_int32_t command, wanted; + u_int32_t command; u_int16_t reg; int error; int timeout; sc = device_get_softc(dev); - command = pci_read_config(dev, PCIR_COMMAND, 4); - wanted = PCIM_CMD_PORTEN|PCIM_CMD_MEMEN; - command |= wanted; - pci_write_config(dev, PCIR_COMMAND, command, 4); - command = pci_read_config(dev, PCIR_COMMAND, 4); - if ((command & wanted) != wanted) { - device_printf(dev, "wi_pci_attach() failed to enable pci!\n"); - return (ENXIO); - } - if (sc->wi_bus_type != WI_BUS_PCI_NATIVE) { error = wi_alloc(dev, WI_PCI_IORES); if (error) diff --git a/src/libs/compat/freebsd_network/compat/dev/pci/pcireg.h b/src/libs/compat/freebsd_network/compat/dev/pci/pcireg.h index 216882c833..ef3513560f 100644 --- a/src/libs/compat/freebsd_network/compat/dev/pci/pcireg.h +++ b/src/libs/compat/freebsd_network/compat/dev/pci/pcireg.h @@ -64,6 +64,7 @@ #define PCIM_CMD_BACKTOBACK 0x0200 #define PCIM_CMD_INTxDIS 0x0400 #define PCIR_STATUS 0x06 +#define PCIM_STATUS_INTxSTATE 0x0008 #define PCIM_STATUS_CAPPRESENT 0x0010 #define PCIM_STATUS_66CAPABLE 0x0020 #define PCIM_STATUS_BACKTOBACK 0x0080 @@ -134,11 +135,22 @@ #define PCIZ_VC 0x0002 /* Virtual Channel */ #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ +#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ +#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ +#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ +#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ +#define PCIZ_RCRB 0x000a /* RCRB Header */ #define PCIZ_VENDOR 0x000b /* Vendor Unique */ #define PCIZ_ACS 0x000d /* Access Control Services */ #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ #define PCIZ_ATS 0x000f /* Address Translation Services */ #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ +#define PCIZ_MULTICAST 0x0012 /* Multicast */ +#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ +#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ +#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ +#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ +#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ /* config registers for header type 0 devices */ @@ -263,6 +275,9 @@ #define PCIS_STORAGE_SATA 0x06 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 #define PCIS_STORAGE_SAS 0x07 +#define PCIS_STORAGE_NVM 0x08 +#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 +#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 #define PCIS_STORAGE_OTHER 0x80 #define PCIC_NETWORK 0x02 @@ -597,6 +612,10 @@ #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ +#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ +#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ +#define PCIM_HTCAP_PM 0xe000 /* 11100 */ +#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ /* HT MSI Mapping Capability definitions. */ #define PCIM_HTCMD_MSI_ENABLE 0x0001 @@ -617,56 +636,258 @@ #define PCIR_SUBVENDCAP_ID 0x4 /* PCI Express definitions */ -#define PCIR_EXPRESS_FLAGS 0x2 -#define PCIM_EXP_FLAGS_VERSION 0x000F -#define PCIM_EXP_FLAGS_TYPE 0x00F0 -#define PCIM_EXP_TYPE_ENDPOINT 0x0000 -#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 -#define PCIM_EXP_TYPE_ROOT_PORT 0x0040 -#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 -#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 -#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 -#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 -#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 -#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 -#define PCIM_EXP_FLAGS_SLOT 0x0100 -#define PCIM_EXP_FLAGS_IRQ 0x3e00 -#define PCIR_EXPRESS_DEVICE_CAP 0x4 -#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 -#define PCIR_EXPRESS_DEVICE_CTL 0x8 -#define PCIM_EXP_CTL_NFER_ENABLE 0x0002 -#define PCIM_EXP_CTL_FER_ENABLE 0x0004 -#define PCIM_EXP_CTL_URR_ENABLE 0x0008 -#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 -#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 -#define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 -#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 -#define PCIR_EXPRESS_DEVICE_STA 0xa -#define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 -#define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 -#define PCIM_EXP_STA_FATAL_ERROR 0x0004 -#define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008 -#define PCIM_EXP_STA_AUX_POWER 0x0010 -#define PCIM_EXP_STA_TRANSACTION_PND 0x0020 -#define PCIR_EXPRESS_LINK_CAP 0xc -#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f -#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 -#define PCIM_LINK_CAP_ASPM 0x00000c00 -#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 -#define PCIM_LINK_CAP_L1_EXIT 0x00038000 -#define PCIM_LINK_CAP_PORT 0xff000000 -#define PCIR_EXPRESS_LINK_CTL 0x10 -#define PCIR_EXPRESS_LINK_STA 0x12 -#define PCIM_LINK_STA_SPEED 0x000f -#define PCIM_LINK_STA_WIDTH 0x03f0 -#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 -#define PCIM_LINK_STA_TRAINING 0x0800 -#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 -#define PCIR_EXPRESS_SLOT_CAP 0x14 -#define PCIR_EXPRESS_SLOT_CTL 0x18 -#define PCIR_EXPRESS_SLOT_STA 0x1a -#define PCIR_EXPRESS_ROOT_CTL 0x1c -#define PCIR_EXPRESS_ROOT_STA 0x20 +#define PCIER_FLAGS 0x2 +#define PCIEM_FLAGS_VERSION 0x000F +#define PCIEM_FLAGS_TYPE 0x00F0 +#define PCIEM_TYPE_ENDPOINT 0x0000 +#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 +#define PCIEM_TYPE_ROOT_PORT 0x0040 +#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 +#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 +#define PCIEM_TYPE_PCI_BRIDGE 0x0070 +#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 +#define PCIEM_TYPE_ROOT_INT_EP 0x0090 +#define PCIEM_TYPE_ROOT_EC 0x00a0 +#define PCIEM_FLAGS_SLOT 0x0100 +#define PCIEM_FLAGS_IRQ 0x3e00 +#define PCIER_DEVICE_CAP 0x4 +#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 +#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 +#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 +#define PCIEM_CAP_L0S_LATENCY 0x000001c0 +#define PCIEM_CAP_L1_LATENCY 0x00000e00 +#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 +#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 +#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 +#define PCIEM_CAP_FLR 0x10000000 +#define PCIER_DEVICE_CTL 0x8 +#define PCIEM_CTL_COR_ENABLE 0x0001 +#define PCIEM_CTL_NFER_ENABLE 0x0002 +#define PCIEM_CTL_FER_ENABLE 0x0004 +#define PCIEM_CTL_URR_ENABLE 0x0008 +#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 +#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 +#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 +#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 +#define PCIEM_CTL_AUX_POWER_PM 0x0400 +#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 +#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 +#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ +#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ +#define PCIER_DEVICE_STA 0xa +#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 +#define PCIEM_STA_NON_FATAL_ERROR 0x0002 +#define PCIEM_STA_FATAL_ERROR 0x0004 +#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 +#define PCIEM_STA_AUX_POWER 0x0010 +#define PCIEM_STA_TRANSACTION_PND 0x0020 +#define PCIER_LINK_CAP 0xc +#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f +#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 +#define PCIEM_LINK_CAP_ASPM 0x00000c00 +#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 +#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 +#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 +#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 +#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 +#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 +#define PCIEM_LINK_CAP_PORT 0xff000000 +#define PCIER_LINK_CTL 0x10 +#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 +#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 +#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 +#define PCIEM_LINK_CTL_ASPMC 0x0003 +#define PCIEM_LINK_CTL_RCB 0x0008 +#define PCIEM_LINK_CTL_LINK_DIS 0x0010 +#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 +#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 +#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 +#define PCIEM_LINK_CTL_ECPM 0x0100 +#define PCIEM_LINK_CTL_HAWD 0x0200 +#define PCIEM_LINK_CTL_LBMIE 0x0400 +#define PCIEM_LINK_CTL_LABIE 0x0800 +#define PCIER_LINK_STA 0x12 +#define PCIEM_LINK_STA_SPEED 0x000f +#define PCIEM_LINK_STA_WIDTH 0x03f0 +#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 +#define PCIEM_LINK_STA_TRAINING 0x0800 +#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 +#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 +#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 +#define PCIER_SLOT_CAP 0x14 +#define PCIEM_SLOT_CAP_APB 0x00000001 +#define PCIEM_SLOT_CAP_PCP 0x00000002 +#define PCIEM_SLOT_CAP_MRLSP 0x00000004 +#define PCIEM_SLOT_CAP_AIP 0x00000008 +#define PCIEM_SLOT_CAP_PIP 0x00000010 +#define PCIEM_SLOT_CAP_HPS 0x00000020 +#define PCIEM_SLOT_CAP_HPC 0x00000040 +#define PCIEM_SLOT_CAP_SPLV 0x00007f80 +#define PCIEM_SLOT_CAP_SPLS 0x00018000 +#define PCIEM_SLOT_CAP_EIP 0x00020000 +#define PCIEM_SLOT_CAP_NCCS 0x00040000 +#define PCIEM_SLOT_CAP_PSN 0xfff80000 +#define PCIER_SLOT_CTL 0x18 +#define PCIEM_SLOT_CTL_ABPE 0x0001 +#define PCIEM_SLOT_CTL_PFDE 0x0002 +#define PCIEM_SLOT_CTL_MRLSCE 0x0004 +#define PCIEM_SLOT_CTL_PDCE 0x0008 +#define PCIEM_SLOT_CTL_CCIE 0x0010 +#define PCIEM_SLOT_CTL_HPIE 0x0020 +#define PCIEM_SLOT_CTL_AIC 0x00c0 +#define PCIEM_SLOT_CTL_PIC 0x0300 +#define PCIEM_SLOT_CTL_PCC 0x0400 +#define PCIEM_SLOT_CTL_EIC 0x0800 +#define PCIEM_SLOT_CTL_DLLSCE 0x1000 +#define PCIER_SLOT_STA 0x1a +#define PCIEM_SLOT_STA_ABP 0x0001 +#define PCIEM_SLOT_STA_PFD 0x0002 +#define PCIEM_SLOT_STA_MRLSC 0x0004 +#define PCIEM_SLOT_STA_PDC 0x0008 +#define PCIEM_SLOT_STA_CC 0x0010 +#define PCIEM_SLOT_STA_MRLSS 0x0020 +#define PCIEM_SLOT_STA_PDS 0x0040 +#define PCIEM_SLOT_STA_EIS 0x0080 +#define PCIEM_SLOT_STA_DLLSC 0x0100 +#define PCIER_ROOT_CTL 0x1c +#define PCIER_ROOT_CAP 0x1e +#define PCIER_ROOT_STA 0x20 +#define PCIER_DEVICE_CAP2 0x24 +#define PCIER_DEVICE_CTL2 0x28 +#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f +#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 +#define PCIEM_CTL2_ARI 0x0020 +#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 +#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 +#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 +#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 +#define PCIEM_CTL2_LTR_ENABLE 0x0400 +#define PCIEM_CTL2_OBFF 0x6000 +#define PCIEM_OBFF_DISABLE 0x0000 +#define PCIEM_OBFF_MSGA_ENABLE 0x2000 +#define PCIEM_OBFF_MSGB_ENABLE 0x4000 +#define PCIEM_OBFF_WAKE_ENABLE 0x6000 +#define PCIEM_CTL2_END2END_TLP 0x8000 +#define PCIER_DEVICE_STA2 0x2a +#define PCIER_LINK_CAP2 0x2c +#define PCIER_LINK_CTL2 0x30 +#define PCIER_LINK_STA2 0x32 +#define PCIER_SLOT_CAP2 0x34 +#define PCIER_SLOT_CTL2 0x38 +#define PCIER_SLOT_STA2 0x3a + +/* Old compatibility definitions for PCI Express registers */ +#define PCIR_EXPRESS_FLAGS PCIER_FLAGS +#define PCIM_EXP_FLAGS_VERSION PCIEM_FLAGS_VERSION +#define PCIM_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE +#define PCIM_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT +#define PCIM_EXP_TYPE_LEGACY_ENDPOINT PCIEM_TYPE_LEGACY_ENDPOINT +#define PCIM_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT +#define PCIM_EXP_TYPE_UPSTREAM_PORT PCIEM_TYPE_UPSTREAM_PORT +#define PCIM_EXP_TYPE_DOWNSTREAM_PORT PCIEM_TYPE_DOWNSTREAM_PORT +#define PCIM_EXP_TYPE_PCI_BRIDGE PCIEM_TYPE_PCI_BRIDGE +#define PCIM_EXP_TYPE_PCIE_BRIDGE PCIEM_TYPE_PCIE_BRIDGE +#define PCIM_EXP_TYPE_ROOT_INT_EP PCIEM_TYPE_ROOT_INT_EP +#define PCIM_EXP_TYPE_ROOT_EC PCIEM_TYPE_ROOT_EC +#define PCIM_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT +#define PCIM_EXP_FLAGS_IRQ PCIEM_FLAGS_IRQ +#define PCIR_EXPRESS_DEVICE_CAP PCIER_DEVICE_CAP +#define PCIM_EXP_CAP_MAX_PAYLOAD PCIEM_CAP_MAX_PAYLOAD +#define PCIM_EXP_CAP_PHANTHOM_FUNCS PCIEM_CAP_PHANTHOM_FUNCS +#define PCIM_EXP_CAP_EXT_TAG_FIELD PCIEM_CAP_EXT_TAG_FIELD +#define PCIM_EXP_CAP_L0S_LATENCY PCIEM_CAP_L0S_LATENCY +#define PCIM_EXP_CAP_L1_LATENCY PCIEM_CAP_L1_LATENCY +#define PCIM_EXP_CAP_ROLE_ERR_RPT PCIEM_CAP_ROLE_ERR_RPT +#define PCIM_EXP_CAP_SLOT_PWR_LIM_VAL PCIEM_CAP_SLOT_PWR_LIM_VAL +#define PCIM_EXP_CAP_SLOT_PWR_LIM_SCALE PCIEM_CAP_SLOT_PWR_LIM_SCALE +#define PCIM_EXP_CAP_FLR PCIEM_CAP_FLR +#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL +#define PCIM_EXP_CTL_COR_ENABLE PCIEM_CTL_COR_ENABLE +#define PCIM_EXP_CTL_NFER_ENABLE PCIEM_CTL_NFER_ENABLE +#define PCIM_EXP_CTL_FER_ENABLE PCIEM_CTL_FER_ENABLE +#define PCIM_EXP_CTL_URR_ENABLE PCIEM_CTL_URR_ENABLE +#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE PCIEM_CTL_RELAXED_ORD_ENABLE +#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCIM_EXP_CTL_EXT_TAG_FIELD PCIEM_CTL_EXT_TAG_FIELD +#define PCIM_EXP_CTL_PHANTHOM_FUNCS PCIEM_CTL_PHANTHOM_FUNCS +#define PCIM_EXP_CTL_AUX_POWER_PM PCIEM_CTL_AUX_POWER_PM +#define PCIM_EXP_CTL_NOSNOOP_ENABLE PCIEM_CTL_NOSNOOP_ENABLE +#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST +#define PCIM_EXP_CTL_BRDG_CFG_RETRY PCIEM_CTL_BRDG_CFG_RETRY +#define PCIM_EXP_CTL_INITIATE_FLR PCIEM_CTL_INITIATE_FLR +#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA +#define PCIM_EXP_STA_CORRECTABLE_ERROR PCIEM_STA_CORRECTABLE_ERROR +#define PCIM_EXP_STA_NON_FATAL_ERROR PCIEM_STA_NON_FATAL_ERROR +#define PCIM_EXP_STA_FATAL_ERROR PCIEM_STA_FATAL_ERROR +#define PCIM_EXP_STA_UNSUPPORTED_REQ PCIEM_STA_UNSUPPORTED_REQ +#define PCIM_EXP_STA_AUX_POWER PCIEM_STA_AUX_POWER +#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND +#define PCIR_EXPRESS_LINK_CAP PCIER_LINK_CAP +#define PCIM_LINK_CAP_MAX_SPEED PCIEM_LINK_CAP_MAX_SPEED +#define PCIM_LINK_CAP_MAX_WIDTH PCIEM_LINK_CAP_MAX_WIDTH +#define PCIM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM +#define PCIM_LINK_CAP_L0S_EXIT PCIEM_LINK_CAP_L0S_EXIT +#define PCIM_LINK_CAP_L1_EXIT PCIEM_LINK_CAP_L1_EXIT +#define PCIM_LINK_CAP_CLOCK_PM PCIEM_LINK_CAP_CLOCK_PM +#define PCIM_LINK_CAP_SURPRISE_DOWN PCIEM_LINK_CAP_SURPRISE_DOWN +#define PCIM_LINK_CAP_DL_ACTIVE PCIEM_LINK_CAP_DL_ACTIVE +#define PCIM_LINK_CAP_LINK_BW_NOTIFY PCIEM_LINK_CAP_LINK_BW_NOTIFY +#define PCIM_LINK_CAP_ASPM_COMPLIANCE PCIEM_LINK_CAP_ASPM_COMPLIANCE +#define PCIM_LINK_CAP_PORT PCIEM_LINK_CAP_PORT +#define PCIR_EXPRESS_LINK_CTL PCIER_LINK_CTL +#define PCIM_EXP_LINK_CTL_ASPMC_DIS PCIEM_LINK_CTL_ASPMC_DIS +#define PCIM_EXP_LINK_CTL_ASPMC_L0S PCIEM_LINK_CTL_ASPMC_L0S +#define PCIM_EXP_LINK_CTL_ASPMC_L1 PCIEM_LINK_CTL_ASPMC_L1 +#define PCIM_EXP_LINK_CTL_ASPMC PCIEM_LINK_CTL_ASPMC +#define PCIM_EXP_LINK_CTL_RCB PCIEM_LINK_CTL_RCB +#define PCIM_EXP_LINK_CTL_LINK_DIS PCIEM_LINK_CTL_LINK_DIS +#define PCIM_EXP_LINK_CTL_RETRAIN_LINK PCIEM_LINK_CTL_RETRAIN_LINK +#define PCIM_EXP_LINK_CTL_COMMON_CLOCK PCIEM_LINK_CTL_COMMON_CLOCK +#define PCIM_EXP_LINK_CTL_EXTENDED_SYNC PCIEM_LINK_CTL_EXTENDED_SYNC +#define PCIM_EXP_LINK_CTL_ECPM PCIEM_LINK_CTL_ECPM +#define PCIM_EXP_LINK_CTL_HAWD PCIEM_LINK_CTL_HAWD +#define PCIM_EXP_LINK_CTL_LBMIE PCIEM_LINK_CTL_LBMIE +#define PCIM_EXP_LINK_CTL_LABIE PCIEM_LINK_CTL_LABIE +#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA +#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED +#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH +#define PCIM_LINK_STA_TRAINING_ERROR PCIEM_LINK_STA_TRAINING_ERROR +#define PCIM_LINK_STA_TRAINING PCIEM_LINK_STA_TRAINING +#define PCIM_LINK_STA_SLOT_CLOCK PCIEM_LINK_STA_SLOT_CLOCK +#define PCIM_LINK_STA_DL_ACTIVE PCIEM_LINK_STA_DL_ACTIVE +#define PCIM_LINK_STA_LINK_BW_MGMT PCIEM_LINK_STA_LINK_BW_MGMT +#define PCIM_LINK_STA_LINK_AUTO_BW PCIEM_LINK_STA_LINK_AUTO_BW +#define PCIR_EXPRESS_SLOT_CAP PCIER_SLOT_CAP +#define PCIR_EXPRESS_SLOT_CTL PCIER_SLOT_CTL +#define PCIR_EXPRESS_SLOT_STA PCIER_SLOT_STA +#define PCIR_EXPRESS_ROOT_CTL PCIER_ROOT_CTL +#define PCIR_EXPRESS_ROOT_CAP PCIER_ROOT_CAP +#define PCIR_EXPRESS_ROOT_STA PCIER_ROOT_STA +#define PCIR_EXPRESS_DEVICE_CAP2 PCIER_DEVICE_CAP2 +#define PCIR_EXPRESS_DEVICE_CTL2 PCIER_DEVICE_CTL2 +#define PCIM_EXP_CTL2_COMP_TIMEOUT_VAL PCIEM_CTL2_COMP_TIMEOUT_VAL +#define PCIM_EXP_CTL2_COMP_TIMEOUT_DIS PCIEM_CTL2_COMP_TIMEOUT_DIS +#define PCIM_EXP_CTL2_ARI PCIEM_CTL2_ARI +#define PCIM_EXP_CTL2_ATOMIC_REQ_ENABLE PCIEM_CTL2_ATOMIC_REQ_ENABLE +#define PCIM_EXP_CTL2_ATOMIC_EGR_BLOCK PCIEM_CTL2_ATOMIC_EGR_BLOCK +#define PCIM_EXP_CTL2_ID_ORDERED_REQ_EN PCIEM_CTL2_ID_ORDERED_REQ_EN +#define PCIM_EXP_CTL2_ID_ORDERED_CMP_EN PCIEM_CTL2_ID_ORDERED_CMP_EN +#define PCIM_EXP_CTL2_LTR_ENABLE PCIEM_CTL2_LTR_ENABLE +#define PCIM_EXP_CTL2_OBFF PCIEM_CTL2_OBFF +#define PCIM_EXP_OBFF_DISABLE PCIEM_OBFF_DISABLE +#define PCIM_EXP_OBFF_MSGA_ENABLE PCIEM_OBFF_MSGA_ENABLE +#define PCIM_EXP_OBFF_MSGB_ENABLE PCIEM_OBFF_MSGB_ENABLE +#define PCIM_EXP_OBFF_WAKE_ENABLE PCIEM_OBFF_WAKE_ENABLE +#define PCIM_EXP_CTL2_END2END_TLP PCIEM_CTL2_END2END_TLP +#define PCIR_EXPRESS_DEVICE_STA2 PCIER_DEVICE_STA2 +#define PCIR_EXPRESS_LINK_CAP2 PCIER_LINK_CAP2 +#define PCIR_EXPRESS_LINK_CTL2 PCIER_LINK_CTL2 +#define PCIR_EXPRESS_LINK_STA2 PCIER_LINK_STA2 +#define PCIR_EXPRESS_SLOT_CAP2 PCIER_SLOT_CAP2 +#define PCIR_EXPRESS_SLOT_CTL2 PCIER_SLOT_CTL2 +#define PCIR_EXPRESS_SLOT_STA2 PCIER_SLOT_STA2 /* MSI-X definitions */ #define PCIR_MSIX_CTRL 0x2 @@ -697,6 +918,7 @@ #define PCIR_AER_UC_STATUS 0x04 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 +#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 #define PCIM_AER_UC_POISONED_TLP 0x00001000 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 @@ -707,6 +929,10 @@ #define PCIM_AER_UC_ECRC_ERROR 0x00080000 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 +#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 +#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 +#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 +#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ #define PCIR_AER_COR_STATUS 0x10 @@ -715,6 +941,9 @@ #define PCIM_AER_COR_BAD_DLLP 0x00000080 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 +#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 +#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 +#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ #define PCIR_AER_CAP_CONTROL 0x18 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f @@ -722,6 +951,9 @@ #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 +#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 +#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 +#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 #define PCIR_AER_HEADER_LOG 0x1c #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 @@ -738,6 +970,7 @@ #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ +#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ /* Virtual Channel definitions */ #define PCIR_VC_CAP1 0x04