From d96acb0dde724cffaaac4f944315ccc17451cb37 Mon Sep 17 00:00:00 2001
From: Rudolf Cornelissen <rudolf.cornelissen@gmail.com>
Date: Thu, 6 Jan 2005 15:09:11 +0000
Subject: [PATCH] more DMA related info, modified PLL type detection: all NV40+
 have extended PLL's.

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10591 a95241bf-73f2-0310-859d-f6bbb57e9c96
---
 .../accelerants/nvidia/engine/nv_acc.c        |  8 ++++++--
 .../accelerants/nvidia/engine/nv_info.c       | 19 +++++++------------
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc.c b/src/add-ons/accelerants/nvidia/engine/nv_acc.c
index 97a60380bd..d94398e017 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_acc.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_acc.c
@@ -93,7 +93,10 @@ status_t nv_acc_init()
 	/* cache1 DMA instance adress = none (b0-15);
 	 * instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */
 	/* note:
-	 * should point to a DMA definition in CTX register space (which is sort of RAM) */
+	 * should point to a DMA definition in CTX register space (which is sort of RAM).
+	 * This define tells the engine where the DMA cmd buffer is and what it's size is;
+	 * inside that cmd buffer you'll find the engine handles for the FIFO channels,
+	 * followed by actual issued engine commands. */
 	ACCW(PF_CACH1_DMAI, 0x00000000);
 
 	/* cache0 push0 access disabled */
@@ -205,7 +208,8 @@ status_t nv_acc_init()
 	/* note:
 	 * CTX determines which HT handles point to what engine commands.
 	 * (CTX registers are actually a sort of RAM space.) */
-	/* (setup a DMA define 'set') */
+	/* setup a DMA define for use by command defines below.
+	 * (would currently be used by CTX 'sets' 0x6 upto/including 0xe: 3D stuff.) */
 	ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;
 								  * DMA target node is NVM (non-volatile memory?)
 								  * (instead of doing PCI or AGP transfers) */
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c
index 6c4392ce8a..4c6ac9e821 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_info.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c
@@ -1,7 +1,7 @@
 /* Read initialisation information from card */
 /* some bits are hacks, where PINS is not known */
 /* Author:
-   Rudolf Cornelissen 7/2003-12/2004
+   Rudolf Cornelissen 7/2003-1/2005
 */
 
 #define MODULE_BIT 0x00002000
@@ -2801,22 +2801,17 @@ static void pinsnv20_arch_fake(void)
 static void pinsnv30_arch_fake(void)
 {
 	/* determine PLL type */
-	LOG(8,("INFO: NV30 architecture chip, PIXPLLC2 DAC1 = $%08x, DAC2 = $%08x\n",
-		DACR(PIXPLLC2), DAC2R(PIXPLLC2)));
-	switch (si->ps.card_type)
+	if ((si->ps.card_type == NV31) ||
+		(si->ps.card_type == NV36) ||
+		(si->ps.card_type >= NV40))
 	{
-	case NV31:
-	case NV36:
-	/* fixme? could be all >= NV40 cards have extended PLL's... (these 2 are confirmed) */
-	case NV40:
-	case NV43:
 		/* we have a extended PLL */
 		si->ps.ext_pll = true;
-		break;
-	default:
+	}
+	else
+	{
 		/* we have a standard PLL */
 		si->ps.ext_pll = false;
-		break;
 	}
 	/* carefull not to take to high limits, and high should be >= 2x low. */
 	si->ps.max_system_vco = 350;