diff --git a/headers/private/graphics/cirrus/DriverInterface.h b/headers/private/graphics/cirrus/DriverInterface.h deleted file mode 100644 index cad48029b7..0000000000 --- a/headers/private/graphics/cirrus/DriverInterface.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson; - Apsed; - Rudolf Cornelissen 10/2002-9/2004. -*/ - -#ifndef DRIVERINTERFACE_H -#define DRIVERINTERFACE_H - -#include -#include "video_overlay.h" -#include -#include -#include -#include "AGP.h" - -#define DRIVER_PREFIX "skel" - -// XXX: need to shuffle this around -#define TI_REF_FREQ 14.318 /* 3025 only */ - -//#define cirrus_5434 0 -//#define cirrus_5430 1 - -// PCI IDs, as defined in QEMU's code -#define CIRRUS_ID_CLGD5430 (0x28<<2) -#define CIRRUS_ID_CLGD5434 (0x2A<<2) -#define CIRRUS_ID_CLGD5436 (0x2B<<2) -#define CIRRUS_ID_CLGD5446 (0x2E<<2) -#define CIRRUS_ID_CLGD5462 0x00d0 -#define CIRRUS_ID_CLGD5465 0x00d6 - -/* - Internal driver state (also for sharing info between driver and accelerant) -*/ -#if defined(__cplusplus) -extern "C" { -#endif - -typedef struct { - sem_id sem; - int32 ben; -} benaphore; - -#define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; -#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); -#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); -#define DELETE_BEN(x) delete_sem(x.sem); - - -#define SKEL_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ - -/*dualhead extensions to flags*/ -#define DUALHEAD_OFF (0<<6) -#define DUALHEAD_CLONE (1<<6) -#define DUALHEAD_ON (2<<6) -#define DUALHEAD_SWITCH (3<<6) -#define DUALHEAD_BITS (3<<6) -#define DUALHEAD_CAPABLE (1<<8) -#define TV_BITS (3<<9) -#define TV_MON (0<<9 -#define TV_PAL (1<<9) -#define TV_NTSC (2<<9) -#define TV_CAPABLE (1<<11) -#define TV_VIDEO (1<<12) - -#define SKD_MOVE_CURSOR 0x00000001 -#define SKD_PROGRAM_CLUT 0x00000002 -#define SKD_SET_START_ADDR 0x00000004 -#define SKD_SET_CURSOR 0x00000008 -#define SKD_HANDLER_INSTALLED 0x80000000 - -enum { - ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, - ENG_GET_PCI, - ENG_SET_PCI, - ENG_DEVICE_NAME, - ENG_RUN_INTERRUPTS, - ENG_GET_NTH_AGP_INFO, - ENG_ENABLE_AGP, - ENG_ISA_OUT, - ENG_ISA_IN -}; - -/* max. number of overlay buffers */ -#define MAXBUFFERS 3 - -/* internal used info on overlay buffers */ -typedef struct -{ - uint16 slopspace; - uint32 size; -} int_buf_info; - -typedef struct settings { // apsed, see comments in skel.settings - // for driver - char accelerant[B_FILE_NAME_LENGTH]; - bool dumprom; - // for accelerant - uint32 logmask; - uint32 memory; - bool usebios; - bool hardcursor; - bool switchhead; - bool force_pci; - bool unhide_fw; - bool pgm_panel; -} settings; - -/*shared info*/ -typedef struct { - /*a few ID things*/ - uint16 vendor_id; /* PCI vendor ID, from pci_info */ - uint16 device_id; /* PCI device ID, from pci_info */ - uint8 revision; /* PCI device revsion, from pci_info */ - uint8 bus; /* PCI bus number, from pci_info */ - uint8 device; /* PCI device number on bus, from pci_info */ - uint8 function; /* PCI function number in device, from pci_info */ - - /* bug workaround for 4.5.0 */ - uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ - uint32 * clone_bugfix_regs; - - /*memory mappings*/ - area_id regs_area; /* Kernel's area_id for the memory mapped registers. - It will be cloned into the accelerant's address - space. */ - - area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ - area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ - area_id dma_buffer_area; /* Area assigned for dma*/ - - void *framebuffer; /* As viewed from virtual memory */ - void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ - - void *pseudo_dma; /* As viewed from virtual memory */ - - void *dma_buffer; /* buffer for dma*/ - void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ - - /*screenmode list*/ - area_id mode_area; /* Contains the list of display modes the driver supports */ - uint32 mode_count; /* Number of display modes in the list */ - - /*flags - used by driver*/ - uint32 flags; - - /*vblank semaphore*/ - sem_id vblank; /* The vertical blank semaphore. Ownership will be - transfered to the team opening the device first */ - /*cursor information*/ - struct { - uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ - uint16 hot_y; /* is 0,0 */ - uint16 x; /* The location of the cursor hot spot on the */ - uint16 y; /* desktop */ - uint16 width; /* Width and height of the cursor shape (always 16!) */ - uint16 height; - bool is_visible; /* Is the cursor currently displayed? */ - bool dh_right; /* Is cursor on right side of stretched screen? */ - } cursor; - - /*colour lookup table*/ - uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ - - /*more display mode stuff*/ - display_mode dm; /* current display mode configuration: head1 */ - display_mode dm2; /* current display mode configuration: head2 */ - bool acc_mode; /* signals (non)accelerated mode */ - bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ - bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ - - /*frame buffer config - for BDirectScreen*/ - frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ - frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ - - /*acceleration engine*/ - struct { - uint32 count; /* last dwgsync slot used */ - uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ - benaphore lock; /* for serializing access to the acceleration engine */ - } engine; - - /* card info - information gathered from PINS (and other sources) */ - - struct - { - /* specialised registers for card initialisation read from NV BIOS (pins) */ - - /* general card information */ - uint32 card_type; /* see card_type enum above */ - //uint32 card_arch; /* see card_arch enum above */ - bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ - bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ - bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ - bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ - bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ - bool tmds1_active; /* found panel on CRTC1 that is active */ - bool tmds2_active; /* found panel on CRTC2 that is active */ - display_timing p1_timing; /* 'modeline' fetched for panel 1 */ - display_timing p2_timing; /* 'modeline' fetched for panel 2 */ - float panel1_aspect; /* panel's aspect ratio */ - float panel2_aspect; /* panel's aspect ratio */ - bool crtc2_prim; /* using CRTC2 as primary CRTC */ - uint32 tvout_chip_type; /* see tvchip_type enum above */ - uint8 monitors; /* output devices connection matrix */ - status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ - - /* PINS */ - float f_ref; /* PLL reference-oscillator frequency (Mhz) */ - bool ext_pll; /* the extended PLL contains more dividers */ - uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ - uint32 min_system_vco; - uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ - uint32 min_pixel_vco; - uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ - uint32 min_video_vco; - uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ - uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ - uint32 max_dac1_clock; /* dac1 limits (Mhz) */ - uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ - uint32 max_dac1_clock_16; - uint32 max_dac1_clock_24; - uint32 max_dac1_clock_32; - uint32 max_dac1_clock_32dh; - uint32 max_dac2_clock; /* dac2 limits (Mhz) */ - uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ - uint32 max_dac2_clock_16; - uint32 max_dac2_clock_24; - uint32 max_dac2_clock_32; - uint32 max_dac2_clock_32dh; - bool secondary_head; /* presence of functions */ - bool tvout; - bool primary_dvi; - bool secondary_dvi; - uint32 memory_size; /* memory (in bytes) */ - } ps; - - /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ - uint8 rom_mirror[65536]; - - /* some configuration settings from ~/config/settings/kernel/drivers/skel.settings if exists */ - settings settings; - - struct - { - overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ - int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ - overlay_token myToken; /* scaler is free/in use */ - benaphore lock; /* for creating buffers and aquiring overlay unit routines */ - bool crtc; /* location of overlay unit */ - /* variables needed for virtualscreens (move_overlay()): */ - bool active; /* true is overlay currently in use */ - overlay_window ow; /* current position of overlay output window */ - overlay_buffer ob; /* current inputbuffer in use */ - overlay_view my_ov; /* current corrected view in inputbuffer */ - uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ - uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ - } overlay; - -} shared_info; - -/* Read or write a value in PCI configuration space */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - uint32 offset; /* Offset to read/write */ - uint32 size; /* Number of bytes to transfer */ - uint32 value; /* The value read or written */ -} eng_get_set_pci; - -/* Set some boolean condition (like enabling or disabling interrupts) */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - bool do_it; /* state to set */ -} eng_set_bool_state; - -/* Retrieve the area_id of the kernel/accelerant shared info */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - area_id shared_info_area; /* area_id containing the shared information */ -} eng_get_private_data; - -/* Retrieve the device name. Usefull for when we have a file handle, but want -to know the device name (like when we are cloning the accelerant) */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - char *name; /* The name of the device, less the /dev root */ -} eng_device_name; - -/* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme -used (pre 3.x or 3.x) */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - bool agp_bus;/* indicates if we have access to the AGP busmanager */ - uint8 index; /* device index in list of devices found */ - bool exist; /* we got AGP device info */ - agp_info agpi; /* AGP interface info of a device */ -} eng_nth_agp_info; - -/* Execute an AGP command */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - bool agp_bus;/* indicates if we have access to the AGP busmanager */ - uint32 cmd; /* actual command to execute */ -} eng_cmd_agp; - -/* Read or write a value in ISA I/O space */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - uint16 adress; /* Offset to read/write */ - uint8 size; /* Number of bytes to transfer */ - uint16 data; /* The value read or written */ -} eng_in_out_isa; - -enum { - - _WAIT_FOR_VBLANK = (1 << 0) -}; - -#if defined(__cplusplus) -} -#endif - - -#endif diff --git a/headers/private/graphics/cirrus/macros.h b/headers/private/graphics/cirrus/macros.h deleted file mode 100644 index 06caf0d88c..0000000000 --- a/headers/private/graphics/cirrus/macros.h +++ /dev/null @@ -1,800 +0,0 @@ -/* registers definitions and macros for access to them */ - -/* PCI_config_space */ -#define ENCFG_DEVID 0x00 -#define ENCFG_DEVCTRL 0x04 -#define ENCFG_CLASS 0x08 -#define ENCFG_HEADER 0x0c -#define ENCFG_BASE1REGS 0x10 -#define ENCFG_BASE2FB 0x14 -#define ENCFG_BASE3 0x18 -#define ENCFG_BASE4 0x1c //unknown if used -#define ENCFG_BASE5 0x20 //unknown if used -#define ENCFG_BASE6 0x24 //unknown if used -#define ENCFG_BASE7 0x28 //unknown if used -#define ENCFG_SUBSYSID1 0x2c -#define ENCFG_ROMBASE 0x30 -#define ENCFG_CAPPTR 0x34 -#define ENCFG_CFG_1 0x38 //unknown if used -#define ENCFG_INTERRUPT 0x3c -#define ENCFG_SUBSYSID2 0x40 -#define ENCFG_AGPREF 0x44 -#define ENCFG_AGPSTAT 0x48 -#define ENCFG_AGPCMD 0x4c -#define ENCFG_ROMSHADOW 0x50 -#define ENCFG_VGA 0x54 -#define ENCFG_SCHRATCH 0x58 -#define ENCFG_CFG_10 0x5c -#define ENCFG_CFG_11 0x60 -#define ENCFG_CFG_12 0x64 -#define ENCFG_CFG_13 0x68 //unknown if used -#define ENCFG_CFG_14 0x6c //unknown if used -#define ENCFG_CFG_15 0x70 //unknown if used -#define ENCFG_CFG_16 0x74 //unknown if used -#define ENCFG_CFG_17 0x78 //unknown if used -#define ENCFG_CFG_18 0x7c //unknown if used -#define ENCFG_CFG_19 0x80 //unknown if used -#define ENCFG_CFG_20 0x84 //unknown if used -#define ENCFG_CFG_21 0x88 //unknown if used -#define ENCFG_CFG_22 0x8c //unknown if used -#define ENCFG_CFG_23 0x90 //unknown if used -#define ENCFG_CFG_24 0x94 //unknown if used -#define ENCFG_CFG_25 0x98 //unknown if used -#define ENCFG_CFG_26 0x9c //unknown if used -#define ENCFG_CFG_27 0xa0 //unknown if used -#define ENCFG_CFG_28 0xa4 //unknown if used -#define ENCFG_CFG_29 0xa8 //unknown if used -#define ENCFG_CFG_30 0xac //unknown if used -#define ENCFG_CFG_31 0xb0 //unknown if used -#define ENCFG_CFG_32 0xb4 //unknown if used -#define ENCFG_CFG_33 0xb8 //unknown if used -#define ENCFG_CFG_34 0xbc //unknown if used -#define ENCFG_CFG_35 0xc0 //unknown if used -#define ENCFG_CFG_36 0xc4 //unknown if used -#define ENCFG_CFG_37 0xc8 //unknown if used -#define ENCFG_CFG_38 0xcc //unknown if used -#define ENCFG_CFG_39 0xd0 //unknown if used -#define ENCFG_CFG_40 0xd4 //unknown if used -#define ENCFG_CFG_41 0xd8 //unknown if used -#define ENCFG_CFG_42 0xdc //unknown if used -#define ENCFG_CFG_43 0xe0 //unknown if used -#define ENCFG_CFG_44 0xe4 //unknown if used -#define ENCFG_CFG_45 0xe8 //unknown if used -#define ENCFG_CFG_46 0xec //unknown if used -#define ENCFG_CFG_47 0xf0 //unknown if used -#define ENCFG_CFG_48 0xf4 //unknown if used -#define ENCFG_CFG_49 0xf8 //unknown if used -#define ENCFG_CFG_50 0xfc //unknown if used - -/* used INT registers for vblank */ -#define RG32_MAIN_INTE 0x00000140 -#define RG32_CRTC_INTS 0x00600100 -#define RG32_CRTC_INTE 0x00600140 - -/* ACCeleration registers */ -/* engine initialisation registers */ -#define ENACC_FORMATS 0x00400618 -#define ENACC_OFFSET0 0x00400640 -#define ENACC_OFFSET1 0x00400644 -#define ENACC_OFFSET2 0x00400648 -#define ENACC_OFFSET3 0x0040064c -#define ENACC_OFFSET4 0x00400650 -#define ENACC_OFFSET5 0x00400654 -#define ENACC_BBASE0 0x00400658 -#define ENACC_BBASE1 0x0040065c -#define ENACC_BBASE2 0x00400660 -#define ENACC_BBASE3 0x00400664 -#define ENACC_NV10_BBASE4 0x00400668 -#define ENACC_NV10_BBASE5 0x0040066c -#define ENACC_PITCH0 0x00400670 -#define ENACC_PITCH1 0x00400674 -#define ENACC_PITCH2 0x00400678 -#define ENACC_PITCH3 0x0040067c -#define ENACC_PITCH4 0x00400680 -#define ENACC_BLIMIT0 0x00400684 -#define ENACC_BLIMIT1 0x00400688 -#define ENACC_BLIMIT2 0x0040068c -#define ENACC_BLIMIT3 0x00400690 -#define ENACC_NV10_BLIMIT4 0x00400694 -#define ENACC_NV10_BLIMIT5 0x00400698 -#define ENACC_BPIXEL 0x00400724 -#define ENACC_NV20_OFFSET0 0x00400820 -#define ENACC_NV20_OFFSET1 0x00400824 -#define ENACC_NV20_OFFSET2 0x00400828 -#define ENACC_NV20_OFFSET3 0x0040082c -#define ENACC_STRD_FMT 0x00400830 -#define ENACC_NV20_PITCH0 0x00400850 -#define ENACC_NV20_PITCH1 0x00400854 -#define ENACC_NV20_PITCH2 0x00400858 -#define ENACC_NV20_PITCH3 0x0040085c -#define ENACC_NV20_BLIMIT6 0x00400864 -#define ENACC_NV20_BLIMIT7 0x00400868 -#define ENACC_NV20_BLIMIT8 0x0040086c -#define ENACC_NV20_BLIMIT9 0x00400870 -#define ENACC_NV30_WHAT 0x00400890 - -/* specials */ -#define ENACC_DEBUG0 0x00400080 -#define ENACC_DEBUG1 0x00400084 -#define ENACC_DEBUG2 0x00400088 -#define ENACC_DEBUG3 0x0040008c -#define ENACC_NV10_DEBUG4 0x00400090 -#define ENACC_ACC_INTS 0x00400100 -#define ENACC_ACC_INTE 0x00400140 -#define ENACC_NV10_CTX_CTRL 0x00400144 -#define ENACC_STATUS 0x00400700 -#define ENACC_NV04_SURF_TYP 0x0040070c -#define ENACC_NV10_SURF_TYP 0x00400710 -#define ENACC_NV04_ACC_STAT 0x00400710 -#define ENACC_NV10_ACC_STAT 0x00400714 -#define ENACC_FIFO_EN 0x00400720 -#define ENACC_PAT_SHP 0x00400810 -#define ENACC_NV10_XFMOD0 0x00400f40 -#define ENACC_NV10_XFMOD1 0x00400f44 -#define ENACC_NV10_PIPEADR 0x00400f50 -#define ENACC_NV10_PIPEDAT 0x00400f54 -/* PGRAPH cache registers */ -#define ENACC_CACHE1_1 0x00400160 -#define ENACC_CACHE1_2 0x00400180 -#define ENACC_CACHE1_3 0x004001a0 -#define ENACC_CACHE1_4 0x004001c0 -#define ENACC_CACHE1_5 0x004001e0 -#define ENACC_CACHE2_1 0x00400164 -#define ENACC_CACHE2_2 0x00400184 -#define ENACC_CACHE2_3 0x004001a4 -#define ENACC_CACHE2_4 0x004001c4 -#define ENACC_CACHE2_5 0x004001e4 -#define ENACC_CACHE3_1 0x00400168 -#define ENACC_CACHE3_2 0x00400188 -#define ENACC_CACHE3_3 0x004001a8 -#define ENACC_CACHE3_4 0x004001c8 -#define ENACC_CACHE3_5 0x004001e8 -#define ENACC_CACHE4_1 0x0040016c -#define ENACC_CACHE4_2 0x0040018c -#define ENACC_CACHE4_3 0x004001ac -#define ENACC_CACHE4_4 0x004001cc -#define ENACC_CACHE4_5 0x004001ec -#define ENACC_NV10_CACHE5_1 0x00400170 -#define ENACC_NV04_CTX_CTRL 0x00400170 -#define ENACC_CACHE5_2 0x00400190 -#define ENACC_CACHE5_3 0x004001b0 -#define ENACC_CACHE5_4 0x004001d0 -#define ENACC_CACHE5_5 0x004001f0 -#define ENACC_NV10_CACHE6_1 0x00400174 -#define ENACC_CACHE6_2 0x00400194 -#define ENACC_CACHE6_3 0x004001b4 -#define ENACC_CACHE6_4 0x004001d4 -#define ENACC_CACHE6_5 0x004001f4 -#define ENACC_NV10_CACHE7_1 0x00400178 -#define ENACC_CACHE7_2 0x00400198 -#define ENACC_CACHE7_3 0x004001b8 -#define ENACC_CACHE7_4 0x004001d8 -#define ENACC_CACHE7_5 0x004001f8 -#define ENACC_NV10_CACHE8_1 0x0040017c -#define ENACC_CACHE8_2 0x0040019c -#define ENACC_CACHE8_3 0x004001bc -#define ENACC_CACHE8_4 0x004001dc -#define ENACC_CACHE8_5 0x004001fc -#define ENACC_NV10_CTX_SW1 0x0040014c -#define ENACC_NV10_CTX_SW2 0x00400150 -#define ENACC_NV10_CTX_SW3 0x00400154 -#define ENACC_NV10_CTX_SW4 0x00400158 -#define ENACC_NV10_CTX_SW5 0x0040015c -/* engine tile registers src */ -#define ENACC_NV20_FBWHAT0 0x00100200 -#define ENACC_NV20_FBWHAT1 0x00100204 -#define ENACC_NV10_FBTIL0AD 0x00100240 -#define ENACC_NV10_FBTIL0ED 0x00100244 -#define ENACC_NV10_FBTIL0PT 0x00100248 -#define ENACC_NV10_FBTIL0ST 0x0010024c -#define ENACC_NV10_FBTIL1AD 0x00100250 -#define ENACC_NV10_FBTIL1ED 0x00100254 -#define ENACC_NV10_FBTIL1PT 0x00100258 -#define ENACC_NV10_FBTIL1ST 0x0010025c -#define ENACC_NV10_FBTIL2AD 0x00100260 -#define ENACC_NV10_FBTIL2ED 0x00100264 -#define ENACC_NV10_FBTIL2PT 0x00100268 -#define ENACC_NV10_FBTIL2ST 0x0010026c -#define ENACC_NV10_FBTIL3AD 0x00100270 -#define ENACC_NV10_FBTIL3ED 0x00100274 -#define ENACC_NV10_FBTIL3PT 0x00100278 -#define ENACC_NV10_FBTIL3ST 0x0010027c -#define ENACC_NV10_FBTIL4AD 0x00100280 -#define ENACC_NV10_FBTIL4ED 0x00100284 -#define ENACC_NV10_FBTIL4PT 0x00100288 -#define ENACC_NV10_FBTIL4ST 0x0010028c -#define ENACC_NV10_FBTIL5AD 0x00100290 -#define ENACC_NV10_FBTIL5ED 0x00100294 -#define ENACC_NV10_FBTIL5PT 0x00100298 -#define ENACC_NV10_FBTIL5ST 0x0010029c -#define ENACC_NV10_FBTIL6AD 0x001002a0 -#define ENACC_NV10_FBTIL6ED 0x001002a4 -#define ENACC_NV10_FBTIL6PT 0x001002a8 -#define ENACC_NV10_FBTIL6ST 0x001002ac -#define ENACC_NV10_FBTIL7AD 0x001002b0 -#define ENACC_NV10_FBTIL7ED 0x001002b4 -#define ENACC_NV10_FBTIL7PT 0x001002b8 -#define ENACC_NV10_FBTIL7ST 0x001002bc -/* engine tile registers dst */ -#define ENACC_NV20_WHAT0 0x004009a4 -#define ENACC_NV20_WHAT1 0x004009a8 -#define ENACC_NV10_TIL0AD 0x00400b00 -#define ENACC_NV10_TIL0ED 0x00400b04 -#define ENACC_NV10_TIL0PT 0x00400b08 -#define ENACC_NV10_TIL0ST 0x00400b0c -#define ENACC_NV10_TIL1AD 0x00400b10 -#define ENACC_NV10_TIL1ED 0x00400b14 -#define ENACC_NV10_TIL1PT 0x00400b18 -#define ENACC_NV10_TIL1ST 0x00400b1c -#define ENACC_NV10_TIL2AD 0x00400b20 -#define ENACC_NV10_TIL2ED 0x00400b24 -#define ENACC_NV10_TIL2PT 0x00400b28 -#define ENACC_NV10_TIL2ST 0x00400b2c -#define ENACC_NV10_TIL3AD 0x00400b30 -#define ENACC_NV10_TIL3ED 0x00400b34 -#define ENACC_NV10_TIL3PT 0x00400b38 -#define ENACC_NV10_TIL3ST 0x00400b3c -#define ENACC_NV10_TIL4AD 0x00400b40 -#define ENACC_NV10_TIL4ED 0x00400b44 -#define ENACC_NV10_TIL4PT 0x00400b48 -#define ENACC_NV10_TIL4ST 0x00400b4c -#define ENACC_NV10_TIL5AD 0x00400b50 -#define ENACC_NV10_TIL5ED 0x00400b54 -#define ENACC_NV10_TIL5PT 0x00400b58 -#define ENACC_NV10_TIL5ST 0x00400b5c -#define ENACC_NV10_TIL6AD 0x00400b60 -#define ENACC_NV10_TIL6ED 0x00400b64 -#define ENACC_NV10_TIL6PT 0x00400b68 -#define ENACC_NV10_TIL6ST 0x00400b6c -#define ENACC_NV10_TIL7AD 0x00400b70 -#define ENACC_NV10_TIL7ED 0x00400b74 -#define ENACC_NV10_TIL7PT 0x00400b78 -#define ENACC_NV10_TIL7ST 0x00400b7c -/* cache setup registers */ -#define ENACC_PF_INTSTAT 0x00002100 -#define ENACC_PF_INTEN 0x00002140 -#define ENACC_PF_RAMHT 0x00002210 -#define ENACC_PF_RAMFC 0x00002214 -#define ENACC_PF_RAMRO 0x00002218 -#define ENACC_PF_CACHES 0x00002500 -#define ENACC_PF_SIZE 0x0000250c -#define ENACC_PF_CACH0_PSH0 0x00003000 -#define ENACC_PF_CACH0_PUL0 0x00003050 -#define ENACC_PF_CACH0_PUL1 0x00003054 -#define ENACC_PF_CACH1_PSH0 0x00003200 -#define ENACC_PF_CACH1_PSH1 0x00003204 -#define ENACC_PF_CACH1_DMAI 0x0000322c -#define ENACC_PF_CACH1_PUL0 0x00003250 -#define ENACC_PF_CACH1_PUL1 0x00003254 -#define ENACC_PF_CACH1_HASH 0x00003258 -/* Ptimer registers */ -#define ENACC_PT_INTSTAT 0x00009100 -#define ENACC_PT_INTEN 0x00009140 -#define ENACC_PT_NUMERATOR 0x00009200 -#define ENACC_PT_DENOMINATR 0x00009210 -/* used PRAMIN registers */ -#define ENACC_PR_CTX0_R 0x00711400 -#define ENACC_PR_CTX1_R 0x00711404 -#define ENACC_PR_CTX2_R 0x00711408 -#define ENACC_PR_CTX3_R 0x0071140c -#define ENACC_PR_CTX0_0 0x00711420 -#define ENACC_PR_CTX1_0 0x00711424 -#define ENACC_PR_CTX2_0 0x00711428 -#define ENACC_PR_CTX3_0 0x0071142c -#define ENACC_PR_CTX0_1 0x00711430 -#define ENACC_PR_CTX1_1 0x00711434 -#define ENACC_PR_CTX2_1 0x00711438 -#define ENACC_PR_CTX3_1 0x0071143c -#define ENACC_PR_CTX0_2 0x00711440 -#define ENACC_PR_CTX1_2 0x00711444 -#define ENACC_PR_CTX2_2 0x00711448 -#define ENACC_PR_CTX3_2 0x0071144c -#define ENACC_PR_CTX0_3 0x00711450 -#define ENACC_PR_CTX1_3 0x00711454 -#define ENACC_PR_CTX2_3 0x00711458 -#define ENACC_PR_CTX3_3 0x0071145c -#define ENACC_PR_CTX0_4 0x00711460 -#define ENACC_PR_CTX1_4 0x00711464 -#define ENACC_PR_CTX2_4 0x00711468 -#define ENACC_PR_CTX3_4 0x0071146c -#define ENACC_PR_CTX0_5 0x00711470 -#define ENACC_PR_CTX1_5 0x00711474 -#define ENACC_PR_CTX2_5 0x00711478 -#define ENACC_PR_CTX3_5 0x0071147c -#define ENACC_PR_CTX0_6 0x00711480 -#define ENACC_PR_CTX1_6 0x00711484 -#define ENACC_PR_CTX2_6 0x00711488 -#define ENACC_PR_CTX3_6 0x0071148c -#define ENACC_PR_CTX0_7 0x00711490 -#define ENACC_PR_CTX1_7 0x00711494 -#define ENACC_PR_CTX2_7 0x00711498 -#define ENACC_PR_CTX3_7 0x0071149c -#define ENACC_PR_CTX0_8 0x007114a0 -#define ENACC_PR_CTX1_8 0x007114a4 -#define ENACC_PR_CTX2_8 0x007114a8 -#define ENACC_PR_CTX3_8 0x007114ac -#define ENACC_PR_CTX0_9 0x007114b0 -#define ENACC_PR_CTX1_9 0x007114b4 -#define ENACC_PR_CTX2_9 0x007114b8 -#define ENACC_PR_CTX3_9 0x007114bc -#define ENACC_PR_CTX0_A 0x007114c0 -#define ENACC_PR_CTX1_A 0x007114c4 /* not used */ -#define ENACC_PR_CTX2_A 0x007114c8 -#define ENACC_PR_CTX3_A 0x007114cc -#define ENACC_PR_CTX0_B 0x007114d0 -#define ENACC_PR_CTX1_B 0x007114d4 -#define ENACC_PR_CTX2_B 0x007114d8 -#define ENACC_PR_CTX3_B 0x007114dc -#define ENACC_PR_CTX0_C 0x007114e0 -#define ENACC_PR_CTX1_C 0x007114e4 -#define ENACC_PR_CTX2_C 0x007114e8 -#define ENACC_PR_CTX3_C 0x007114ec -#define ENACC_PR_CTX0_D 0x007114f0 -#define ENACC_PR_CTX1_D 0x007114f4 -#define ENACC_PR_CTX2_D 0x007114f8 -#define ENACC_PR_CTX3_D 0x007114fc -#define ENACC_PR_CTX0_E 0x00711500 -#define ENACC_PR_CTX1_E 0x00711504 -#define ENACC_PR_CTX2_E 0x00711508 -#define ENACC_PR_CTX3_E 0x0071150c -/* used RAMHT registers (hash-table(?)) */ -#define ENACC_HT_HANDL_00 0x00710000 -#define ENACC_HT_VALUE_00 0x00710004 -#define ENACC_HT_HANDL_01 0x00710008 -#define ENACC_HT_VALUE_01 0x0071000c -#define ENACC_HT_HANDL_02 0x00710010 -#define ENACC_HT_VALUE_02 0x00710014 -#define ENACC_HT_HANDL_03 0x00710018 -#define ENACC_HT_VALUE_03 0x0071001c -#define ENACC_HT_HANDL_04 0x00710020 -#define ENACC_HT_VALUE_04 0x00710024 -#define ENACC_HT_HANDL_05 0x00710028 -#define ENACC_HT_VALUE_05 0x0071002c -#define ENACC_HT_HANDL_06 0x00710030 -#define ENACC_HT_VALUE_06 0x00710034 -#define ENACC_HT_HANDL_10 0x00710080 -#define ENACC_HT_VALUE_10 0x00710084 -#define ENACC_HT_HANDL_11 0x00710088 -#define ENACC_HT_VALUE_11 0x0071008c -#define ENACC_HT_HANDL_12 0x00710090 -#define ENACC_HT_VALUE_12 0x00710094 -#define ENACC_HT_HANDL_13 0x00710098 -#define ENACC_HT_VALUE_13 0x0071009c -#define ENACC_HT_HANDL_14 0x007100a0 -#define ENACC_HT_VALUE_14 0x007100a4 -#define ENACC_HT_HANDL_15 0x007100a8 -#define ENACC_HT_VALUE_15 0x007100ac -#define ENACC_HT_HANDL_16 0x007100b0 -#define ENACC_HT_VALUE_16 0x007100b4 -#define ENACC_HT_HANDL_17 0x007100b8 -#define ENACC_HT_VALUE_17 0x007100bc - -/* acc engine fifo setup registers (for function_register 'mappings') */ -#define ENACC_FIFO_00800000 0x00800000 -#define ENACC_FIFO_00802000 0x00802000 -#define ENACC_FIFO_00804000 0x00804000 -#define ENACC_FIFO_00806000 0x00806000 -#define ENACC_FIFO_00808000 0x00808000 -#define ENACC_FIFO_0080a000 0x0080a000 -#define ENACC_FIFO_0080c000 0x0080c000 -#define ENACC_FIFO_0080e000 0x0080e000 - -/* ROP3 registers (Raster OPeration) */ -#define RG16_ROP_FIFOFREE 0x00800010 /* little endian */ -#define ENACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ - -/* clip registers */ -#define RG16_CLP_FIFOFREE 0x00802010 /* little endian */ -#define ENACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ -#define ENACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ - -/* pattern registers */ -#define RG16_PAT_FIFOFREE 0x00804010 /* little endian */ -#define ENACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ -#define ENACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ -#define ENACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ -#define ENACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ -#define ENACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ - -/* blit registers */ -#define RG16_BLT_FIFOFREE 0x00808010 /* little endian */ -#define ENACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ -#define ENACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ -#define ENACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ - -/* used bitmap registers */ -#define RG16_BMP_FIFOFREE 0x0080a010 /* little endian */ -#define ENACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ -#define ENACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ -#define ENACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ - -/* PCI direct registers */ -#define RG32_PWRUPCTRL 0x00000200 -#define RG32_DUALHEAD_CTRL 0x000010f0//verify!!! -#define RG8_MISCW 0x000c03c2 -#define RG8_MISCR 0x000c03cc -#define RG8_VSE2 0x000c03c3 -#define RG8_SEQIND 0x000c03c4 -#define RG16_SEQIND 0x000c03c4 -#define RG8_SEQDAT 0x000c03c5 -#define RG8_GRPHIND 0x000c03ce -#define RG16_GRPHIND 0x000c03ce -#define RG8_GRPHDAT 0x000c03cf - -/* bootstrap info registers */ -#define RG32_NV4STRAPINFO 0x00100000 -#define RG32_PFB_CONFIG_0 0x00100200 -#define RG32_PFB_CONFIG_1 0x00100204 -#define RG32_NV10STRAPINFO 0x0010020c -#define RG32_FB_MRS1 0x001002c0 -#define RG32_FB_MRS2 0x001002c8 -#define RG32_NVSTRAPINFO2 0x00101000 - -/* registers needed for 'coldstart' */ -#define RG32_PFB_DEBUG_0 0x00100080 -#define RG32_PFB_REFCTRL 0x00100210 -#define RG32_COREPLL 0x00680500 -#define RG32_MEMPLL 0x00680504 -#define RG32_PLL_CTRL 0x00680510 -#define RG32_COREPLL2 0x00680570 /* NV31, NV36 only */ -#define RG32_MEMPLL2 0x00680574 /* NV31, NV36 only */ -#define RG32_CONFIG 0x00600804 - -/* primary head */ -#define RG8_ATTRINDW 0x006013c0 -#define RG8_ATTRDATW 0x006013c0 -#define RG8_ATTRDATR 0x006013c1 -#define RG8_CRTCIND 0x006013d4 -#define RG16_CRTCIND 0x006013d4 -#define RG8_CRTCDAT 0x006013d5 -#define RG8_INSTAT1 0x006013da -#define RG32_NV10FBSTADD32 0x00600800 -#define RG32_RASTER 0x00600808 -#define RG32_NV10CURADD32 0x0060080c -#define RG32_CURCONF 0x00600810 -#define RG32_PANEL_PWR 0x0060081c -#define RG32_FUNCSEL 0x00600860 - -/* secondary head */ -#define RG8_ATTR2INDW 0x006033c0 -#define RG8_ATTR2DATW 0x006033c0 -#define RG8_ATTR2DATR 0x006033c1 -#define RG8_CRTC2IND 0x006033d4 -#define RG16_CRTC2IND 0x006033d4 -#define RG8_CRTC2DAT 0x006033d5 -#define RG8_2INSTAT1 0x006033da//verify!!! -#define RG32_NV10FB2STADD32 0x00602800 -#define RG32_RASTER2 0x00602808 -#define RG32_NV10CUR2ADD32 0x0060280c -#define RG32_2CURCONF 0x00602810 -#define RG32_2PANEL_PWR 0x0060281c//verify!!! -#define RG32_2FUNCSEL 0x00602860 - -/* DAC direct registers (standard VGA palette RAM registers) */ -/* primary head */ -#define RG8_PALMASK 0x006813c6 -#define RG8_PALINDR 0x006813c7 -#define RG8_PALINDW 0x006813c8 -#define RG8_PALDATA 0x006813c9 -/* secondary head */ -#define RG8_PAL2MASK 0x006833c6 -#define RG8_PAL2INDR 0x006833c7 -#define RG8_PAL2INDW 0x006833c8 -#define RG8_PAL2DATA 0x006833c9 - -/* PCI direct DAC registers (32bit) */ -/* primary head */ -#define ENDAC_CURPOS 0x00680300 -#define ENDAC_PIXPLLC 0x00680508 -#define ENDAC_PLLSEL 0x0068050c -#define ENDAC_OUTPUT 0x0068052c -#define ENDAC_PIXPLLC2 0x00680578 -#define ENDAC_GENCTRL 0x00680600 -#define ENDAC_TSTCTRL 0x00680608 -#define ENDAC_TSTDATA 0x00680610 -#define ENDAC_TV_SETUP 0x00680700 -/* (flatpanel registers: confirmed for TNT2 and up) */ -#define ENDAC_FP_VDISPEND 0x00680800 -#define ENDAC_FP_VTOTAL 0x00680804 -#define ENDAC_FP_VCRTC 0x00680808 -#define ENDAC_FP_VSYNC_S 0x0068080c -#define ENDAC_FP_VSYNC_E 0x00680810 -#define ENDAC_FP_VVALID_S 0x00680814 -#define ENDAC_FP_VVALID_E 0x00680818 -#define ENDAC_FP_HDISPEND 0x00680820 -#define ENDAC_FP_HTOTAL 0x00680824 -#define ENDAC_FP_HCRTC 0x00680828 -#define ENDAC_FP_HSYNC_S 0x0068082c -#define ENDAC_FP_HSYNC_E 0x00680830 -#define ENDAC_FP_HVALID_S 0x00680834 -#define ENDAC_FP_HVALID_E 0x00680838 -#define ENDAC_FP_CHKSUM 0x00680840 -#define ENDAC_FP_TST_CTRL 0x00680844 -#define ENDAC_FP_TG_CTRL 0x00680848 -#define ENDAC_FP_DEBUG0 0x00680880 -#define ENDAC_FP_DEBUG1 0x00680884 -#define ENDAC_FP_DEBUG2 0x00680888 -#define ENDAC_FP_DEBUG3 0x0068088c -/* secondary head */ -#define ENDAC2_CURPOS 0x00682300 -#define ENDAC2_PIXPLLC 0x00680520 -#define ENDAC2_OUTPUT 0x0068252c -#define ENDAC2_PIXPLLC2 0x0068057c -#define ENDAC2_GENCTRL 0x00682600 -#define ENDAC2_TSTCTRL 0x00682608 -#define ENDAC2_TV_SETUP 0x00682700 //verify!!! -/* (flatpanel registers) */ -#define ENDAC2_FP_VDISPEND 0x00682800 -#define ENDAC2_FP_VTOTAL 0x00682804 -#define ENDAC2_FP_VCRTC 0x00682808 -#define ENDAC2_FP_VSYNC_S 0x0068280c -#define ENDAC2_FP_VSYNC_E 0x00682810 -#define ENDAC2_FP_VVALID_S 0x00682814 -#define ENDAC2_FP_VVALID_E 0x00682818 -#define ENDAC2_FP_HDISPEND 0x00682820 -#define ENDAC2_FP_HTOTAL 0x00682824 -#define ENDAC2_FP_HCRTC 0x00682828 -#define ENDAC2_FP_HSYNC_S 0x0068282c -#define ENDAC2_FP_HSYNC_E 0x00682830 -#define ENDAC2_FP_HVALID_S 0x00682834 -#define ENDAC2_FP_HVALID_E 0x00682838 -#define ENDAC2_FP_CHKSUM 0x00682840 -#define ENDAC2_FP_TST_CTRL 0x00682844 -#define ENDAC2_FP_TG_CTRL 0x00682848 -#define ENDAC2_FP_DEBUG0 0x00682880 -#define ENDAC2_FP_DEBUG1 0x00682884 -#define ENDAC2_FP_DEBUG2 0x00682888 -#define ENDAC2_FP_DEBUG3 0x0068288c - -/* Nvidia CRTC indexed registers */ -/* VGA standard registers: */ -#define ENCRTCX_HTOTAL 0x00 -#define ENCRTCX_HDISPE 0x01 -#define ENCRTCX_HBLANKS 0x02 -#define ENCRTCX_HBLANKE 0x03 -#define ENCRTCX_HSYNCS 0x04 -#define ENCRTCX_HSYNCE 0x05 -#define ENCRTCX_VTOTAL 0x06 -#define ENCRTCX_OVERFLOW 0x07 -#define ENCRTCX_PRROWSCN 0x08 -#define ENCRTCX_MAXSCLIN 0x09 -#define ENCRTCX_VGACURCTRL 0x0a -#define ENCRTCX_FBSTADDH 0x0c -#define ENCRTCX_FBSTADDL 0x0d -#define ENCRTCX_VSYNCS 0x10 -#define ENCRTCX_VSYNCE 0x11 -#define ENCRTCX_VDISPE 0x12 -#define ENCRTCX_PITCHL 0x13 -#define ENCRTCX_VBLANKS 0x15 -#define ENCRTCX_VBLANKE 0x16 -#define ENCRTCX_MODECTL 0x17 -#define ENCRTCX_LINECOMP 0x18 -/* Nvidia specific registers: */ -#define ENCRTCX_REPAINT0 0x19 -#define ENCRTCX_REPAINT1 0x1a -#define ENCRTCX_FIFO 0x1b -#define ENCRTCX_LOCK 0x1f -#define ENCRTCX_FIFO_LWM 0x20 -#define ENCRTCX_BUFFER 0x21 -#define ENCRTCX_LSR 0x25 -#define ENCRTCX_PIXEL 0x28 -#define ENCRTCX_HEB 0x2d -#define ENCRTCX_CURCTL2 0x2f -#define ENCRTCX_CURCTL1 0x30 -#define ENCRTCX_CURCTL0 0x31 -#define ENCRTCX_LCD 0x33 -#define ENCRTCX_RMA 0x38 -#define ENCRTCX_INTERLACE 0x39 -#define ENCRTCX_TREG 0x3d -#define ENCRTCX_EXTRA 0x41 -#define ENCRTCX_OWNER 0x44 -#define ENCRTCX_FP_HTIMING 0x53 -#define ENCRTCX_FP_VTIMING 0x54 -#define ENCRTCX_0x59 0x59 -#define ENCRTCX_0x9f 0x9f - -/* Nvidia ATTRIBUTE indexed registers */ -/* VGA standard registers: */ -#define ENATBX_MODECTL 0x10 -#define ENATBX_OSCANCOLOR 0x11 -#define ENATBX_COLPLANE_EN 0x12 -#define ENATBX_HORPIXPAN 0x13 -#define ENATBX_COLSEL 0x14 - -/* Nvidia SEQUENCER indexed registers */ -/* VGA standard registers: */ -#define ENSEQX_RESET 0x00 -#define ENSEQX_CLKMODE 0x01 -#define ENSEQX_MEMMODE 0x04 - -/* Nvidia GRAPHICS indexed registers */ -/* VGA standard registers: */ -#define ENGRPHX_ENSETRESET 0x01 -#define ENGRPHX_DATAROTATE 0x03 -#define ENGRPHX_READMAPSEL 0x04 -#define ENGRPHX_MODE 0x05 -#define ENGRPHX_MISC 0x06 -#define ENGRPHX_BITMASK 0x08 - -/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ -#define ENBES_NV04_INTE 0x00680140 -#define ENBES_NV04_ISCALVH 0x00680200 -#define ENBES_NV04_CTRL_V 0x00680204 -#define ENBES_NV04_CTRL_H 0x00680208 -#define ENBES_NV04_OE_STATE 0x00680224 -#define ENBES_NV04_SU_STATE 0x00680228 -#define ENBES_NV04_RM_STATE 0x0068022c -#define ENBES_NV04_DSTREF 0x00680230 -#define ENBES_NV04_DSTSIZE 0x00680234 -#define ENBES_NV04_FIFOTHRS 0x00680238 -#define ENBES_NV04_FIFOBURL 0x0068023c -#define ENBES_NV04_COLKEY 0x00680240 -#define ENBES_NV04_GENCTRL 0x00680244 -#define ENBES_NV04_RED_AMP 0x00680280 -#define ENBES_NV04_GRN_AMP 0x00680284 -#define ENBES_NV04_BLU_AMP 0x00680288 -#define ENBES_NV04_SAT 0x0068028c -/* buffer 0 */ -#define ENBES_NV04_0BUFADR 0x0068020c -#define ENBES_NV04_0SRCPTCH 0x00680214 -#define ENBES_NV04_0OFFSET 0x0068021c -/* buffer 1 */ -#define ENBES_NV04_1BUFADR 0x00680210 -#define ENBES_NV04_1SRCPTCH 0x00680218 -#define ENBES_NV04_1OFFSET 0x00680220 - -/* Nvidia BES (Back End Scaler) registers (>= NV10) */ -#define ENBES_NV10_INTE 0x00008140 -#define ENBES_NV10_BUFSEL 0x00008700 -#define ENBES_NV10_GENCTRL 0x00008704 -#define ENBES_NV10_COLKEY 0x00008b00 -/* buffer 0 */ -#define ENBES_NV10_0BUFADR 0x00008900 -#define ENBES_NV10_0MEMMASK 0x00008908 -#define ENBES_NV10_0BRICON 0x00008910 -#define ENBES_NV10_0SAT 0x00008918 -#define ENBES_NV10_0OFFSET 0x00008920 -#define ENBES_NV10_0SRCSIZE 0x00008928 -#define ENBES_NV10_0SRCREF 0x00008930 -#define ENBES_NV10_0ISCALH 0x00008938 -#define ENBES_NV10_0ISCALV 0x00008940 -#define ENBES_NV10_0DSTREF 0x00008948 -#define ENBES_NV10_0DSTSIZE 0x00008950 -#define ENBES_NV10_0SRCPTCH 0x00008958 -/* buffer 1 */ -#define ENBES_NV10_1BUFADR 0x00008904 -#define ENBES_NV10_1MEMMASK 0x0000890c -#define ENBES_NV10_1BRICON 0x00008914 -#define ENBES_NV10_1SAT 0x0000891c -#define ENBES_NV10_1OFFSET 0x00008924 -#define ENBES_NV10_1SRCSIZE 0x0000892c -#define ENBES_NV10_1SRCREF 0x00008934 -#define ENBES_NV10_1ISCALH 0x0000893c -#define ENBES_NV10_1ISCALV 0x00008944 -#define ENBES_NV10_1DSTREF 0x0000894c -#define ENBES_NV10_1DSTSIZE 0x00008954 -#define ENBES_NV10_1SRCPTCH 0x0000895c -/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ -#define ENBES_DEC_GENCTRL 0x00001588 - -//old: -/*MAVEN registers (<= G400) */ -#define ENMAV_PGM 0x3E -#define ENMAV_PIXPLLM 0x80 -#define ENMAV_PIXPLLN 0x81 -#define ENMAV_PIXPLLP 0x82 -#define ENMAV_GAMMA1 0x83 -#define ENMAV_GAMMA2 0x84 -#define ENMAV_GAMMA3 0x85 -#define ENMAV_GAMMA4 0x86 -#define ENMAV_GAMMA5 0x87 -#define ENMAV_GAMMA6 0x88 -#define ENMAV_GAMMA7 0x89 -#define ENMAV_GAMMA8 0x8A -#define ENMAV_GAMMA9 0x8B -#define ENMAV_MONSET 0x8C -#define ENMAV_TEST 0x8D -#define ENMAV_WREG_0X8E_L 0x8E -#define ENMAV_WREG_0X8E_H 0x8F -#define ENMAV_HSCALETV 0x90 -#define ENMAV_TSCALETVL 0x91 -#define ENMAV_TSCALETVH 0x92 -#define ENMAV_FFILTER 0x93 -#define ENMAV_MONEN 0x94 -#define ENMAV_RESYNC 0x95 -#define ENMAV_LASTLINEL 0x96 -#define ENMAV_LASTLINEH 0x97 -#define ENMAV_WREG_0X98_L 0x98 -#define ENMAV_WREG_0X98_H 0x99 -#define ENMAV_HSYNCLENL 0x9A -#define ENMAV_HSYNCLENH 0x9B -#define ENMAV_HSYNCSTRL 0x9C -#define ENMAV_HSYNCSTRH 0x9D -#define ENMAV_HDISPLAYL 0x9E -#define ENMAV_HDISPLAYH 0x9F -#define ENMAV_HTOTALL 0xA0 -#define ENMAV_HTOTALH 0xA1 -#define ENMAV_VSYNCLENL 0xA2 -#define ENMAV_VSYNCLENH 0xA3 -#define ENMAV_VSYNCSTRL 0xA4 -#define ENMAV_VSYNCSTRH 0xA5 -#define ENMAV_VDISPLAYL 0xA6 -#define ENMAV_VDISPLAYH 0xA7 -#define ENMAV_VTOTALL 0xA8 -#define ENMAV_VTOTALH 0xA9 -#define ENMAV_HVIDRSTL 0xAA -#define ENMAV_HVIDRSTH 0xAB -#define ENMAV_VVIDRSTL 0xAC -#define ENMAV_VVIDRSTH 0xAD -#define ENMAV_VSOMETHINGL 0xAE -#define ENMAV_VSOMETHINGH 0xAF -#define ENMAV_OUTMODE 0xB0 -#define ENMAV_LOCK 0xB3 -#define ENMAV_LUMA 0xB9 -#define ENMAV_VDISPLAYTV 0xBE -#define ENMAV_STABLE 0xBF -#define ENMAV_HDISPLAYTV 0xC2 -#define ENMAV_BREG_0XC6 0xC6 -//end old. - -/* Macros for convenient accesses to the NV chips */ -#define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] -#define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] -#define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2] - -/* read and write to PCI config space */ -#define CFGR(A) (eng_pci_access.offset=ENCFG_##A, ioctl(fd,ENG_GET_PCI, &eng_pci_access,sizeof(eng_pci_access)), eng_pci_access.value) -#define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) - -/* read and write from ISA I/O space */ -#define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) -#define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) -#define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data) -#define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data) - -/* read and write from the dac registers */ -#define DACR(A) (ENG_RG32(ENDAC_##A)) -#define DACW(A,B) (ENG_RG32(ENDAC_##A)=B) - -/* read and write from the secondary dac registers */ -#define DAC2R(A) (ENG_RG32(ENDAC2_##A)) -#define DAC2W(A,B) (ENG_RG32(ENDAC2_##A)=B) - -/* read and write from the backend scaler registers */ -#define BESR(A) (ENG_RG32(ENBES_##A)) -#define BESW(A,B) (ENG_RG32(ENBES_##A)=B) - -/* read and write from CRTC indexed registers */ -#define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) -#define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) - -/* read and write from second CRTC indexed registers */ -#define CRTC2W(A,B)(ENG_REG16(RG16_CRTC2IND) = ((ENCRTCX_##A) | ((B) << 8))) -#define CRTC2R(A) (ENG_REG8(RG8_CRTC2IND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTC2DAT)) - -/* read and write from ATTRIBUTE indexed registers */ -#define ATBW(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATW) = (B)) -#define ATBR(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATR)) - -/* read and write from ATTRIBUTE indexed registers */ -#define ATB2W(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATW) = (B)) -#define ATB2R(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATR)) - -/* read and write from SEQUENCER indexed registers */ -#define SEQW(A,B)(ENG_REG16(RG16_SEQIND) = ((ENSEQX_##A) | ((B) << 8))) -#define SEQR(A) (ENG_REG8(RG8_SEQIND) = (ENSEQX_##A), ENG_REG8(RG8_SEQDAT)) - -/* read and write from PCI GRAPHICS indexed registers */ -#define GRPHW(A,B)(ENG_REG16(RG16_GRPHIND) = ((ENGRPHX_##A) | ((B) << 8))) -#define GRPHR(A) (ENG_REG8(RG8_GRPHIND) = (ENGRPHX_##A), ENG_REG8(RG8_GRPHDAT)) - -/* read and write from the acceleration engine registers */ -#define ACCR(A) (ENG_RG32(ENACC_##A)) -#define ACCW(A,B) (ENG_RG32(ENACC_##A)=B) - -//old: -/* read and write from maven (<= G400) */ -#define MAVR(A) (i2c_maven_read (ENMAV_##A )) -#define MAVW(A,B) (i2c_maven_write(ENMAV_##A ,B)) -#define MAVRW(A) (i2c_maven_read (ENMAV_##A )|(i2c_maven_read(ENMAV_##A +1)<<8)) -#define MAVWW(A,B) (i2c_maven_write(ENMAV_##A ,B &0xFF),i2c_maven_write(ENMAV_##A +1,B >>8)) diff --git a/src/add-ons/kernel/drivers/graphics/cirrus/Jamfile b/src/add-ons/kernel/drivers/graphics/cirrus/Jamfile deleted file mode 100644 index 56876b67b2..0000000000 --- a/src/add-ons/kernel/drivers/graphics/cirrus/Jamfile +++ /dev/null @@ -1,21 +0,0 @@ -SubDir HAIKU_TOP src add-ons kernel drivers graphics cirrus ; - -SetSubDirSupportedPlatformsBeOSCompatible ; - -UsePrivateHeaders graphics ; -UsePrivateHeaders [ FDirName graphics cirrus ] ; - -KernelAddon cirrus.driver : - driver.c -; - -Package haiku-cirrus-cvs : - README.html UPDATE.html ; -Package haiku-cirrus-cvs : - skel.driver : - boot home config add-ons kernel drivers bin ; -PackageDriverSymLink haiku-cirrus-cvs : graphics cirrus.driver ; -Package haiku-cirrus-cvs : - cirrus.settings : - boot home config settings kernel drivers ; - diff --git a/src/add-ons/kernel/drivers/graphics/cirrus/README.html b/src/add-ons/kernel/drivers/graphics/cirrus/README.html deleted file mode 100644 index a50f6d1a84..0000000000 --- a/src/add-ons/kernel/drivers/graphics/cirrus/README.html +++ /dev/null @@ -1,150 +0,0 @@ - - - - - Readme for Haiku skeleton graphics driver - - -

Haiku skeleton graphics driver



-
-

NOTE PLEASE:
-You use this software at your own risk! Although I don't expect it to damage your PC, videocard or Monitor, I cannot guarantee this!

-
-

Supported cards (as far as is known):

-
    -
  • None. -
-
-
-

Features:

-
    -
  • None. -
-Known limitations: -
    -
  • Everything you can think of. -
-
-
-

Installation:

-
-In contrary to what I have said before you don't need to de-install official Be drivers for this driver to work correctly. This driver will install in the user part of the BeOS, so not in the system part where the official drivers are.
-BeOS first checks (during boot) if there are 'user-addons' that should be loaded for a device. If not, it loads it's own drivers (if any). You can select which driver should be loaded by hitting the spacebar as soon as the BeOS 'icons' screen appears. If you select disable user addons the system will load it's own drivers. If you don't do anything, the system will load the Haiku skeleton graphics driver.
-
-Note: This might turn out to be handy if you run into trouble upon testing the driver, or if you are 'tweaking' the skel.settings file...
-

-actual INSTALLATION:
-
-Doubleclick on the install.sh file and follow the instructions. You have to reboot in order to load the driver. Make sure you read the Settings information below before you do that...
-
-
-alternate INSTALLATION method:
-
-Unzip the zip file that contains the driver to the root folder. Now reboot and you should be using the new driver.
-
-
-DE-INSTALLATION:
-
-Currently there's no uninstall script included. Just do it manually:
-
-Delete the skel.accelerant file in home/config/add-ons/accelerants/
-Delete the skel.driver file in home/config/add-ons/kernel/drivers/bin/
-Delete the skel.settings file in home/config/settings/kernel/drivers/
-Delete the skel.driver shortcut in home/config/add-ons/kernel/drivers/dev/graphics/ which pointed to the file skel.driver.
-
-You have to reboot in order to apply the original configuration.
-
-
-
-

Settings:


-Please read this information carefully *before* installing and using the Haiku skeleton graphics driver. It might spare you some trouble afterwards..
-

The driver uses a file named skel.settings to determine how to use your card. After installation this file will be located at home/config/settings/kernel/drivers/. How you should setup this file depends on what you want to do with the driver. While it has a 'failsave' default configuration, you might be able to do better than that... Anyway, read the nifty details below.
-
-Note: The driver only reads this file during it's initialisation. This means that you have to reboot in order to let changes take effect.
-
-
-
-skel.settings driver configuration:
-

    -
  • usebios:
    -The name of this item may be somewhat misleading, it might be changed in the future. It actually tells the driver if it should coldstart the card or not. The driver will rely on the VGA BIOS to have coldstarted the card before BeOS booted if you specify 'true'.
    -To make things look even more complex the driver might actually use the BIOS to determine your cards specifications on *both* possible settings. -
      -
    • false:
      - If you specify usebios false the driver will attempt to coldstart the card, which is the preferred way of doing it because of the better tuned setup if all is right. Unfortunately there's not enough info available to make this work reliably, so it's not used by default. This setting would enable you to use your card as a secondary card in your system. Be advised though that BeOS officially does not (yet) support multiple VGA cards, so you need special software in order to be able to actually use it (a video consumer node for instance). -
    • true: (default setting)
      - Specify usebios true unless you want to try to use a card as a secondary card in your system. -
    -
  • memory: (disabled by default)
    - This option enables you to override the 'memory amount autodetection' of the driver. If autodetection is working incorrect, you can manually set the amount this way. You could also lower the amount of RAM to a lower value than actually there to test with for instance overlay use in applications. So this option is probably mostly of interest to developers. Specify the RAM amount in Mb (use only 'whole' numbers!).
    -This option is disabled by default (preceded by a '#').
    -
  • hardcursor:
    - A hardcursor is nessesary for DirectWindow windowed mode support. -
      -
    • false:
      - If you have trouble with the hardcursor (on one or both of the heads), select hardcursor false. Make sure you let me know about the hardcursor trouble also: this should not happen! -
    • true: (default setting)
      - A software cursor 'flickers' a bit sometimes because it has to be redrawn constantly. So hardcursor true is the preferred setting. For DirectWindow windowed mode functionality you need to use this setting also (Chart demo app for instance). -
    -
  • logmask: (set to minimal by default)
    -The logmask option is very handy to track down trouble in the driver. You should only enable this if you are doing so, otherwise keep it turned off because it slows down your system. (All lines have a '#' preceding 'logmask' by default.) Logging creates a logfile called skel.accelerant.0.log in your ~ (home) folder. A second logfile may get created depending on how the driver is used (on cloning; for BWindowScreen for example). The second file is called skel.accelerant.1.log, and it will also be in your home folder.
    -Note: -
      -
    • You may only enable *one* logmask-line. The value you place after it (hexadecimal 32bit) determines what will be logged. The first 7 digits determine the part of the driver that will be logging, the last single digit determines the level of logging (like 'all messages', or only 'error messages'). -
    -
  • dumprom:
    -Dumprom is another 'tool' for bug-tracking purposes. -
      -
    • false: (default setting)
      - Keep it set to dumprom false, unless you want the driver to dump the contents of your VGA BIOS ROM in a file. -
    • true:
      - dumprom true lets the driver dump a copy of your VGA BIOS in a file called skel.rom in your ~ (home) folder. -
    -
  • switchhead:
    -The driver always autodetects which output should be used as primary one, but you can let the driver 'invert' the outcome of that detection with this option (only for dualhead cards). -
      -
    • false: (default setting)
      - Keep it set to switchhead false, unless you feel you want the card's other output to be used as primary one. Note that if a single connected screen is found, that screen will be the driver's primary output with this setting. -
    • true:
      - switchhead true lets the driver 'invert' the output assignments for all modes. Use only when you have two screens connected, otherwise the one connected screen will remain black as the other (not connected) output is being used.
      -
    -Note: -
      -
    • If the driver determines it cannot use a digital panel despite it being physically connected and powered on, using the switchhead option will not fix this. This is no fault in your card or the panel, but happens only because the driver relies on certain functions inside your cards BIOS to behave in a certain way. -
    -
  • force_pci:
    -On AGP cards you can block the use of AGP mode transfers. -
      -
    • false: (default setting)
      -Keep this option set to force_pci false, unless the graphics card or motherboard has trouble using AGP. -
    • true:
      -force_pci true prevents the graphicsdriver from activating AGP mode, so it will be using PCI mode like it has always been in the past. The downside of this is that this comes at a performance penalty if your motherboard supports the AGP 'fastwrite' (FW) option, which won't be utilized with this setting. -
    -Note: -
      -
    • If you have trouble using AGP mode, you should prefer tweaking the AGP busmanager settings file as it might well enable you to use a 'lesser' AGP mode instead of falling back to PCI mode alltogether. -
    -
  • unhide_fw:
    -This option is only used if your card is running in AGP mode. It's a real tweak option. It's officially unsupported, and it's unknown if it can do harm to your card or system. It exists because using it can speedup unaccelerated graphics a lot. Think about video playback or playing quake2 in software rendering mode... -
      -
    • false: (default setting)
      -Keep this option set to unhide_fw false unless you are certain you want to try the 'unsupported' graphics speedup. On cards supporting FW by default the unhide_fw option has no effect. -
    • true:
      -If you have an older card that officially doesn't support the AGP FW feature, you could possibly get this feature anyway by setting unhide_fw true. Please make sure that at the first sign of trouble (system hanging, displaying artifacts, etc) you disable this feature here again, or you might risk destroying your card and/or AGP slot. -
    -
  • pgm_panel:
    -This option only has an effect if you have a laptop panel or DVI panel connected. It's existing because it's currently impossible to setup the driver in a way every single panel outthere is happy about it. -
      -
    • false:
      -If you select pgm_panel false the driver will not program the panel's pixelclock (refreshrate). Instead it relies on your cardBIOS to have done that correctly. While this is probably the case, it might introduce some displaying errors every now and then. -
    • true: (default setting)
      -With the pgm_panel true setting, the driver will fix your panel's refreshrate to 60Hz. While this should be working on all panels outthere, some panels are particular picky about refreshrates below 60.0Hz (they shut off), and some other panels are particular picky about refreshrates above 60.0Hz (they shut off). While the driver requests the hardware to set 60.0Hz, this isn't exactly possible, so the actual setting is bound to be a tiny bit below or above 60.0Hz. -
    -
- -
-
-Rudolf Cornelissen. -

(Page last updated on November 4, 2004)

- - diff --git a/src/add-ons/kernel/drivers/graphics/cirrus/UPDATE.html b/src/add-ons/kernel/drivers/graphics/cirrus/UPDATE.html deleted file mode 100644 index bece1416c8..0000000000 --- a/src/add-ons/kernel/drivers/graphics/cirrus/UPDATE.html +++ /dev/null @@ -1,102 +0,0 @@ - - -Changes - - -

Changes done for each driverversion:

-

skel_driver 0.00, (Rudolf)

-
    -
  • based on nVidia driver 0.30; -
  • Kerneldriver uses MTR-WC mapping where available; -
  • Accelerant uses AGP busmanager to enable AGP FW where available; -
  • This is all this driver really does currently. -
-

Still todo:

-
    -
  • Clean up this driver a bit; -
  • TVout support; -
  • Improve/extend various stuff when/if possible. -
-

-

-Welcome at the Haiku-OS skeleton graphicsdriver.
-
-It contains a lot of non-working programming, almost all of which sits in the 'engine' folder of the accelerant. The main task to make this a working driver for any card outthere, is rewriting the engine. The code there is kept in place because in fact most of the time you only have to replace the actual card-register programming. And it's always handy to have an example of previous working code at hand when you do that: at least, that's my experience.
-
-Using this driver as a starting point for development
-
-You have to add your cardID and vendorID to both the kerneldriver (driver.c) and the accelerant (general.c). On top of that, you need to make the kerneldriver framebuffer mapping work. Probably the only thing you need to know is the correct area in which the buffer sits: probably the largest one available.
-
-Once you have this done in the driver, you should setup a VESA file for the resolution and depth you are going to work in (you will be developing the driver while you already work with it). Use the lowest resolution you can live with, and choose 8-bit colordepth.
-Now bootup the system in vesa mode or failsafe video mode (Startup option). Select the vesa mode you will be using explicitly for all workspaces in the Screen preferences app.
-
-OK, you should be set now. Install the new driver and reboot... You should have a normal Vesa like screen, only you'll find you have the kerneldriver loaded, the accelerant is running, and you can set modes via the Screen prefs panel: although it will only mess-up your screen. (Luckily the app falls-back to the old mode if you don't confirm the new mode ;-).
-
-If your CPU supports MTRR, the kerneldriver will have activated that, and if your card is AGP and you have the busmanager installed, the accelerant will have activated that. This means you should already have optimum speed for framebuffer access: working with BeOS should be smoother already than it was before when you where using real Vesa mode (and nothing else).
-
-
-
-OK, your first task is get to the point I am describing above. Once you have that going, it's time to really start development. Personally, I have a certain list I always run-down. My advice would be to follow it more or less, as the order of doing things has a certain logic to it, making the steps as testable as can be using this development method.
-
-
    -
  • step 1. Setup VESA mode.
    -You can do this via the 'vesa' settings file in /boot/home/config/settings/kernel/drivers/. Make sure there are no spaces or other characters after the last character defining the colordepth of the mode, or the mode will maybe not get recognized. A mode set here will get activated after the next normal reboot. A sample vesa settings file can be found in the 'sample' folder in the before mentioned folder. -
  • step 2. Setup new driver with VESA running underneath, as described above.
    -This is possible because the VESA mode is set somewhere during the bootprocess (around icon 2 or 3 in the splashscreen), while the real (new) driver is loaded when the splashscreen disappears. The real driver doesn't actually have to do anything, as the system is already capable of running in the VESA mode set before. The one thing we actually do, is map the framebuffer ourself instead of relying on the access via VESA/legacy space; and point the app_server at it so it uses the newly mapped buffer to write to the screen. All other functions are simply shut-off, as far as they are card-type specific. Developing the driver means we have to fill in the gaps one by one, testing the new functions as we go.
    -
    -Note: the card has to support VESA VBE2 (VESA BIOS Extensions V2) somehow or this development method won't work... -
  • step 3. Setup hardware cursor. (for BeOS and Zeta at least)
    -As soon as the cursor hooks are exported, the app_server will start using the driver's cursor. As long as those hooks are not exported, the app_server will generate a fake cursor itself, which I'd call a software cursor. Software cursors tend to flicker when the content displayed 'below' it gets updated. The driver's cursor is a bitmap in the graphicshardware that gets overlayed on top of the screen, so this cursor has nothing to do with the content of the desktop.
    -While it's hard or next to impossible to work with a driver that displays no cursor while the app_server is relying on it, you can get it going anyway. Of course, it will require some rebooting from time to time (get used to that ;-). I'd suggest first implementing the enable/disable bit for the cursor, and setting it's foreground and background color to white and black. Once activation of the cursor works you'll probably see a static (non-moving) random bitmap somewhere on the screen, measuring 32x32 or 64x64 pixels. Once you can see that, you can implement moving the cursor. As soon as that works, the driver is useable again more or less, as you can see what you point at.
    -As last 'item' of the cursor you need to draw the cursor's bitmap (see below on starting adress info). On modern cards this bitmap is placed somewhere in the cards graphicsmemory, and mostly needs to be on a boundary of 2K or 4K. Some older cards have specific cursor memory inside the GPU (graphics processor unit), which you then probably access in a serial way (index and data registers).
    -
    -Once the cursor works, you'll need to make sure you are telling the hardware where it can find it. By default it will probably be at cardRAM adress offset zero. Which is also where the framebuffer is placed by default mostly. This means you will see distortions in the upper few lines of the desktop as long as you place the cursor bitmap there (it's just 2K in size mostly, because 4 colors are supported in the BeOS supported mode, needing 2 bits per pixel), but the upside of this is that this is your actual confirmation the app_server is writing cursor bitmaps to graphicsRAM. So, in theory you have two choices: move the cursor bitmap, or move the Desktop. It's probably the safest bet to move the desktop (in the next step: step 3), as the visible screenbuffer can be much more precisely placed. On some cards it might not be possible however to move the desktop from adress zero, or, the cursor. It's upto you to find that out.
    -always keep in mind that you need to tell the location of the cursor and visible screenbuffer (Desktop) to two 'clients': the app_server AND the hardware.
    -
    -Things to consider with cursors might be these: -
      -
    • if you inform the card's GPU about the cursor's location, you do so by specifying the relative offset to the beginning of the cardRAM, not by specifying a physical adress. For informing the app_server you use the physical adress. -
    • redrawing needs to be done during/not during vertical retrace on some hardware (otherwise you could see distortions on some hardware); -
    • repositioning needs to be done during/not during vertical retrace on some hardware (likewise); -
    • the bitmap's reference point can be left-top or right-bottom. You'll have to correct the coordinates the app_server relays for this sometimes; -
    • the cursor bitmap may not be positioned below reference point 0,0 as the variables are mostly unsigned integers. If you do that anyway, the cursor will 'magically' disappear (wraparound). This problem occurs when you try to point at something at the left or top of the screen if it does: the source is the fact that cursors have a 'hot spot', indicating what exact postion in the bitmap the pointer is. -
    -
  • step 4. Setup framebuffer startadress.
    -Once you have setup the framebuffer (relative offset) startadress correctly, the 'collision' of the hardware cursor and the desktop should be gone. Mostly you specify the starting adress in 32-bit words, as opposed to byte adresses. Some hardware even has larger granularity, you'll have to see for yourself. Most hardware can support byte-adressing however, but you need to tell the lowest bits to an old 'VGA' register then (called pixelpanning or so).
    -You'll probably be wanting to do your best to setup byte-adressing, as this will offer smooth panning in virtual modes (MOVE_DISPLAY hook), without granularity steps taken. Byte adressing (panning) is tested in the next step (5). On the site I have for the nVidia/Matrox/Neomagic drivers you can find a small command line app called 'virtualscreen', that sets a virtual mode you request, which you can then test for this step in development, and for some other steps as well (like the next one).
    -
    -Setup a virtual screen with ONLY a large virtual height now: the width should NOT be changed (will not work yet due to missing register programming that will be added in the next step). Now move the cursor up and down so the screen starts to scroll (only possible if you have setup and activated a hardware cursor as the software cursor in the app_server does not support this feature). If you should see distortions now and then the hardware requires you to do the adress-updating during- or: not during- retrace (so synced). If syncing should be done make sure you add a timeout, as the startadress setting is also done during a SETMODE hook command, when no retraces will occur at all (screen is shut-off then!)
    -
    -Note that a screen with virtual WIDTH will use byte adressing (in 8 bit colordepth) indicating if the lower bits work OK. A screen with large virtual HEIGHT can be used to see if you got the upper bits right, or if you are missing a bit: screen wraparounds will occur then, showing you the top of the desktop while you are way below.
    -If you scroll the screen memory startadresses will be increased or decreased with the width of the screen, or to be exact: width the 'bytes_per_row' variable in the Be 'frame_buffer_config' struct (and nothing else!).
    -
    -Hints:
    -
      -
    • Know that the app_server will only work correctly on virtualscreens upto and including 10000 x 10000 pixels. Beyond that things still work, but the fill_color function will only 'handle' a rectangle upto/including 10000 x 10000 pixels; -
    • BeIDE for example cannot create windows with height beyond 2048 pixels. (it will nicely limit at that though.); -
    • Make sure that if you cannot program for byte granularity, you adjust the steps taken in MOVE_DISPLAY and MOVE_CURSOR to reflect this, otherwise you will for instance loose the cursor from the visible part of the screen on panning sometimes. Note that both functions work with pixels, while you program in bytes: the granularity is therefore colordepth dependant; -
    • Note that the VGA register pixelpanning probably works in bytes, but some hardware uses pixels here! You need to do some conversion in the calculations then. -
    -
  • step 5. Setup framebuffer pitch.
    -The framebuffer pitch, so the distance (in bytes, or pixels depending on hardware) between two adjacent horizontal 'lines' usually is NOT programmed in bytes (or pixels), meaning that there is a step-granularity here. The driver is required to be able to set any width anyway, so you have to program the equal, or nearest bigger possible 'value' in the hardware. The 'slopspace' that might exist now, is indicated to the app_Server via the difference in the virtual screen width and the bytes_per_row variable also mentioned in the previous step.
    -
    -Once you think you have setup the framebuffer startadress and pitch both correctly, you are adviced to actually test that by setting a large virtual-width mode, and start panning slowly and fast both. Panning slowly will tell you if you are actually byte-adressing as the movement of the screen will be smooth, and fast moving will probably point you at distortions if the hardware requires you to do the adress-updating during/not during retrace (so synced). Also see if the cursor always stays nicely onscreen, or if it dissapears (partly) sometimes: if so the MOVE_CURSOR function granularity needs to be adjusted.
    -
    -Note that panning will only work if you have a hardware cursor in the driver and it's used. The software cursor in the app_server does not support panning in modes. -
  • step 6. Setup colordepth.
    -
  • step 7. Setup colorpalette.
    -
  • step 8. Setup DPMS.
    -
  • step 9. Setup refreshrate (pixelPLL).
    -
  • step 10. Setup screentiming (CRTC, modeline).
    -
  • step 11. Setup 'enhanced mode'.
    -
  • step 12. Setup 2D acceleration.
    -
  • step 13. Setup video overlay.
    -
  • step 14. Setup card coldstart.
    -
-
-Todo: complete list..
-
-Rudolf Cornelissen. -

(Page last updated on November 8, 2004)

- - diff --git a/src/add-ons/kernel/drivers/graphics/cirrus/cirrus.settings b/src/add-ons/kernel/drivers/graphics/cirrus/cirrus.settings deleted file mode 100644 index 2ebd63d20f..0000000000 --- a/src/add-ons/kernel/drivers/graphics/cirrus/cirrus.settings +++ /dev/null @@ -1,57 +0,0 @@ -# Settings file for the cirrus driver and accelerant -# -# This file should be moved to the directory -# ~/config/settings/kernel/drivers/ -# - -# nv.driver parameters -# accelerant "nv.accelerant" - -# nv.accelerant parameters -usebios true # if true rely on bios to coldstart the card -memory 2 # in MB, override builtin memory size detection -hardcursor false # if true use on-chip cursor capabilities -#logmask 0x00000000 # nothing logged, is default -#logmask 0x08000604 # log overlay use in full -#logmask 0xffffffff # log everything -dumprom false # dump bios rom in ~/nv.rom -switchhead false # switch head assignment (dualhead cards only) -force_pci false # block AGP mode use if true (AGP cards only) - -# WARNING: tweak alert! modify stuff below on your own risk... -unhide_fw false # if true 'unhide' cards AGP fastwrite support on cards that hide it -pgm_panel true # if false don't program DVI and laptop panel pixelclocks (refreshrates) -#--------- that's all. - - -#logmask setup info: -#log level select: -#logmask 0x0000000x # lowest digit: bitmask to select logging level. - -#log modules select: -#logmask 0xxxxxxxx0 # highest 7 digits: bitmask to select individual modules to log. - -#log modules: -#logmask 0x00000100 # engine: agp -#logmask 0x00000200 # engine: bes -#logmask 0x00000400 # overlay -#logmask 0x00000800 # engine: support -#logmask 0x00001000 # engine: dac2 -#logmask 0x00002000 # engine: info -#logmask 0x00004000 # engine: i2c -#logmask 0x00008000 # engine: general -#logmask 0x00010000 # engine: dac1 -#logmask 0x00020000 # engine: crtc2 -#logmask 0x00040000 # engine: crtc1 -#logmask 0x00080000 # engine: acc -#logmask 0x00100000 # engine: brooktree tv -#logmask 0x00200000 # set displaymode -#logmask 0x00400000 # propose displaymode -#logmask 0x00800000 # init accelerant -#logmask 0x01000000 # get timing constraints -#logmask 0x02000000 # get mode info -#logmask 0x04000000 # get device info -#logmask 0x08000000 # get accelerant hook -#logmask 0x10000000 # engine management -#logmask 0x20000000 # cursor -#logmask 0x40000000 # acceleration diff --git a/src/add-ons/kernel/drivers/graphics/cirrus/driver.c b/src/add-ons/kernel/drivers/graphics/cirrus/driver.c deleted file mode 100644 index 23141dc6e1..0000000000 --- a/src/add-ons/kernel/drivers/graphics/cirrus/driver.c +++ /dev/null @@ -1,990 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson; - Rudolf Cornelissen 3/2002-4/2006. - François Revol 2006. -*/ - -/* standard kernel driver stuff */ -#include -#include -#include -#include -#include -#include -#include // for strtoXX -#include "AGP.h" - -/* this is for the standardized portion of the driver API */ -/* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ -#include - -/* this is for sprintf() */ -#include - -/* this is for string compares */ -#include - -/* The private interface between the accelerant and the kernel driver. */ -#include "DriverInterface.h" -#include "macros.h" - -#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) -#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) - -#define MAX_DEVICES 8 - -#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" // apsed - -/* Tell the kernel what revision of the driver API we support */ -int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 - -/* these structures are private to the kernel driver */ -typedef struct device_info device_info; - -typedef struct { - timer te; /* timer entry for add_timer() */ - device_info *di; /* pointer to the owning device */ - bigtime_t when_target; /* when we're supposed to wake up */ -} timer_info; - -struct device_info { - uint32 is_open; /* a count of how many times the devices has been opened */ - area_id shared_area; /* the area shared between the driver and all of the accelerants */ - shared_info *si; /* a pointer to the shared area, for convenience */ - vuint32 *regs; /* kernel's pointer to memory mapped registers */ - pci_info pcii; /* a convenience copy of the pci info for this device */ - char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ -}; - -typedef struct { - uint32 count; /* number of devices actually found */ - benaphore kernel; /* for serializing opens/closes */ - char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ - device_info di[MAX_DEVICES]; /* device specific stuff */ -} DeviceData; - -/* prototypes for our private functions */ -static status_t open_hook (const char* name, uint32 flags, void** cookie); -static status_t close_hook (void* dev); -static status_t free_hook (void* dev); -static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); -static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); -static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); -static status_t map_device(device_info *di); -static void unmap_device(device_info *di); -static void probe_devices(void); -static int32 eng_interrupt(void *data); - -static DeviceData *pd; -static isa_module_info *isa_bus = NULL; -static pci_module_info *pci_bus = NULL; -static agp_module_info *agp_bus = NULL; -static device_hooks graphics_device_hooks = { - open_hook, - close_hook, - free_hook, - control_hook, - read_hook, - write_hook, - NULL, - NULL, - NULL, - NULL -}; - -#define VENDOR_ID_CIRRUS 0x1013 /* Cirrus */ - -static uint16 cirrus_device_list[] = { - CIRRUS_ID_CLGD5430, - CIRRUS_ID_CLGD5434, - //CIRRUS_ID_CLGD5436, - //CIRRUS_ID_CLGD5446, - CIRRUS_ID_CLGD5462, - CIRRUS_ID_CLGD5465, - 0 -}; - -static struct { - uint16 vendor; - uint16 *devices; -} SupportedDevices[] = { - {VENDOR_ID_CIRRUS, cirrus_device_list}, - {0x0000, NULL} -}; - -static settings current_settings = { // see comments in skel.settings - // for driver - DRIVER_PREFIX ".accelerant", - false, // dumprom - // for accelerant - 0x00000000, // logmask - 0, // memory - true, // usebios - true, // hardcursor - false, // switchhead - false, // force_pci - false, // unhide_fw - true, // pgm_panel -}; - -static void dumprom (void *rom, uint32 size) -{ - int fd; - uint32 cnt; - - fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); - if (fd < 0) return; - - /* apparantly max. 32kb may be written at once; - * the ROM size is a multiple of that anyway. */ - for (cnt = 0; (cnt < size); cnt += 32768) - write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); - close (fd); -} - -/* return 1 if vblank interrupt has occured */ -static int caused_vbi(vuint32 * regs) -{ -// return (ENG_RG32(RG32_CRTC_INTS) & 0x00000001); -return 0; -} - -/* clear the vblank interrupt */ -static void clear_vbi(vuint32 * regs) -{ -// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; -} - -static void enable_vbi(vuint32 * regs) -{ - /* clear the vblank interrupt */ -// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; - /* enable nVidia interrupt source vblank */ -// ENG_RG32(RG32_CRTC_INTE) |= 0x00000001; - /* enable nVidia interrupt system hardware (b0-1) */ -// ENG_RG32(RG32_MAIN_INTE) = 0x00000001; -} - -static void disable_vbi(vuint32 * regs) -{ - /* disable nVidia interrupt source vblank */ -// ENG_RG32(RG32_CRTC_INTE) &= 0xfffffffe; - /* clear the vblank interrupt */ -// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; - /* disable nVidia interrupt system hardware (b0-1) */ -// ENG_RG32(RG32_MAIN_INTE) = 0x00000000; -} - -/* - init_hardware() - Returns B_OK if one is - found, otherwise returns B_ERROR so the driver will be unloaded. -*/ -status_t -init_hardware(void) { - long pci_index = 0; - pci_info pcii; - bool found_one = false; - - /* choke if we can't find the PCI bus */ - if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) - return B_ERROR; - - /* choke if we can't find the ISA bus */ - if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) - { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - - /* while there are more pci devices */ - while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { - int vendor = 0; - - /* if we match a supported vendor */ - while (SupportedDevices[vendor].vendor) { - if (SupportedDevices[vendor].vendor == pcii.vendor_id) { - uint16 *devices = SupportedDevices[vendor].devices; - /* while there are more supported devices */ - while (*devices) { - /* if we match a supported device */ - if (*devices == pcii.device_id ) { - - found_one = true; - goto done; - } - /* next supported device */ - devices++; - } - } - vendor++; - } - /* next pci_info struct, please */ - pci_index++; - } - -done: - /* put away the module manager */ - put_module(B_PCI_MODULE_NAME); - return (found_one ? B_OK : B_ERROR); -} - -status_t -init_driver(void) { - void *settings_handle; - - // get driver/accelerant settings, apsed - settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); - if (settings_handle != NULL) { - const char *item; - char *end; - uint32 value; - - // for driver - item = get_driver_parameter (settings_handle, "accelerant", "", ""); - if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { - strcpy (current_settings.accelerant, item); - } - current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); - - // for accelerant - item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); - value = strtoul (item, &end, 0); - if (*end == '\0') current_settings.logmask = value; - - item = get_driver_parameter (settings_handle, "memory", "0", "0"); - value = strtoul (item, &end, 0); - if (*end == '\0') current_settings.memory = value; - - current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); - current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); - current_settings.switchhead = get_driver_boolean_parameter (settings_handle, "switchhead", false, false); - current_settings.force_pci = get_driver_boolean_parameter (settings_handle, "force_pci", false, false); - current_settings.unhide_fw = get_driver_boolean_parameter (settings_handle, "unhide_fw", false, false); - current_settings.pgm_panel = get_driver_boolean_parameter (settings_handle, "pgm_panel", false, false); - - unload_driver_settings (settings_handle); - } - - /* get a handle for the pci bus */ - if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) - return B_ERROR; - - /* get a handle for the isa bus */ - if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) - { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - - /* get a handle for the agp bus if it exists */ - get_module(B_AGP_MODULE_NAME, (module_info **)&agp_bus); - - /* driver private data */ - pd = (DeviceData *)calloc(1, sizeof(DeviceData)); - if (!pd) { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - /* initialize the benaphore */ - INIT_BEN(pd->kernel); - /* find all of our supported devices */ - probe_devices(); - return B_OK; -} - -const char ** -publish_devices(void) { - /* return the list of supported devices */ - return (const char **)pd->device_names; -} - -device_hooks * -find_device(const char *name) { - int index = 0; - while (pd->device_names[index]) { - if (strcmp(name, pd->device_names[index]) == 0) - return &graphics_device_hooks; - index++; - } - return NULL; - -} - -void uninit_driver(void) { - - /* free the driver data */ - DELETE_BEN(pd->kernel); - free(pd); - pd = NULL; - - /* put the pci module away */ - put_module(B_PCI_MODULE_NAME); - put_module(B_ISA_MODULE_NAME); - - /* put the agp module away if it's there */ - if (agp_bus) put_module(B_AGP_MODULE_NAME); -} - -static status_t map_device(device_info *di) -{ - char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ - shared_info *si = di->si; - uint32 tmpUlong; - pci_info *pcii = &(di->pcii); - system_info sysinfo; - - /*storage for the physical to virtual table (used for dma buffer)*/ -// physical_entry physical_memory[2]; -// #define G400_DMA_BUFFER_SIZE 1024*1024 - - /* variables for making copy of ROM */ - uint8* rom_temp; - area_id rom_area; - - /* Nvidia cards have registers in [0] and framebuffer in [1] */ - int registers = 1; - int frame_buffer = 0; -// int pseudo_dma = 2; - - /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ - tmpUlong = get_pci(PCI_command, 2); - /* enable PCI access */ - tmpUlong |= PCI_command_memory; - /* enable busmastering */ - tmpUlong |= PCI_command_master; - /* disable ISA I/O access */ - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /*work out which version of BeOS is running*/ - get_system_info(&sysinfo); - if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ - { - si->use_clone_bugfix = 1; - } - else - { - si->use_clone_bugfix = 0; - } - - /* work out a name for the register mapping */ - sprintf(buffer, DEVICE_FORMAT " regs", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* get a virtual memory address for the registers*/ - si->regs_area = map_physical_memory( - buffer, - /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ - (void *) di->pcii.u.h0.base_registers_pci[registers], - di->pcii.u.h0.base_register_sizes[registers], - B_ANY_KERNEL_ADDRESS, - (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), - (void **)&(di->regs)); - si->clone_bugfix_regs = (uint32 *) di->regs; - - /* if mapping registers to vmem failed then pass on error */ - if (si->regs_area < 0) return si->regs_area; - - /* work out a name for the ROM mapping*/ - sprintf(buffer, DEVICE_FORMAT " rom", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* disable ROM shadowing, we want the guaranteed exact contents of the chip */ - /* warning: - * don't touch: (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. - * NV18, NV28 and NV34 keep working. - * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, - * however the actual ROM content (so the used part) is intact (confirmed). */ - //set_pci(ENCFG_ROMSHADOW, 4, 0); - - /* get ROM memory mapped base adress - this is defined in the PCI standard */ - tmpUlong = get_pci(PCI_rom_base, 4); - if (tmpUlong) - { - /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ - tmpUlong |= 0x00000001; - set_pci(PCI_rom_base, 4, tmpUlong); - - rom_area = map_physical_memory( - buffer, - (void *)di->pcii.u.h0.rom_base_pci, - di->pcii.u.h0.rom_size, - B_ANY_KERNEL_ADDRESS, - B_READ_AREA, - (void **)&(rom_temp) - ); - - /* check if we got the BIOS signature (might fail on laptops..) */ - if (rom_temp[0]!=0x55 || rom_temp[1]!=0xaa) - { - /* apparantly no ROM is mapped here */ - delete_area(rom_area); - rom_area = -1; - /* force using ISA legacy map as fall-back */ - tmpUlong = 0x00000000; - } - } - - if (!tmpUlong) - { - /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ - rom_area = map_physical_memory( - buffer, - (void *)0x000c0000, - 65536, - B_ANY_KERNEL_ADDRESS, - B_READ_AREA, - (void **)&(rom_temp) - ); - } - - /* if mapping ROM to vmem failed then clean up and pass on error */ - if (rom_area < 0) { - delete_area(si->regs_area); - si->regs_area = -1; - return rom_area; - } - - /* dump ROM to file if selected in skel.settings - * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ - if (current_settings.dumprom) dumprom (rom_temp, 65536); - /* make a copy of ROM for future reference */ - memcpy (si->rom_mirror, rom_temp, 65536); - - /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ - tmpUlong = get_pci(PCI_rom_base, 4); - tmpUlong &= 0xfffffffe; - set_pci(PCI_rom_base, 4, tmpUlong); - delete_area(rom_area); - - /* work out a name for the framebuffer mapping*/ - sprintf(buffer, DEVICE_FORMAT " framebuffer", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* map the framebuffer into vmem, using Write Combining*/ - si->fb_area = map_physical_memory( - buffer, - /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ - (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], - di->pcii.u.h0.base_register_sizes[frame_buffer], - B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, - B_READ_AREA + B_WRITE_AREA, - &(si->framebuffer)); - - /*if failed with write combining try again without*/ - if (si->fb_area < 0) { - si->fb_area = map_physical_memory( - buffer, - /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ - (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], - di->pcii.u.h0.base_register_sizes[frame_buffer], - B_ANY_KERNEL_BLOCK_ADDRESS, - B_READ_AREA + B_WRITE_AREA, - &(si->framebuffer)); - } - - /* if there was an error, delete our other areas and pass on error*/ - if (si->fb_area < 0) - { - delete_area(si->regs_area); - si->regs_area = -1; - return si->fb_area; - } -//fixme: retest for card coldstart and PCI/virt_mem mapping!! - /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ - si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; - - // remember settings for use here and in accelerant - si->settings = current_settings; - - /* in any case, return the result */ - return si->fb_area; -} - -static void unmap_device(device_info *di) { - shared_info *si = di->si; - uint32 tmpUlong; - pci_info *pcii = &(di->pcii); - - /* disable memory mapped IO */ - tmpUlong = get_pci(PCI_command, 4); - tmpUlong &= 0xfffffffc; - set_pci(PCI_command, 4, tmpUlong); - /* delete the areas */ - if (si->regs_area >= 0) delete_area(si->regs_area); - if (si->fb_area >= 0) delete_area(si->fb_area); - si->regs_area = si->fb_area = -1; - si->framebuffer = NULL; - di->regs = NULL; -} - -static void probe_devices(void) { - uint32 pci_index = 0; - uint32 count = 0; - device_info *di = pd->di; - - /* while there are more pci devices */ - while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { - int vendor = 0; - - /* if we match a supported vendor */ - while (SupportedDevices[vendor].vendor) { - if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { - uint16 *devices = SupportedDevices[vendor].devices; - /* while there are more supported devices */ - while (*devices) { - /* if we match a supported device */ - if (*devices == di->pcii.device_id ) { - /* publish the device name */ - sprintf(di->name, "graphics/" DEVICE_FORMAT, - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* remember the name */ - pd->device_names[count] = di->name; - /* mark the driver as available for R/W open */ - di->is_open = 0; - /* mark areas as not yet created */ - di->shared_area = -1; - /* mark pointer to shared data as invalid */ - di->si = NULL; - /* inc pointer to device info */ - di++; - /* inc count */ - count++; - /* break out of these while loops */ - goto next_device; - } - /* next supported device */ - devices++; - } - } - vendor++; - } -next_device: - /* next pci_info struct, please */ - pci_index++; - } - /* propagate count */ - pd->count = count; - /* terminate list of device names with a null pointer */ - pd->device_names[pd->count] = NULL; -} - -static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { - uint32 handled = B_HANDLED_INTERRUPT; - /* release the vblank semaphore */ - if (si->vblank >= 0) { - int32 blocked; - if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { - release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); - handled = B_INVOKE_SCHEDULER; - } - } - return handled; -} - -static int32 -eng_interrupt(void *data) -{ - int32 handled = B_UNHANDLED_INTERRUPT; - device_info *di = (device_info *)data; - shared_info *si = di->si; - int32 *flags = &(si->flags); - vuint32 *regs; - - /* is someone already handling an interrupt for this device? */ - if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { - goto exit0; - } - /* get regs */ - regs = di->regs; - - /* was it a VBI? */ - if (caused_vbi(regs)) { - /*clear the interrupt*/ - clear_vbi(regs); - /*release the semaphore*/ - handled = thread_interrupt_work(flags, regs, si); - } - - /* note that we're not in the handler any more */ - atomic_and(flags, ~SKD_HANDLER_INSTALLED); - -exit0: - return handled; -} - -static status_t open_hook (const char* name, uint32 flags, void** cookie) { - int32 index = 0; - device_info *di; - shared_info *si; - thread_id thid; - thread_info thinfo; - status_t result = B_OK; - vuint32 *regs; - char shared_name[B_OS_NAME_LENGTH]; - - /* find the device name in the list of devices */ - /* we're never passed a name we didn't publish */ - while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; - - /* for convienience */ - di = &(pd->di[index]); - - /* make sure no one else has write access to the common data */ - AQUIRE_BEN(pd->kernel); - - /* if it's already open for writing */ - if (di->is_open) { - /* mark it open another time */ - goto mark_as_open; - } - /* create the shared area */ - sprintf(shared_name, DEVICE_FORMAT " shared", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - /* create this area with NO user-space read or write permissions, to prevent accidental dammage */ - di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 0); - if (di->shared_area < 0) { - /* return the error */ - result = di->shared_area; - goto done; - } - - /* save a few dereferences */ - si = di->si; - - /* save the vendor and device IDs */ - si->vendor_id = di->pcii.vendor_id; - si->device_id = di->pcii.device_id; - si->revision = di->pcii.revision; - si->bus = di->pcii.bus; - si->device = di->pcii.device; - si->function = di->pcii.function; - - /* note the amount of system RAM the system BIOS assigned to the card if applicable: - * unified memory architecture (UMA) */ - switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) - { - case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ - /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ - si->ps.memory_size = 1024 * 1024 * - (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); - /* last 64kB RAM is used for the BIOS (or something else?) */ - si->ps.memory_size -= (64 * 1024); - break; - case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ - /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ - si->ps.memory_size = 1024 * 1024 * - (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); - /* last 64kB RAM is used for the BIOS (or something else?) */ - si->ps.memory_size -= (64 * 1024); - break; - default: - /* all other cards have own RAM: the amount of which is determined in the - * accelerant. */ - break; - } - - /* map the device */ - result = map_device(di); - if (result < 0) goto free_shared; - result = B_OK; - - /* create a semaphore for vertical blank management */ - si->vblank = create_sem(0, di->name); - if (si->vblank < 0) { - result = si->vblank; - goto unmap; - } - - /* change the owner of the semaphores to the opener's team */ - /* this is required because apps can't aquire kernel semaphores */ - thid = find_thread(NULL); - get_thread_info(thid, &thinfo); - set_sem_owner(si->vblank, thinfo.team); - - /* assign local regs pointer for SAMPLExx() macros */ - regs = di->regs; - - /* disable and clear any pending interrupts */ - disable_vbi(regs); - - /* If there is a valid interrupt line assigned then set up interrupts */ - if ((di->pcii.u.h0.interrupt_pin == 0x00) || - (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ - (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ - { - /* we are aborting! */ - /* Note: the R4 graphics driver kit lacks this statement!! */ - result = B_ERROR; - /* interrupt does not exist so exit without installing our handler */ - goto delete_the_sem; - } - else - { - /* otherwise install our interrupt handler */ - result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, eng_interrupt, (void *)di, 0); - /* bail if we couldn't install the handler */ - if (result != B_OK) goto delete_the_sem; - } - -mark_as_open: - /* mark the device open */ - di->is_open++; - - /* send the cookie to the opener */ - *cookie = di; - - goto done; - - -delete_the_sem: - delete_sem(si->vblank); - -unmap: - unmap_device(di); - -free_shared: - /* clean up our shared area */ - delete_area(di->shared_area); - di->shared_area = -1; - di->si = NULL; - -done: - /* end of critical section */ - RELEASE_BEN(pd->kernel); - - /* all done, return the status */ - return result; -} - -/* ---------- - read_hook - does nothing, gracefully ------ */ -static status_t -read_hook (void* dev, off_t pos, void* buf, size_t* len) -{ - *len = 0; - return B_NOT_ALLOWED; -} - -/* ---------- - write_hook - does nothing, gracefully ------ */ -static status_t -write_hook (void* dev, off_t pos, const void* buf, size_t* len) -{ - *len = 0; - return B_NOT_ALLOWED; -} - -/* ---------- - close_hook - does nothing, gracefully ------ */ -static status_t -close_hook (void* dev) -{ - /* we don't do anything on close: there might be dup'd fd */ - return B_NO_ERROR; -} - -/* ----------- - free_hook - close down the device ------------ */ -static status_t -free_hook (void* dev) { - device_info *di = (device_info *)dev; - shared_info *si = di->si; - vuint32 *regs = di->regs; - - /* lock the driver */ - AQUIRE_BEN(pd->kernel); - - /* if opened multiple times, decrement the open count and exit */ - if (di->is_open > 1) - goto unlock_and_exit; - - /* disable and clear any pending interrupts */ - disable_vbi(regs); - - /* remove interrupt handler */ - remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, eng_interrupt, di); - - /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ - delete_sem(si->vblank); - si->vblank = -1; - - /* free regs and framebuffer areas */ - unmap_device(di); - - /* clean up our shared area */ - delete_area(di->shared_area); - di->shared_area = -1; - di->si = NULL; - -unlock_and_exit: - /* mark the device available */ - di->is_open--; - /* unlock the driver */ - RELEASE_BEN(pd->kernel); - /* all done */ - return B_OK; -} - -/* ----------- - control_hook - where the real work is done ------------ */ -static status_t -control_hook (void* dev, uint32 msg, void *buf, size_t len) { - device_info *di = (device_info *)dev; - status_t result = B_DEV_INVALID_IOCTL; - uint32 tmpUlong; - - switch (msg) { - /* the only PUBLIC ioctl */ - case B_GET_ACCELERANT_SIGNATURE: { - char *sig = (char *)buf; - strcpy(sig, current_settings.accelerant); - result = B_OK; - } break; - - /* PRIVATE ioctl from here on */ - case ENG_GET_PRIVATE_DATA: { - eng_get_private_data *gpd = (eng_get_private_data *)buf; - if (gpd->magic == SKEL_PRIVATE_DATA_MAGIC) { - gpd->shared_info_area = di->shared_area; - result = B_OK; - } - } break; - case ENG_GET_PCI: { - eng_get_set_pci *gsp = (eng_get_set_pci *)buf; - if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - gsp->value = get_pci(gsp->offset, gsp->size); - result = B_OK; - } - } break; - case ENG_SET_PCI: { - eng_get_set_pci *gsp = (eng_get_set_pci *)buf; - if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - set_pci(gsp->offset, gsp->size, gsp->value); - result = B_OK; - } - } break; - case ENG_DEVICE_NAME: { // apsed - eng_device_name *dn = (eng_device_name *)buf; - if (dn->magic == SKEL_PRIVATE_DATA_MAGIC) { - strcpy(dn->name, di->name); - result = B_OK; - } - } break; - case ENG_RUN_INTERRUPTS: { - eng_set_bool_state *ri = (eng_set_bool_state *)buf; - if (ri->magic == SKEL_PRIVATE_DATA_MAGIC) { - vuint32 *regs = di->regs; - if (ri->do_it) { - enable_vbi(regs); - } else { - disable_vbi(regs); - } - result = B_OK; - } - } break; - case ENG_GET_NTH_AGP_INFO: { - eng_nth_agp_info *nai = (eng_nth_agp_info *)buf; - if (nai->magic == SKEL_PRIVATE_DATA_MAGIC) { - nai->exist = false; - nai->agp_bus = false; - if (agp_bus) { - nai->agp_bus = true; - if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) { - nai->exist = true; - } - } - result = B_OK; - } - } break; - case ENG_ENABLE_AGP: { - eng_cmd_agp *nca = (eng_cmd_agp *)buf; - if (nca->magic == SKEL_PRIVATE_DATA_MAGIC) { - if (agp_bus) { - nca->agp_bus = true; - (*agp_bus->enable_agp)(&(nca->cmd)); - } else { - nca->agp_bus = false; - nca->cmd = 0; - } - result = B_OK; - } - } break; - case ENG_ISA_OUT: { - eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; - if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - - /* lock the driver: - * no other graphics card may have ISA I/O enabled when we enter */ - AQUIRE_BEN(pd->kernel); - - /* enable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong |= PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - if (io_isa->size == 1) - isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); - else - isa_bus->write_io_16(io_isa->adress, io_isa->data); - result = B_OK; - - /* disable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /* end of critical section */ - RELEASE_BEN(pd->kernel); - } - } break; - case ENG_ISA_IN: { - eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; - if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - - /* lock the driver: - * no other graphics card may have ISA I/O enabled when we enter */ - AQUIRE_BEN(pd->kernel); - - /* enable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong |= PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - if (io_isa->size == 1) - io_isa->data = isa_bus->read_io_8(io_isa->adress); - else - io_isa->data = isa_bus->read_io_16(io_isa->adress); - result = B_OK; - - /* disable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /* end of critical section */ - RELEASE_BEN(pd->kernel); - } - } break; - } - return result; -}