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small cleanup. This fixes DMA buffer freespace tracking as well.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11000 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-01-24 09:50:07 +00:00
parent dd43b03ce1
commit de653df809
1 changed files with 77 additions and 115 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+65 -103
View File
@@ -31,6 +31,7 @@ blit
static void nv_start_dma(void); static void nv_start_dma(void);
static status_t nv_acc_fifofree_dma(uint16 cmd_size); static status_t nv_acc_fifofree_dma(uint16 cmd_size);
static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size); static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size);
static void nv_acc_set_ch_dma(uint16 ch, uint32 handle);
/* used to track engine DMA stalls */ /* used to track engine DMA stalls */
static uint8 err; static uint8 err;
@@ -78,7 +79,7 @@ status_t nv_acc_wait_idle_dma()
status_t nv_acc_init_dma() status_t nv_acc_init_dma()
{ {
uint16 cnt; uint16 cnt;
uint32 surf_depth, patt_depth, bmap_depth; uint32 surf_depth, cmd_depth;
/* reset the engine DMA stalls counter */ /* reset the engine DMA stalls counter */
err = 0; err = 0;
@@ -702,55 +703,30 @@ status_t nv_acc_init_dma()
si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
/*** init FIFO via DMA command buffer. ***/ /*** init FIFO via DMA command buffer. ***/
/* note: /* wait for room in fifo for new FIFO assigment cmds if needed: */
* we know there's space enough in the command buffer to issue these commands, nv_acc_fifofree_dma(16);
* so no need to wait for room in there. */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH0 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* program new FIFO assignments */
(NV_GENERAL_FIFO_CH1 | (1 << 18)); /* Raster OPeration: */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
(0x80000000 | si->engine.fifo.handle[1]); /* Clip */ /* Clip: */
nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* Pattern: */
(NV_GENERAL_FIFO_CH2 | (1 << 18)); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* 2D Surface: */
(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */ nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
/* Blit: */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
(NV_GENERAL_FIFO_CH3 | (1 << 18)); /* Bitmap: */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */ /* Line: (not used or 3D only?) */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH4 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[4]); /* Blit */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH5 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH6 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
//fixme: temporary so there's something valid here.. (maybe needed, don't yet know) //fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
// (0x80000000 | si->engine.fifo.handle[6]); /* Line (not used or 3D only?) */ // nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);
(0x80000000 | si->engine.fifo.handle[0]); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[0]);
/* Textured Triangle: (3D only) */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH7 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
//fixme: temporary so there's something valid here.. (maybe needed, don't yet know) //fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
// (0x80000000 | si->engine.fifo.handle[7]); /* Textured Triangle (3D only) */ // nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]);
(0x80000000 | si->engine.fifo.handle[0]); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[0]);
/* update the current free space we have left in the DMA buffer */
si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
//fixme: overlay should stay outside the DMA buffer, also add a failsafe //fixme: overlay should stay outside the DMA buffer, also add a failsafe
// space in between both functions as errors might hang the engine! // space in between both functions as errors might hang the engine!
@@ -759,26 +735,25 @@ status_t nv_acc_init_dma()
{ {
case B_CMAP8: case B_CMAP8:
surf_depth = 0x00000001; surf_depth = 0x00000001;
patt_depth = 0x00000003; cmd_depth = 0x00000003;
bmap_depth = 0x00000003;
break; break;
case B_RGB15_LITTLE: case B_RGB15_LITTLE:
case B_RGB16_LITTLE: case B_RGB16_LITTLE:
surf_depth = 0x00000004; surf_depth = 0x00000004;
patt_depth = 0x00000001; cmd_depth = 0x00000001;
bmap_depth = 0x00000001;
break; break;
case B_RGB32_LITTLE: case B_RGB32_LITTLE:
case B_RGBA32_LITTLE: case B_RGBA32_LITTLE:
surf_depth = 0x00000006; surf_depth = 0x00000006;
patt_depth = 0x00000003; cmd_depth = 0x00000003;
bmap_depth = 0x00000003;
break; break;
default: default:
LOG(8,("ACC_DMA: init, invalid bit depth\n")); LOG(8,("ACC_DMA: init, invalid bit depth\n"));
return B_ERROR; return B_ERROR;
} }
/* wait for room in fifo for surface setup cmd if needed */
nv_acc_fifofree_dma(5);
/* now setup 2D surface (writing 5 32bit words) */ /* now setup 2D surface (writing 5 32bit words) */
nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 4); nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 4);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = surf_depth; /* Format */ si->engine.dma.cmdbuffer[si->engine.dma.current++] = surf_depth; /* Format */
@@ -791,13 +766,17 @@ status_t nv_acc_init_dma()
si->engine.dma.cmdbuffer[si->engine.dma.current++] = si->engine.dma.cmdbuffer[si->engine.dma.current++] =
((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */ ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */
/* wait for room in fifo for pattern colordepth setup cmd if needed */
nv_acc_fifofree_dma(2);
/* set pattern colordepth (writing 2 32bit words) */ /* set pattern colordepth (writing 2 32bit words) */
nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLORFORMAT, 1); nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLORFORMAT, 1);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = patt_depth; /* SetColorFormat */ si->engine.dma.cmdbuffer[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */
/* wait for room in fifo for bitmap colordepth setup cmd if needed */
nv_acc_fifofree_dma(2);
/* set bitmap colordepth (writing 2 32bit words) */ /* set bitmap colordepth (writing 2 32bit words) */
nv_acc_cmd_dma(NV3_GDI_RECTANGLE_TEXT, NV3_GDI_RECTANGLE_TEXT_SETCOLORFORMAT, 1); nv_acc_cmd_dma(NV3_GDI_RECTANGLE_TEXT, NV3_GDI_RECTANGLE_TEXT_SETCOLORFORMAT, 1);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = bmap_depth; /* SetColorFormat */ si->engine.dma.cmdbuffer[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */
/* tell the engine to fetch and execute all (new) commands in the DMA buffer */ /* tell the engine to fetch and execute all (new) commands in the DMA buffer */
nv_start_dma(); nv_start_dma();
@@ -836,26 +815,23 @@ for (dummy = 0; dummy < 2; dummy++)
} }
} }
/* this routine does not check the engine's internal hardware FIFO, but the DMA
* command buffer. You can see this as a FIFO as well, that feeds the hardware FIFO.
* The hardware FIFO state is checked by the DMA hardware automatically. */
static status_t nv_acc_fifofree_dma(uint16 cmd_size) static status_t nv_acc_fifofree_dma(uint16 cmd_size)
{ {
//test: //test:
uint32 dummy; uint32 dummy;
/* check if the DMA buffer has enough room for the command */
if (si->engine.dma.free < cmd_size) if (si->engine.dma.free < cmd_size)
{ {
//test: //test:
LOG(4,("ACC_FIFOFREE: level 1; free $%08x, max $%08x, current $%08x\n", LOG(4,("ACC_FIFOFREE: level 1; free $%08x, max $%08x, current $%08x\n",
si->engine.dma.free, si->engine.dma.max, si->engine.dma.current )); si->engine.dma.free, si->engine.dma.max, si->engine.dma.current ));
/* update to actual current situation (free is 'cached') */ /* not enough room left, so instruct DMA engine to reset the buffer when
// si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; * it's done */
/* check again if we have enough space */
// if (si->engine.dma.free < cmd_size)
{
//test:
LOG(4,("ACC_FIFOFREE: level 2\n"));
/* nope, so instruct DMA engine to reset the buffer when it's done */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0x20000000; si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0x20000000;
/* reset our buffer pointer, so new commands will be placed at the /* reset our buffer pointer, so new commands will be placed at the
@@ -868,12 +844,8 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size)
* we are assuming here that a large part in the beginning of the DMA * we are assuming here that a large part in the beginning of the DMA
* cmd buffer is already processed. If this is not true, we need to wait * cmd buffer is already processed. If this is not true, we need to wait
* here until the engine becomes idle or so... */ * here until the engine becomes idle or so... */
//test: //test:
//nv_acc_wait_idle_dma();
// {
/* snooze a bit so I do not hammer the bus */
// snooze (100);
// }
for (dummy = 0; dummy < 2; dummy++) for (dummy = 0; dummy < 2; dummy++)
{ {
LOG(4,("ACC_DMA_WRAP: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + LOG(4,("ACC_DMA_WRAP: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET +
@@ -884,7 +856,6 @@ for (dummy = 0; dummy < 2; dummy++)
/* update the current free space we have left in the DMA buffer */ /* update the current free space we have left in the DMA buffer */
si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
} }
}
return B_OK; return B_OK;
} }
@@ -906,10 +877,21 @@ static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((size << 18) | si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((size << 18) |
((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc)); ((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));
/* space left after issuing the current command is the cmd AND it's data less */ /* space left after issuing the current command is the cmd AND it's arguments less */
si->engine.dma.free -= (size + 1); si->engine.dma.free -= (size + 1);
} }
static void nv_acc_set_ch_dma(uint16 ch, uint32 handle)
{
/* issue FIFO channel assign cmd */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((1 << 18) | ch);
/* set new assignment */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = (0x80000000 | handle);
/* space left after issuing the current command is the cmd AND it's arguments less */
si->engine.dma.free -= 2;
}
/* fixme? (check this out..) /* fixme? (check this out..)
* Looks like this stuff can be very much simplified and speed-up, as it seems it's not * Looks like this stuff can be very much simplified and speed-up, as it seems it's not
* nessesary to wait for the engine to become idle before re-assigning channels. * nessesary to wait for the engine to become idle before re-assigning channels.
@@ -962,38 +944,18 @@ void nv_acc_assert_fifo_dma(void)
nv_acc_fifofree_dma(12); nv_acc_fifofree_dma(12);
/* program new FIFO assignments */ /* program new FIFO assignments */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* Raster OPeration: */
(NV_GENERAL_FIFO_CH0 | (1 << 18)); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* Clip: */
(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */ nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
/* Pattern: */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
(NV_GENERAL_FIFO_CH1 | (1 << 18)); /* 2D Surface: */
si->engine.dma.cmdbuffer[si->engine.dma.current++] = nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
(0x80000000 | si->engine.fifo.handle[1]); /* Clip */ /* Blit: */
nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
si->engine.dma.cmdbuffer[si->engine.dma.current++] = /* Bitmap: */
(NV_GENERAL_FIFO_CH2 | (1 << 18)); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH3 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH4 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[4]); /* Blit */
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(NV_GENERAL_FIFO_CH5 | (1 << 18));
si->engine.dma.cmdbuffer[si->engine.dma.current++] =
(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
/* update the current free space we have left in the DMA buffer */
si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
/* tell the engine to fetch and execute all (new) commands in the DMA buffer */ /* tell the engine to fetch and execute all (new) commands in the DMA buffer */
nv_start_dma(); nv_start_dma();