arm64: Set MMU granule sizes to a consistent value in bootloader.
Change-Id: Ia36885df6dec5ac0ac9ce41271115aa7a8c3e6df Reviewed-on: https://review.haiku-os.org/c/haiku/+/8418 Reviewed-by: waddlesplash <[email protected]> Tested-by: Commit checker robot <[email protected]>
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waddlesplash
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@@ -607,10 +607,17 @@
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#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
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#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
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#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
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#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
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#define TCR_TG0_SHIFT 14
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#define TCR_TG0_4K (0 << TCR_TG0_SHIFT)
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#define TCR_TG0_64K (1 << TCR_TG0_SHIFT)
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#define TCR_TG0_16K (2 << TCR_TG0_SHIFT)
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#define TCR_TG0_MASK (3 << TCR_TG0_SHIFT)
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
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#define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
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#define TCR_TG1_MASK (3 << TCR_TG1_SHIFT)
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#define TCR_SH1_SHIFT 28
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#define TCR_SH1_SHIFT 28
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#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
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#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
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@@ -204,8 +204,6 @@ static inline uint32 arch_mmu_user_address_bits()
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static inline uint32 arch_mmu_user_granule()
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static inline uint32 arch_mmu_user_granule()
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{
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{
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static constexpr uint64 TCR_TG0_SHIFT = 14u;
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uint64 reg = _arch_mmu_get_tcr();
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uint64 reg = _arch_mmu_get_tcr();
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return ((reg >> TCR_TG0_SHIFT) & TG_MASK);
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return ((reg >> TCR_TG0_SHIFT) & TG_MASK);
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}
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}
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@@ -122,6 +122,12 @@ void arch_mmu_setup_EL1(uint64 tcr) {
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// TODO: Compiler dependency?
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// TODO: Compiler dependency?
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tcr |= TCR_T1SZ(__builtin_popcountl(KERNEL_BASE));
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tcr |= TCR_T1SZ(__builtin_popcountl(KERNEL_BASE));
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// Set granule sizes to 4KB
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tcr &= ~TCR_TG0_MASK;
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tcr |= TCR_TG0_4K;
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tcr &= ~TCR_TG1_MASK;
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tcr |= TCR_TG1_4K;
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// Set the maximum PA size to the maximum supported by the hardware.
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// Set the maximum PA size to the maximum supported by the hardware.
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uint64_t pa_size = READ_SPECIALREG(ID_AA64MMFR0_EL1) & ID_AA64MMFR0_PA_RANGE_MASK;
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uint64_t pa_size = READ_SPECIALREG(ID_AA64MMFR0_EL1) & ID_AA64MMFR0_PA_RANGE_MASK;
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