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Updated radeon driver to the latest BeBits release 5.1.0.1.

Browse Source 
Probably only works under Haiku due to the new area flags.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12219 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2005-04-01 14:16:38 +00:00
parent eb2068515f
commit e02e12de8a
46 changed files with 3357 additions and 1550 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/radeon/accelerant_ext.h
+3 -4
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@@ -15,8 +15,6 @@
// additional timing flags for GetMode/SetMode
enum {
RADEON_MODE_STANDARD = 0 << 16,
RADEON_MODE_MIRROR = 1 << 16,
RADEON_MODE_CLONE = 2 << 16,
RADEON_MODE_COMBINE = 3 << 16,
RADEON_MODE_MASK = 7 << 16,
@@ -32,8 +30,9 @@ enum {
// operation codes tunneled via ProposeDisplayMode
typedef enum {
ms_swap,
ms_overlay_port
ms_swap = 'sw',
ms_use_laptop_panel = 'up',
ms_tv_standard = 'tv'
} multi_mon_settings;
headers/private/graphics/radeon/crtc_regs.h
-23
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@@ -137,27 +137,4 @@
#define RADEON_CUR2_OFFSET 0x0360
# define RADEON_CUR2_LOCK (1 << 31)
#define RADEON_GRPH_BUFFER_CNTL 0x02f0
# define RADEON_GRPH_START_REQ_MASK (0x7f)
# define RADEON_GRPH_START_REQ_SHIFT 0
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH_STOP_REQ_SHIFT 8
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH_BUFFER_SIZE (1<<29)
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH_STOP_CNTL (1<<31)
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
# define RADEON_GRPH2_START_REQ_MASK (0x7f)
# define RADEON_GRPH2_START_REQ_SHIFT 0
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH2_STOP_REQ_SHIFT 8
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH2_STOP_CNTL (1<<31)
#endif
headers/private/graphics/radeon/dac_regs.h
+35 -6
View File
@@ -17,6 +17,7 @@
# define RADEON_DAC_CMP_EN (1 << 3)
# define RADEON_DAC_CMP_OUTPUT (1 << 7)
# define RADEON_DAC_8BIT_EN (1 << 8)
# define RADEON_DAC_TVO_EN (1 << 10)
# define RADEON_DAC_VGA_ADR_EN (1 << 13)
# define RADEON_DAC_PDWN (1 << 15)
# define RADEON_DAC_MASK_ALL (0xff << 24)
@@ -57,12 +58,40 @@
#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
# define RADEON_DISP_DAC_SOURCE_MASK 0x03
# define RADEON_DISP_DAC_SOURCE_CRTC1 0x00
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
# define RADEON_DISP_DAC_SOURCE_RMX 0x02
# define RADEON_DISP_TVDAC_SOURCE_MASK 0x0c
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 0x04
# define RADEON_DISP_DAC_SOURCE_MASK 3
# define RADEON_DISP_DAC_SOURCE_CRTC1 0
# define RADEON_DISP_DAC_SOURCE_CRTC2 1
# define RADEON_DISP_DAC_SOURCE_RMX 2
# define RADEON_DISP_TVDAC_SOURCE_MASK (3 << 2)
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (1 << 2)
# define RADEON_DISP_TV_SOURCE (1 << 16)
# define RADEON_DISP_TV_MODE_MASK (3 << 17)
# define RADEON_DISP_TV_MODE_888 (0 << 17)
# define RADEON_DISP_TV_MODE_565 (1 << 17)
# define RADEON_DISP_TV_YG_DITH_EN (1 << 19)
# define RADEON_DISP_TV_CBB_CRR_DITH_EN (1 << 20)
# define RADEON_DISP_TV_BIT_WIDTH (1 << 21)
# define RADEON_DISP_TV_SYNC_MODE_SHIFT 22
# define RADEON_DISP_TV_SYNC_MODE_MASK (3 << 22)
# define RADEON_DISP_TV_SYNC_COLOR_MASK (3 << 25)
#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
# define RADEON_DISP_TV_OUT_YG_FILTER_MASK (3 << 0)
# define RADEON_DISP_TV_OUT_YG_SAMPLE (1 << 2)
# define RADEON_DISP_TV_OUT_CrR_FILTER_MASK (3 << 4)
# define RADEON_DISP_TV_OUT_CrR_SAMPLE (1 << 6)
# define RADEON_DISP_TV_OUT_CbB_FILTER_MASK (3 << 8)
# define RADEON_DISP_TV_OUT_CbB_SAMPLE (1 << 10)
# define RADEON_DISP_TV_SUBSAMPLE_CNTL_MASK (3 << 12)
# define RADEON_DISP_TV_H_DOWNSCALE (1 << 15)
# define RADEON_DISP_TV_PATH_SRC (1 << 16)
# define RADEON_DISP_TV_COLOR_SPACE (1 << 17)
# define RADEON_DISP_TV_DITH_MODE (1 << 18)
# define RADEON_DISP_TV_DATA_ZERO_SEL (1 << 19)
# define RADEON_DISP_TV_CLKO_SEL (1 << 20)
# define RADEON_DISP_TV_CLKO_OUT_EN (1 << 21)
# define RADEON_DISP_TV_DOWNSCALE_CNTL (3 << 24)
#define RADEON_DISP_HW_DEBUG 0x0d14
# define RADEON_CRT2_DISP1_SEL (1 << 5)
headers/private/graphics/radeon/memcntrl_regs.h
+23
View File
@@ -25,4 +25,27 @@
#define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c
#define RADEON_OV0_BASE_ADDRESS 0x043c
#define RADEON_GRPH_BUFFER_CNTL 0x02f0
# define RADEON_GRPH_START_REQ_MASK (0x7f)
# define RADEON_GRPH_START_REQ_SHIFT 0
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH_STOP_REQ_SHIFT 8
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH_BUFFER_SIZE (1<<29)
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH_STOP_CNTL (1<<31)
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
# define RADEON_GRPH2_START_REQ_MASK (0x7f)
# define RADEON_GRPH2_START_REQ_SHIFT 0
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH2_STOP_REQ_SHIFT 8
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH2_STOP_CNTL (1<<31)
#endif
headers/private/graphics/radeon/multimon.h
+8
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@@ -14,6 +14,14 @@ class BScreen;
status_t GetSwapDisplays( BScreen *screen, bool *swap );
status_t SetSwapDisplays( BScreen *screen, bool swap );
status_t GetUseLaptopPanel( BScreen *screen, bool *use );
status_t SetUseLaptopPanel( BScreen *screen, bool use );
status_t GetNthSupportedTVStandard( BScreen *screen, int idx, uint32 *standard );
status_t GetTVStandard( BScreen *screen, uint32 *standard );
status_t SetTVStandard( BScreen *screen, uint32 standard );
status_t TestMultiMonSupport( BScreen *screen );
#endif
headers/private/graphics/radeon/pll_regs.h
+4 -2
View File
@@ -47,12 +47,14 @@
# define RADEON_VCLK_SRC_PSCAN_CLK (1 << 0)
# define RADEON_VCLK_SRC_BYTE_CLK (2 << 0)
# define RADEON_VCLK_SRC_PPLL_CLK (3 << 0)
# define RADEON_PIXCLK_ALWAYS_ONb (1 << 6) // negated
# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1 << 7) // negated
# define RADEON_ECP_DIV_SHIFT 8
# define RADEON_ECP_DIV_MASK (3 << 8)
# define RADEON_ECP_DIV_VCLK (0 << 8)
# define RADEON_ECP_DIV_VCLK_2 (1 << 8)
# define RADEON_PIXCLK_ALWAYS_ONb (1 << 6) // negated
# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1 << 7) // negated
# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT 16
# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_MASK (3 << 16)
#define RADEON_HTOTAL_CNTL 0x0009
#define RADEON_SCLK_CNTL 0x000d
# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
headers/private/graphics/radeon/radeon_interface.h
+36 -170
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@@ -102,14 +102,16 @@ typedef enum {
rt_rs200, // IGP 330M/340M/350M
rt_r200, // Radeon 8500/9100
rt_rv250, // Radeon 9000
rt_rv280, // Radeon 9200
rt_m9, // mobile Radeon 9000
rt_rv280, // Radeon 9200
rt_m9plus, // mobile Radeon 9200
// from here on, r300 and up must be located as ATI modified the PLL
// with r300 and the code only tests for >= rt_r300
rt_r300, // Radeon 9700
rt_r300_4p, // Radeon 9500
rt_rv350, // Radeon 9600
rt_m10, // mobile Radeon 9600
rt_rv360, // Radeon 9600
rt_r350, // Radeon 9800
rt_r360 // Radeon 9800
@@ -118,13 +120,15 @@ typedef enum {
// TV standard
typedef enum {
ts_off,
ts_ntsc,
ts_pal,
ts_palm,
ts_palcn,
ts_pal_bdghi,
ts_pal_m,
ts_pal_nc,
ts_scart_pal,
ts_pal60
} tv_standard;
ts_pal_60,
ts_max = ts_pal_60
} tv_standard_e;
// type of TV-Chip
@@ -151,13 +155,6 @@ typedef struct {
} cursor_info;
// head as seen by accelerant
typedef struct {
int physical_head; // idx of physical head
uint32 rel_x, rel_y; // relative position in multi-monitor mode
} virtual_head;
// info about flat panel connected to LVDS or DVI port
typedef struct {
uint panel_pwr_delay;
@@ -175,16 +172,18 @@ typedef struct {
} fp_info;
// physical head
// crtc info
typedef struct {
bool is_crtc2; // true, if connected to crtc2
display_device_e active_displays; // currently driven displays
display_device_e chosen_displays; // displays to be driven by next mode switch
sem_id vblank; // vertical blank interrupt semaphore
bool cursor_on_screen; // cursor is visible on this head
display_mode mode; // display mode of this head
//bool is_crtc2; // true, if crtc2
int8 flatpanel_port; // linked flat panel port (-1 if none)
} physical_head;
bool cursor_on_screen; // cursor is visible on this head
int crtc_idx; // index of CRTC
display_device_e active_displays; // currently driven displays
display_device_e chosen_displays; // displays to be driven after next mode switch
sem_id vblank; // vertical blank interrupt semaphore
uint32 rel_x, rel_y; // relative position in multi-monitor mode
display_mode mode; // display mode of this head
} crtc_info;
// info about PLLs on graphics card as retrieved from BIOS
@@ -220,146 +219,6 @@ typedef struct {
} pll_info;
// PLL divider values
typedef struct {
uint32 post_code; // code for post divider
uint32 post; // value of post divider
uint32 extra_post_code; // code for extra post divider
uint32 extra_post; // value of extra post divider
uint32 ref; // reference divider
uint32 feedback; // feedback divider
uint32 freq; // resulting frequency
} pll_dividers;
// TV-Out parameters
typedef struct {
uint16 y_accum_init;
uint16 uv_accum_init;
uint16 uv_inc;
uint16 h_inc;
uint32 tv_clocks_to_active;
uint16 f_restart;
uint16 v_restart;
uint16 h_restart;
bool mode888;
uint16 y_saw_tooth_slope;
uint16 y_saw_tooth_amp;
uint16 y_rise_accum_init;
uint16 y_fall_accum_init;
bool y_coeff_enable;
uint8 y_coeff_value;
pll_dividers tv_dividers;
pll_dividers crt_dividers;
} tv_params;
// TV-timing
typedef struct {
uint32 freq; // TV sub carrier frequency x12
uint16 h_total;
uint16 h_sync_len;
uint16 h_genclk_delay;
uint16 h_setup_delay;
uint16 h_active_delay;
uint16 h_active_len;
uint16 v_total;
uint16 v_active_lines;
uint16 v_field_total;
uint16 v_fields;
uint16 f_total;
uint16 frame_size_adjust;
uint32 scale;
} tv_timing;
// list of register content (used for mode changes)
typedef struct {
// CRTC regs
uint32 crtc_h_total_disp;
uint32 crtc_h_sync_strt_wid;
uint32 crtc_v_total_disp;
uint32 crtc_v_sync_strt_wid;
uint32 crtc_pitch;
uint32 crtc_gen_cntl;
uint32 crtc_ext_cntl;
uint32 crtc_offset_cntl;
// RMX registers
uint32 fp_horz_stretch;
uint32 fp_vert_stretch;
// Flat panel regs
uint32 fp_gen_cntl;
uint32 fp_panel_cntl;
uint32 lvds_gen_cntl;
uint32 fp_h_sync_strt_wid;
uint32 fp_v_sync_strt_wid;
uint32 fp2_gen_cntl;
uint32 fp2_h_sync_strt_wid;
uint32 fp2_v_sync_strt_wid;
// DAC regs
uint32 dac_cntl2;
uint32 dac_cntl;
uint32 disp_hw_debug;
// PLL regs
uint32 ppll_div_3;
uint32 ppll_ref_div;
uint32 htotal_cntl;
// pure information
uint32 dot_clock_freq; // in 10 kHz
uint32 pll_output_freq;// in 10 kHz
int feedback_div;
int post_div;
// Common regs
uint32 surface_cntl;
uint32 disp_output_cntl;
// TV-Out registers
uint32 tv_ftotal;
uint32 tv_vscaler_cntl1;
uint32 tv_y_saw_tooth_cntl;
uint32 tv_y_fall_cntl;
uint32 tv_y_rise_cntl;
uint32 tv_vscaler_cntl2;
uint32 tv_hrestart;
uint32 tv_vrestart;
uint32 tv_frestart;
uint32 tv_tv_pll_cntl;
uint32 tv_crt_pll_cntl;
uint32 tv_clock_sel_cntl;
uint32 tv_clkout_cntl;
uint32 tv_htotal;
uint32 tv_hsize;
uint32 tv_hdisp;
uint32 tv_hstart;
uint32 tv_vtotal;
uint32 tv_vdisp;
uint32 tv_sync_size;
uint32 tv_timing_cntl;
uint32 tv_dac_cntl; // affects CRT connected to TV-DAC
uint32 tv_modulator_cntl1;
uint32 tv_modulator_cntl2;
uint32 tv_data_delay_a;
uint32 tv_data_delay_b;
uint32 tv_frame_lock_cntl;
uint32 tv_pll_cntl1;
uint32 tv_rgb_cntl;
uint32 tv_pre_dac_mux_cntl;
uint32 tv_master_cntl;
uint32 tv_uv_adr;
uint32 tv_pll_fine_cntl;
} port_regs;
// one overlay buffer
typedef struct overlay_buffer_node {
struct overlay_buffer_node *next, *prev;
@@ -382,7 +241,7 @@ typedef struct {
overlay_buffer_node *on; // current buffer
overlay_buffer_node *prev_on; // previous buffer (for temporal deinterlace, currently unused)
int8 head; // physical head where the overlay is shown on
int crtc_idx; // crtc where the overlay is shown on
uint32 rel_offset; // offset of overlay source due to clipping
} overlay_info;
@@ -393,8 +252,11 @@ typedef struct {
typedef struct {
uint32 id; // identifier used to know which card the 2D accelerator
// is prepared for (we use area_id of this structure)
virtual_head heads[2]; // heads assigned to virtual card
uint8 num_heads; // number of heads assigned to virtual card
bool assigned_crtc[2]; // mask of heads assigned to virtual card
bool used_crtc[2]; // mask of heads assigned to virtual card
display_device_e controlled_displays; // displays devices controlled byvc
display_device_e connected_displays; // bit-field of connected displays
int8 independant_heads; // number of heads to be programmed independantly
int8 different_heads; // number of heads showing different parts of framebuffer
@@ -410,9 +272,12 @@ typedef struct {
cursor_info cursor;
multi_mode_e wanted_multi_mode; // multi monitor mode as requested by user
bool swap_displays; // true to swap monitors
bool use_laptop_panel; // true to always use laptop panel
tv_standard_e tv_standard; // standard to use for TV Out
bool enforce_mode_change; // set to make sure next display mode change
// is executed even if display mode seems to be
// still the same
frame_buffer_config fbc; // data for direct frame buffer access
@@ -528,6 +393,7 @@ typedef struct {
radeon_type asic; // ASIC version
bool is_mobility; // mobility version
tv_chip_type tv_chip; // type of TV-Out encoder
bool new_pll; // r300 style PLL
uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable)
@@ -539,11 +405,9 @@ typedef struct {
void *framebuffer_pci; // physical address of frame buffer (aka local memory)
// this is a hack needed by BeOS
physical_head heads[2]; // physical heads
uint8 num_heads; // number of physical heads
crtc_info crtc[2]; // info about each crtc
uint8 num_crtc; // number of physical heads
display_device_e connected_displays; // bit-field of connected displays
fp_info flatpanels[2]; // info about connected flat panels (if any)
memory_type_info memory[mt_last]; // info about memory types
@@ -618,6 +482,7 @@ typedef struct {
uint channel; // channel, i.e. device
uint address; // address
uint32 data; // read data
bool lock; // true, if CP lock must be acquired
} radeon_vip_read;
// write VIP register
@@ -626,6 +491,7 @@ typedef struct {
uint channel; // channel, i.e. device
uint address; // address
uint32 data; // data to write
bool lock; // true, if CP lock must be acquired
} radeon_vip_write;
// find channel of device with given ID
headers/private/graphics/radeon/radeon_regs.h
+1 -3
View File
@@ -250,12 +250,10 @@
#define RADEON_TRAIL_X 0x1618
#define RADEON_TRAIL_X_SUB 0x1620
#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
#define RADEON_VGA_DDA_CONFIG 0x02e8
#define RADEON_VGA_DDA_CONFIG 0x02e8 // Rage 128 reg
#define RADEON_VGA_DDA_ON_OFF 0x02ec
#define RADEON_VID_BUFFER_CONTROL 0x0900
#define RADEON_VIDEOMUX_CNTL 0x0190
#define RADEON_VIPH_CONTROL 0x0c40 /* ? */
#define RADEON_OVR_CLR 0x0230
#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
headers/private/graphics/radeon/theatre_regs.h
+18
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@@ -58,6 +58,9 @@
#define THEATRE_VIP_Y_FALL_CNTL 0x01cc
#define THEATRE_VIP_Y_RISE_CNTL 0x01d0
#define THEATRE_VIP_Y_SAW_TOOTH_CNTL 0x01d4
#define THEATRE_VIP_UPSAMP_AND_GAIN_CNTL 0x01e0
#define THEATRE_VIP_GAIN_LIMIT_SETTINGS 0x01e4
#define THEATRE_VIP_LINEAR_GAIN_SETTINGS 0x01e8
#define THEATRE_VIP_MODULATOR_CNTL1 0x0200
#define THEATRE_VIP_MODULATOR_CNTL2 0x0204
#define THEATRE_VIP_PRE_DAC_MUX_CNTL 0x0240
@@ -67,6 +70,21 @@
#define THEATRE_VIP_VBI_20BIT_CNTL 0x02d0
#define THEATRE_VIP_VBI_LEVEL_CNTL 0x02d8
#define THEATRE_VIP_UV_ADR 0x0300
#define THEATRE_VIP_UPSAMP_COEFF0_0 0x0340
#define THEATRE_VIP_UPSAMP_COEFF0_1 0x0344
#define THEATRE_VIP_UPSAMP_COEFF0_2 0x0348
#define THEATRE_VIP_UPSAMP_COEFF1_0 0x034c
#define THEATRE_VIP_UPSAMP_COEFF1_1 0x0350
#define THEATRE_VIP_UPSAMP_COEFF1_2 0x0354
#define THEATRE_VIP_UPSAMP_COEFF2_0 0x0358
#define THEATRE_VIP_UPSAMP_COEFF2_1 0x035c
#define THEATRE_VIP_UPSAMP_COEFF2_2 0x0360
#define THEATRE_VIP_UPSAMP_COEFF3_0 0x0364
#define THEATRE_VIP_UPSAMP_COEFF3_1 0x0368
#define THEATRE_VIP_UPSAMP_COEFF3_2 0x036c
#define THEATRE_VIP_UPSAMP_COEFF4_0 0x0370
#define THEATRE_VIP_UPSAMP_COEFF4_1 0x0374
#define THEATRE_VIP_UPSAMP_COEFF4_2 0x0378
#define THEATRE_VIP_HSCALER_CONTROL 0x0600
#define THEATRE_VIP_VSCALER_CONTROL 0x0604
headers/private/graphics/radeon/tv_out_regs.h
+52 -4
View File
@@ -15,10 +15,13 @@
# define RADEON_TV_MASTER_CNTL_CRT_ASYNC_RST (1 << 1)
# define RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX (1 << 3)
# define RADEON_TV_MASTER_CNTL_TV_FIFO_ASYNC_RST (1 << 4)
# define RADEON_TV_MASTER_CNTL_VIN_ASYNC_RST (1 << 5)
# define RADEON_TV_MASTER_CNTL_AUD_ASYNC_RST (1 << 6)
# define RADEON_TV_MASTER_CNTL_DVS_ASYNC_RST (1 << 7)
# define RADEON_TV_MASTER_CNTL_CRT_FIFO_CE_EN (1 << 9)
# define RADEON_TV_MASTER_CNTL_TV_FIFO_CE_EN (1 << 10)
# define RADEON_TV_MASTER_CNTL_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TV_MASTER_CNTL_TV_CLK_ALWAYS_ONb (1 << 30)
# define RADEON_TV_MASTER_CNTL_TVCLK_ALWAYS_ONb (1 << 30)
# define RADEON_TV_MASTER_CNTL_TV_ON (1 << 31)
#define RADEON_TV_RGB_CNTL 0x0804
@@ -37,9 +40,24 @@
#define RADEON_TV_HRESTART 0x0838
#define RADEON_TV_VRESTART 0x083c
#define RADEON_TV_HOST_READ_DATA 0x0840
#define RADEON_TV_HOST_WRITE_DATA 0x0844
#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
# define RADEON_TV_HOST_RD_WT_CNTL_RD (1 << 12)
# define RADEON_TV_HOST_RD_WT_CNTL_RD_ACK (1 << 13)
# define RADEON_TV_HOST_RD_WT_CNTL_WT (1 << 14)
# define RADEON_TV_HOST_RD_WT_CNTL_WT_ACK (1 << 15)
#define RADEON_TV_VSCALER_CNTL1 0x084c
# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29)
# define RADEON_TV_VSCALER_CNTL1_UV_INC_SHIFT 0
# define RADEON_TV_VSCALER_CNTL1_UV_INC_MASK 0x0000ffff
# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_SHIFT 16
# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_MASK 0x003f0000
# define RADEON_TV_VSCALER_CNTL1_Y_W_EN (1 << 24)
# define RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT 26
# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29)
#define RADEON_TV_TIMING_CNTL 0x0850
# define RADEON_TV_TIMING_CNTL_UV_OUTPUT_POST_SCALE_SHIFT 24
@@ -57,18 +75,26 @@
# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_VALUE_SHIFT 24
#define RADEON_TV_Y_RISE_CNTL 0x085c
# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG 16
# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG (1 << 16)
#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
# define RADEON_TV_Y_SAW_TOOTH_CNTL_SLOPE_SHIFT 16
#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
#define RADEON_TV_MODULATOR_CNTL1 0x0870
# define RADEON_TV_MODULATOR_CNTL1_YFLT_EN (1 << 2)
# define RADEON_TV_MODULATOR_CNTL1_UVFLT_EN (1 << 3)
# define RADEON_TV_MODULATOR_CNTL1_ALT_PHASE_EN (1 << 6)
# define RADEON_TV_MODULATOR_CNTL1_SYNC_TIP_LEVEL (1 << 7)
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 18
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 8
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_MASK 0x00007f00
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_SHIFT 16
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_MASK 0x007f0000
# define RADEON_TV_MODULATOR_CNTL1_SLEW_RATE_LIMIT (1 << 23)
# define RADEON_TV_MODULATOR_CNTL1_CY_FILT_BLEND_SHIFT 28
#define RADEON_TV_MODULATOR_CNTL2 0x0874
# define TV_MODULATOR_CNTL2_U_BURST_LEVEL_MASK 0x1ff
@@ -90,6 +116,7 @@
# define RADEON_TV_DAC_CNTL_NBLANK (1 << 0)
# define RADEON_TV_DAC_CNTL_NHOLD (1 << 1)
# define RADEON_TV_DAC_CNTL_PEDESTAL (1 << 2)
# define RADEON_TV_DAC_CNTL_DASLEEP (1 << 3) // Theatre only
# define RADEON_TV_DAC_CNTL_DETECT (1 << 4)
# define RADEON_TV_DAC_CNTL_CMPOUT (1 << 5)
# define RADEON_TV_DAC_CNTL_BGSLEEP (1 << 6)
@@ -99,11 +126,29 @@
# define RADEON_TV_DAC_CNTL_STD_RS343 (3 << 8)
# define RADEON_TV_DAC_CNTL_BGADJ_SHIFT 16
# define RADEON_TV_DAC_CNTL_DACADJ_SHIFT 20
# define RADEON_TV_DAC_CNTL_RDACPD (1 << 24)
# define RADEON_TV_DAC_CNTL_GDACPD (1 << 25)
# define RADEON_TV_DAC_CNTL_BDACPD (1 << 26)
# define RADEON_TV_DAC_CNTL_RDACDET (1 << 29)
# define RADEON_TV_DAC_CNTL_GDACDET (1 << 30)
# define RADEON_TV_DAC_CNTL_BDACDET (1 << 31)
#define RADEON_TV_CRC_CNTL 0x0890
#define RADEON_TV_UV_ADR 0x08ac
# define RADEON_TV_UV_ADR_MAX_UV_ADR_MASK 0x000000ff
# define RADEON_TV_UV_ADR_MAX_UV_ADR_SHIFT 0
# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_MASK 0x0000ff00
# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_SHIFT 8
# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_MASK 0x00ff0000
# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_SHIFT 16
# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_MASK 0x06000000
# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_SHIFT 25
# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_MASK 0x18000000
# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_SHIFT 27
#define RADEON_TV_MAX_FIFO_ADDR 0x1a7
#define RADEON_TV_MAX_FIFO_ADDR_INTERN 0x1ff
#define RADEON_TV_PLL_FINE_CNTL 0x20
@@ -138,4 +183,7 @@
# define RADEON_TV_PLL_CNTL1_TVPLL_TEST (1 << 31)
# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLK_SHIFT 2
# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLKD_SHIFT 8
#endif
headers/private/graphics/radeon/version.h
+1 -1
View File
@@ -8,4 +8,4 @@
*/
// current version
#define RADEON_DRIVER_VERSION "Version: 4.1.0.0"
#define RADEON_DRIVER_VERSION "Version: 5.1.0.1"