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Updated radeon driver to the latest BeBits release 5.1.0.1.

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Probably only works under Haiku due to the new area flags.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12219 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2005-04-01 14:16:38 +00:00
parent eb2068515f
commit e02e12de8a
46 changed files with 3357 additions and 1550 deletions
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headers/private/graphics/radeon/tv_out_regs.h
+52 -4
View File
@@ -15,10 +15,13 @@
# define RADEON_TV_MASTER_CNTL_CRT_ASYNC_RST (1 << 1)
# define RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX (1 << 3)
# define RADEON_TV_MASTER_CNTL_TV_FIFO_ASYNC_RST (1 << 4)
# define RADEON_TV_MASTER_CNTL_VIN_ASYNC_RST (1 << 5)
# define RADEON_TV_MASTER_CNTL_AUD_ASYNC_RST (1 << 6)
# define RADEON_TV_MASTER_CNTL_DVS_ASYNC_RST (1 << 7)
# define RADEON_TV_MASTER_CNTL_CRT_FIFO_CE_EN (1 << 9)
# define RADEON_TV_MASTER_CNTL_TV_FIFO_CE_EN (1 << 10)
# define RADEON_TV_MASTER_CNTL_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TV_MASTER_CNTL_TV_CLK_ALWAYS_ONb (1 << 30)
# define RADEON_TV_MASTER_CNTL_TVCLK_ALWAYS_ONb (1 << 30)
# define RADEON_TV_MASTER_CNTL_TV_ON (1 << 31)
#define RADEON_TV_RGB_CNTL 0x0804
@@ -37,9 +40,24 @@
#define RADEON_TV_HRESTART 0x0838
#define RADEON_TV_VRESTART 0x083c
#define RADEON_TV_HOST_READ_DATA 0x0840
#define RADEON_TV_HOST_WRITE_DATA 0x0844
#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
# define RADEON_TV_HOST_RD_WT_CNTL_RD (1 << 12)
# define RADEON_TV_HOST_RD_WT_CNTL_RD_ACK (1 << 13)
# define RADEON_TV_HOST_RD_WT_CNTL_WT (1 << 14)
# define RADEON_TV_HOST_RD_WT_CNTL_WT_ACK (1 << 15)
#define RADEON_TV_VSCALER_CNTL1 0x084c
# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29)
# define RADEON_TV_VSCALER_CNTL1_UV_INC_SHIFT 0
# define RADEON_TV_VSCALER_CNTL1_UV_INC_MASK 0x0000ffff
# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_SHIFT 16
# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_MASK 0x003f0000
# define RADEON_TV_VSCALER_CNTL1_Y_W_EN (1 << 24)
# define RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT 26
# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29)
#define RADEON_TV_TIMING_CNTL 0x0850
# define RADEON_TV_TIMING_CNTL_UV_OUTPUT_POST_SCALE_SHIFT 24
@@ -57,18 +75,26 @@
# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_VALUE_SHIFT 24
#define RADEON_TV_Y_RISE_CNTL 0x085c
# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG 16
# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG (1 << 16)
#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
# define RADEON_TV_Y_SAW_TOOTH_CNTL_SLOPE_SHIFT 16
#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
#define RADEON_TV_MODULATOR_CNTL1 0x0870
# define RADEON_TV_MODULATOR_CNTL1_YFLT_EN (1 << 2)
# define RADEON_TV_MODULATOR_CNTL1_UVFLT_EN (1 << 3)
# define RADEON_TV_MODULATOR_CNTL1_ALT_PHASE_EN (1 << 6)
# define RADEON_TV_MODULATOR_CNTL1_SYNC_TIP_LEVEL (1 << 7)
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 18
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 8
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_MASK 0x00007f00
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_SHIFT 16
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_MASK 0x007f0000
# define RADEON_TV_MODULATOR_CNTL1_SLEW_RATE_LIMIT (1 << 23)
# define RADEON_TV_MODULATOR_CNTL1_CY_FILT_BLEND_SHIFT 28
#define RADEON_TV_MODULATOR_CNTL2 0x0874
# define TV_MODULATOR_CNTL2_U_BURST_LEVEL_MASK 0x1ff
@@ -90,6 +116,7 @@
# define RADEON_TV_DAC_CNTL_NBLANK (1 << 0)
# define RADEON_TV_DAC_CNTL_NHOLD (1 << 1)
# define RADEON_TV_DAC_CNTL_PEDESTAL (1 << 2)
# define RADEON_TV_DAC_CNTL_DASLEEP (1 << 3) // Theatre only
# define RADEON_TV_DAC_CNTL_DETECT (1 << 4)
# define RADEON_TV_DAC_CNTL_CMPOUT (1 << 5)
# define RADEON_TV_DAC_CNTL_BGSLEEP (1 << 6)
@@ -99,11 +126,29 @@
# define RADEON_TV_DAC_CNTL_STD_RS343 (3 << 8)
# define RADEON_TV_DAC_CNTL_BGADJ_SHIFT 16
# define RADEON_TV_DAC_CNTL_DACADJ_SHIFT 20
# define RADEON_TV_DAC_CNTL_RDACPD (1 << 24)
# define RADEON_TV_DAC_CNTL_GDACPD (1 << 25)
# define RADEON_TV_DAC_CNTL_BDACPD (1 << 26)
# define RADEON_TV_DAC_CNTL_RDACDET (1 << 29)
# define RADEON_TV_DAC_CNTL_GDACDET (1 << 30)
# define RADEON_TV_DAC_CNTL_BDACDET (1 << 31)
#define RADEON_TV_CRC_CNTL 0x0890
#define RADEON_TV_UV_ADR 0x08ac
# define RADEON_TV_UV_ADR_MAX_UV_ADR_MASK 0x000000ff
# define RADEON_TV_UV_ADR_MAX_UV_ADR_SHIFT 0
# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_MASK 0x0000ff00
# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_SHIFT 8
# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_MASK 0x00ff0000
# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_SHIFT 16
# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_MASK 0x06000000
# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_SHIFT 25
# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_MASK 0x18000000
# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_SHIFT 27
#define RADEON_TV_MAX_FIFO_ADDR 0x1a7
#define RADEON_TV_MAX_FIFO_ADDR_INTERN 0x1ff
#define RADEON_TV_PLL_FINE_CNTL 0x20
@@ -138,4 +183,7 @@
# define RADEON_TV_PLL_CNTL1_TVPLL_TEST (1 << 31)
# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLK_SHIFT 2
# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLKD_SHIFT 8
#endif