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* Add preliminary support for one SandyBridge mobile integrated graphics device

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(the one in my new ThinkPad X1). The PLL is still off a bit so it has a few
  blurry stripes, but EDID and mode setting basically works.
* Starting with IronLake the north/south bridge or (G)MCH/ICH setup was moved
  into a platform control hub (PCH) which means that many registers previously
  located in the GMCH are now in the PCH and have a new address.
* I'm committing this mostly because this way the additions are more easy to
  follow. It is a bit messy and I'll clean it up more and possibly make it a
  bit more generic. Also most of these changes actually apply to IronLake and up
  and aren't SandyBridge specific, so a few of those additions will still get a
  broader scope and new chips will be added.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42839 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2011-10-13 09:07:33 +00:00
parent c6e876fc85
commit e436a27e5f
6 changed files with 249 additions and 62 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+62 -6
View File
@@ -18,13 +18,13 @@
#define VENDOR_ID_INTEL 0x8086
#define INTEL_TYPE_FAMILY_MASK 0xf000
#define INTEL_TYPE_GROUP_MASK 0xfff0
#define INTEL_TYPE_MODEL_MASK 0xffff
#define INTEL_TYPE_FAMILY_MASK 0x000f0000
#define INTEL_TYPE_GROUP_MASK 0x000ffff0
#define INTEL_TYPE_MODEL_MASK 0x000fffff
// families
#define INTEL_TYPE_7xx 0x1000
#define INTEL_TYPE_8xx 0x2000
#define INTEL_TYPE_9xx 0x4000
#define INTEL_TYPE_7xx 0x00010000
#define INTEL_TYPE_8xx 0x00020000
#define INTEL_TYPE_9xx 0x00040000
// groups
#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010)
#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020)
@@ -34,6 +34,7 @@
#define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200)
#define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400)
#define INTEL_TYPE_IGD (INTEL_TYPE_9xx | 0x0800)
#define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x1000)
// models
#define INTEL_TYPE_MOBILE 0x0008
#define INTEL_TYPE_915 (INTEL_TYPE_91x)
@@ -47,6 +48,8 @@
#define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
#define INTEL_TYPE_IGDG (INTEL_TYPE_IGD)
#define INTEL_TYPE_IGDGM (INTEL_TYPE_IGD | INTEL_TYPE_MOBILE)
#define INTEL_TYPE_SNBG (INTEL_TYPE_SNB)
#define INTEL_TYPE_SNBGM (INTEL_TYPE_SNB | INTEL_TYPE_MOBILE)
#define DEVICE_NAME "intel_extreme"
#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
@@ -218,6 +221,59 @@ struct intel_free_graphics_memory {
#define G4X_STOLEN_MEMORY_224MB 0xc0
#define G4X_STOLEN_MEMORY_352MB 0xd0
// PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup
// to a PCH based one, that means anything that used to communicate via (G)MCH
// registers needs to use different ones on PCH based platforms (Ironlake and
// up, SandyBridge, etc.).
#define PCH_DE_INTERRUPT_ENABLE 0x4400c // INTEL_INTERRUPT_ENABLED
#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 // INTEL_DISPLAY_A_ANALOG_PORT
#define PCH_DISPLAY_LVDS_PORT 0xe1180 // INTEL_DISPLAY_LVDS_PORT
#define PCH_I2C_IO_A 0xc5010 // INTEL_I2C_IO_A
#define PCH_I2C_IO_C 0xc5018 // INTEL_I2C_IO_C
#define PCH_DISPLAY_A_PLL 0xc6014 // INTEL_DISPLAY_A_PLL
#define PCH_DISPLAY_B_PLL 0xc6018 // INTEL_DISPLAY_B_PLL
#define PCH_DISPLAY_A_PLL_DIVISOR_0 0xc6040 // INTEL_DISPLAY_A_PLL_DIVISOR_0
#define PCH_DISPLAY_A_PLL_DIVISOR_1 0xc6044 // INTEL_DISPLAY_A_PLL_DIVISOR_1
#define PCH_DISPLAY_B_PLL_DIVISOR_0 0xc6048 // INTEL_DISPLAY_B_PLL_DIVISOR_0
#define PCH_DISPLAY_B_PLL_DIVISOR_1 0xc604c // INTEL_DISPLAY_B_PLL_DIVISOR_1
#define PCH_TRANSCODER_A_HTOTAL 0xe0000 // INTEL_DISPLAY_A_HTOTAL
#define PCH_TRANSCODER_A_HBLANK 0xe0004 // INTEL_DISPLAY_A_HBLANK
#define PCH_TRANSCODER_A_HSYNC 0xe0008 // INTEL_DISPLAY_A_HSYNC
#define PCH_TRANSCODER_A_VTOTAL 0xe000c // INTEL_DISPLAY_A_VTOTAL
#define PCH_TRANSCODER_A_VBLANK 0xe0010 // INTEL_DISPLAY_A_VBLANK
#define PCH_TRANSCODER_A_VSYNC 0xe0014 // INTEL_DISPLAY_A_VSYNC
#define PCH_TRANSCODER_B_HTOTAL 0xe1000 // INTEL_DISPLAY_B_HTOTAL
#define PCH_TRANSCODER_B_HBLANK 0xe1004 // INTEL_DISPLAY_B_HBLANK
#define PCH_TRANSCODER_B_HSYNC 0xe1008 // INTEL_DISPLAY_B_HSYNC
#define PCH_TRANSCODER_B_VTOTAL 0xe100c // INTEL_DISPLAY_B_VTOTAL
#define PCH_TRANSCODER_B_VBLANK 0xe1010 // INTEL_DISPLAY_B_VBLANK
#define PCH_TRANSCODER_B_VSYNC 0xe1014 // INTEL_DISPLAY_B_VSYNC
// SandyBridge (SNB)
#define SNB_GRAPHICS_MEMORY_CONTROL 0x50
#define SNB_STOLEN_MEMORY_MASK 0xf8
#define SNB_STOLEN_MEMORY_32MB (1 << 3)
#define SNB_STOLEN_MEMORY_64MB (2 << 3)
#define SNB_STOLEN_MEMORY_96MB (3 << 3)
#define SNB_STOLEN_MEMORY_128MB (4 << 3)
#define SNB_STOLEN_MEMORY_160MB (5 << 3)
#define SNB_STOLEN_MEMORY_192MB (6 << 3)
#define SNB_STOLEN_MEMORY_224MB (7 << 3)
#define SNB_STOLEN_MEMORY_256MB (8 << 3)
#define SNB_STOLEN_MEMORY_288MB (9 << 3)
#define SNB_STOLEN_MEMORY_320MB (10 << 3)
#define SNB_STOLEN_MEMORY_352MB (11 << 3)
#define SNB_STOLEN_MEMORY_384MB (12 << 3)
#define SNB_STOLEN_MEMORY_416MB (13 << 3)
#define SNB_STOLEN_MEMORY_448MB (14 << 3)
#define SNB_STOLEN_MEMORY_480MB (15 << 3)
#define SNB_STOLEN_MEMORY_512MB (16 << 3)
#define SNB_GTT_SIZE_MASK (3 << 8)
#define SNB_GTT_SIZE_NONE (0 << 8)
#define SNB_GTT_SIZE_1MB (1 << 8)
#define SNB_GTT_SIZE_2MB (2 << 8)
// graphics page translation table
#define INTEL_PAGE_TABLE_CONTROL 0x02020