From eb027537793a9f57d07dc87d86e482e51c8d4b2b Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Fri, 29 Jul 2011 06:10:52 +0000 Subject: [PATCH] * Little cleanup * Add missing Idle call for connectors * Reformulate blanking.. this should match what the register is after the GTF vesa call * Set FrameBuffer to card internal address git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42509 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../private/graphics/radeon_hd/radeon_hd.h | 1 + src/add-ons/accelerants/radeon_hd/lvds.cpp | 7 +++ src/add-ons/accelerants/radeon_hd/lvds.h | 1 + src/add-ons/accelerants/radeon_hd/mc.cpp | 3 +- src/add-ons/accelerants/radeon_hd/mode.cpp | 46 +++++++++---------- src/add-ons/accelerants/radeon_hd/tmds.cpp | 7 +++ src/add-ons/accelerants/radeon_hd/tmds.h | 1 + .../drivers/graphics/radeon_hd/radeon_hd.cpp | 2 + 8 files changed, 44 insertions(+), 24 deletions(-) diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h b/headers/private/graphics/radeon_hd/radeon_hd.h index f6973db6e2..f867546e1d 100644 --- a/headers/private/graphics/radeon_hd/radeon_hd.h +++ b/headers/private/graphics/radeon_hd/radeon_hd.h @@ -83,6 +83,7 @@ struct radeon_shared_info { addr_t frame_buffer_phys; // card PCI BAR address of FB area_id frame_buffer_area; // area of memory mapped FB + uint32 frame_buffer_int; // card internal FB location uint32 frame_buffer_size; // card internal FB aperture size uint8* frame_buffer; // virtual memory mapped FB diff --git a/src/add-ons/accelerants/radeon_hd/lvds.cpp b/src/add-ons/accelerants/radeon_hd/lvds.cpp index 7a7c449a9b..6c7e52793a 100644 --- a/src/add-ons/accelerants/radeon_hd/lvds.cpp +++ b/src/add-ons/accelerants/radeon_hd/lvds.cpp @@ -258,3 +258,10 @@ LVDSSet(uint8 lvdsIndex, display_mode *mode) return B_OK; } + + +void +LVDSAllIdle() +{ + LVDSPower(1, RHD_POWER_RESET); +} diff --git a/src/add-ons/accelerants/radeon_hd/lvds.h b/src/add-ons/accelerants/radeon_hd/lvds.h index 503942d00e..ce32696fd1 100644 --- a/src/add-ons/accelerants/radeon_hd/lvds.h +++ b/src/add-ons/accelerants/radeon_hd/lvds.h @@ -28,6 +28,7 @@ void LVDSVoltageControl(uint8 lvdsIndex); void LVDSPower(uint8 lvdsIndex, int command); status_t LVDSSet(uint8 lvdsIndex, display_mode *mode); +void LVDSAllIdle(); #endif /* RADEON_HD_LVDS_H */ diff --git a/src/add-ons/accelerants/radeon_hd/mc.cpp b/src/add-ons/accelerants/radeon_hd/mc.cpp index e25869c4c1..8c6244b0f7 100644 --- a/src/add-ons/accelerants/radeon_hd/mc.cpp +++ b/src/add-ons/accelerants/radeon_hd/mc.cpp @@ -65,9 +65,10 @@ MCFBSetup(uint32 newFbLocation, uint32 newFbSize) return B_OK; } - if (oldFbLocation >> 32) + if (oldFbLocation >> 32) { TRACE("%s: board claims to use a frame buffer address > 32-bits\n", __func__); + } uint32 idleState = MCIdle(); if (idleState > 0) { diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index eaec697ed0..970ea97d28 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -128,6 +128,7 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode, static void CardBlankSet(uint8 crtid, bool blank) { + return; int blackColorReg = crtid == 1 ? D2CRTC_BLACK_COLOR : D1CRTC_BLACK_COLOR; int blankControlReg @@ -149,34 +150,34 @@ CardFBSet(uint8 crtid, display_mode *mode) get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel); - #if 0 - // TMDSAllIdle // DVI / HDMI - // LVTMAAllIdle // DVI + LVDSAllIdle(); + // DVI / HDMI / LCD + TMDSAllIdle(); + // DVI / HDMI DACAllIdle(); + // VGA + + // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed + //uint64 fbAddress = gInfo->shared_info->frame_buffer_phys; + uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int; // Set the inital frame buffer location in the memory controler uint32 mcFbSize; - MCFBLocation(0, &mcFbSize); - MCFBSetup(Read32(OUT, R6XX_CONFIG_FB_BASE), mcFbSize); - #endif + MCFBLocation(fbAddressInt, &mcFbSize); + //MCFBSetup(gInfo->shared_info->frame_buffer_int, mcFbSize); Write32(CRT, regs->grphUpdate, (1<<16)); // Lock for update (isn't this normally the other way around on VGA? - // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed - uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys; - // Tell GPU which frame buffer address to draw from - Write32(CRT, regs->grphPrimarySurfaceAddr, - fbAddress & 0xffffffff); - Write32(CRT, regs->grphSecondarySurfaceAddr, - fbAddress & 0xffffffff); + Write32(CRT, regs->grphPrimarySurfaceAddr, fbAddressInt & 0xffffffff); + Write32(CRT, regs->grphSecondarySurfaceAddr, fbAddressInt & 0xffffffff); if (gInfo->shared_info->device_chipset >= (RADEON_R700 | 0x70)) { Write32(CRT, regs->grphPrimarySurfaceAddrHigh, - (fbAddress >> 32) & 0xf); + (fbAddressInt >> 32) & 0xf); Write32(CRT, regs->grphSecondarySurfaceAddrHigh, - (fbAddress >> 32) & 0xf); + (fbAddressInt >> 32) & 0xf); } Write32(CRT, regs->grphControl, 0); @@ -248,10 +249,9 @@ CardModeSet(uint8 crtid, display_mode *mode) displayTiming.h_total - 1); // Blanking - uint16 blankStart = MIN(displayTiming.h_sync_start, - displayTiming.h_display); - uint16 blankEnd = MAX(displayTiming.h_sync_end, - displayTiming.h_total); + uint16 blankStart = displayTiming.h_total - displayTiming.h_sync_start; + uint16 blankEnd = displayTiming.h_total + + displayTiming.h_display - displayTiming.h_sync_start; Write32(CRT, regs->crtHBlank, blankStart | (blankEnd << 16)); @@ -267,10 +267,10 @@ CardModeSet(uint8 crtid, display_mode *mode) Write32(CRT, regs->crtVTotal, displayTiming.v_total - 1); - blankStart = MIN(displayTiming.v_sync_start, - displayTiming.v_display); - blankEnd = MAX(displayTiming.v_sync_end, - displayTiming.v_total); + // Blanking + blankStart = displayTiming.v_total - displayTiming.v_sync_start; + blankEnd = displayTiming.v_total + + displayTiming.v_display - displayTiming.v_sync_start; Write32(CRT, regs->crtVBlank, blankStart | (blankEnd << 16)); diff --git a/src/add-ons/accelerants/radeon_hd/tmds.cpp b/src/add-ons/accelerants/radeon_hd/tmds.cpp index 2ecda5077f..1c84e3ce6f 100644 --- a/src/add-ons/accelerants/radeon_hd/tmds.cpp +++ b/src/add-ons/accelerants/radeon_hd/tmds.cpp @@ -224,3 +224,10 @@ TMDSSet(uint8 tmdsIndex, display_mode *mode) // TODO : HdmiSetMode(mode) return B_OK; } + + +void +TMDSAllIdle() +{ + TMDSPower(0, RHD_POWER_RESET); +} diff --git a/src/add-ons/accelerants/radeon_hd/tmds.h b/src/add-ons/accelerants/radeon_hd/tmds.h index 3d1f750227..f2b7eca59f 100644 --- a/src/add-ons/accelerants/radeon_hd/tmds.h +++ b/src/add-ons/accelerants/radeon_hd/tmds.h @@ -13,6 +13,7 @@ void TMDSVoltageControl(uint8 tmdsIndex); bool TMDSSense(uint8 tmdsIndex); status_t TMDSPower(uint8 tmdsIndex, int command); status_t TMDSSet(uint8 tmdsIndex, display_mode *mode); +void TMDSAllIdle(); #endif diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp index b8a37c36d2..17a5e41d30 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp +++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp @@ -99,6 +99,8 @@ radeon_hd_init(radeon_info &info) info.shared_info->frame_buffer_area = info.framebuffer_area; info.shared_info->frame_buffer_phys = info.pci->u.h0.base_registers[RHD_FB_BAR]; + info.shared_info->frame_buffer_int + = read32(info.registers + R6XX_CONFIG_FB_BASE); // Pull active monitor VESA EDID from boot loader edid1_info* edidInfo = (edid1_info*)get_boot_item(EDID_BOOT_INFO,