modified coldstart script execution for pins V5.16 and up: looks like we might be able to coldstart all nVidia cards after all (someday)..
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8942 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -21,6 +21,7 @@ static void getstrap_arch_nv10_20_30(void);
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static status_t pins2_read(uint8 *rom, uint32 offset);
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static status_t pins2_read(uint8 *rom, uint32 offset);
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static status_t pins3_6_read(uint8 *rom, uint32 offset);
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static status_t pins3_6_read(uint8 *rom, uint32 offset);
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab);
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab);
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static status_t coldstart_card_516_up(uint8* rom, uint16 init, uint16 ram_tab);
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static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab);
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static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab);
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static void log_pll(uint32 reg);
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static void log_pll(uint32 reg);
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static void setup_ram_config(uint8* rom, uint16 ram_tab);
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static void setup_ram_config(uint8* rom, uint16 ram_tab);
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@@ -125,7 +126,7 @@ static status_t pins2_read(uint8 *rom, uint32 offset)
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char* product_name = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]);
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char* product_name = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]);
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char* product_rev = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]);
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char* product_rev = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]);
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LOG(8,("INFO: init_1 $%04x, init_2 $%04x, size $%04x\n", init1, init2, init_size));
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LOG(8,("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size));
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LOG(8,("INFO: signon msg:\n%s\n", signon_msg));
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LOG(8,("INFO: signon msg:\n%s\n", signon_msg));
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LOG(8,("INFO: vendor name: %s\n", vendor_name));
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LOG(8,("INFO: vendor name: %s\n", vendor_name));
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LOG(8,("INFO: product name: %s\n", product_name));
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LOG(8,("INFO: product name: %s\n", product_name));
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@@ -146,34 +147,48 @@ static status_t pins3_6_read(uint8 *rom, uint32 offset)
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char* product_name = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]);
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char* product_name = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]);
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char* product_rev = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]);
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char* product_rev = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]);
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LOG(8,("INFO: init_1 $%04x, init_2 $%04x, size $%04x\n", init1, init2, init_size));
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LOG(8,("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size));
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LOG(8,("INFO: signon msg:\n%s\n", signon_msg));
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LOG(8,("INFO: signon msg:\n%s\n", signon_msg));
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LOG(8,("INFO: vendor name: %s\n", vendor_name));
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LOG(8,("INFO: vendor name: %s\n", vendor_name));
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LOG(8,("INFO: product name: %s\n", product_name));
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LOG(8,("INFO: product name: %s\n", product_name));
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LOG(8,("INFO: product rev: %s\n", product_rev));
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LOG(8,("INFO: product rev: %s\n", product_rev));
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/* pins 5.16 and higher only contain PLL VCO range info */
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//fixme: extract RAM and core speeds from startscripts..
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//fixme: add 'parsing scripts while not actually executing' as warmstart method,
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// instead of not parsing at all: this will update the driver's speeds
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// as below, while logging the scripts as well (for our learning pleasure :)
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/* pins 5.16 and higher is more extensive, and works differently from before */
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if (((rom[offset + 5]) >= 5) && ((rom[offset + 6]) >= 0x10))
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if (((rom[offset + 5]) >= 5) && ((rom[offset + 6]) >= 0x10))
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{
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{
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/* get PLL VCO range info */
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uint32 fvco_max = *((uint32*)(&(rom[offset + 67])));
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uint32 fvco_max = *((uint32*)(&(rom[offset + 67])));
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uint32 fvco_min = *((uint32*)(&(rom[offset + 71])));
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uint32 fvco_min = *((uint32*)(&(rom[offset + 71])));
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LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max));
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LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max));
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/* modify presets to reflect card capability */
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/* modify presets to reflect card capability */
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// si->ps.min_video_vco = fvco_min / 1000;
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//fixme: setup and modify PLL code...
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// si->ps.max_video_vco = fvco_max / 1000;
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//si->ps.min_system_vco = fvco_min / 1000;
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//si->ps.max_system_vco = fvco_max / 1000;
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//si->ps.min_pixel_vco = fvco_min / 1000;
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//si->ps.max_pixel_vco = fvco_max / 1000;
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//si->ps.min_video_vco = fvco_min / 1000;
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//si->ps.max_video_vco = fvco_max / 1000;
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/* only pins 5 contains this info */
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/* pins 5.16 and up have a more extensive command list table, and have more
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//fixme: not finished..
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* commands to choose from as well. */
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/* if ((rom[offset + 5]) == 5)
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//fixme: how about pins 6???
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{
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init1 = rom[offset + 75] + (rom[offset + 76] * 256);
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uint16 IOFlagConditionTablePointer =
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LOG(8,("INFO: PINS 5.16 and later cmdlist pointer: $%04x\n", init1));
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rom[offset + 85] + (rom[offset + 86] * 256);
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return coldstart_card_516_up(rom, init1, ram_tab);
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}
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}
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*/ }
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else
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{
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return coldstart_card(rom, init1, init2, init_size, ram_tab);
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/* pre 'pins 5.16' still uses the 'old' method in which the command list
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* table always has two entries. */
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return coldstart_card(rom, init1, init2, init_size, ram_tab);
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}
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}
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}
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab)
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab)
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@@ -244,6 +259,87 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
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return result;
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return result;
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}
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}
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static status_t coldstart_card_516_up(uint8* rom, uint16 init, uint16 ram_tab)
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{
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status_t result = B_OK;
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uint16 adress;
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LOG(8,("INFO: executing coldstart...\n"));
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/* select colormode CRTC registers base adresses */
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NV_REG8(NV8_MISCW) = 0xcb;
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/* unknown.. */
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NV_REG8(NV8_VSE2) = 0x01;
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/* enable access to primary head */
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set_crtc_owner(0);
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/* unlock head's registers for R/W access */
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CRTCW(LOCK, 0x57);
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CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
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/* disable RMA as it's not used */
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/* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers
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* and framebuffer via legacy ISA I/O space.) */
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CRTCW(RMA, 0x00);
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if (si->ps.secondary_head)
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{
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/* enable access to secondary head */
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set_crtc_owner(1);
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/* unlock head's registers for R/W access */
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CRTC2W(LOCK, 0x57);
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CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
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}
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/* turn off both displays and the hardcursors (also disables transfers) */
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nv_crtc_dpms(false, false, false);
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nv_crtc_cursor_hide();
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if (si->ps.secondary_head)
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{
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nv_crtc2_dpms(false, false, false);
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nv_crtc2_cursor_hide();
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}
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/* execute all BIOS coldstart script(s) */
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if (init)
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{
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//fixme: setup new parser instead of misusing the old one...
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int16 size = 32767;
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adress = *((uint16*)(&(rom[init])));
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if (!adress)
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{
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LOG(8,("INFO: no cmdlist found!\n"));
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result = B_ERROR;
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}
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while (adress && (result == B_OK))
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{
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result = exec_type1_script(rom, adress, &size, ram_tab);
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/* next command script, please */
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init += 2;
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adress = *((uint16*)(&(rom[init])));
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}
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/* now enable ROM shadow or the card will remain shut-off! */
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NV_REG32(0x00001800 + NVCFG_ROMSHADOW) |= 0x00000001;
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//temporary: should be called from setmode probably..
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nv_crtc_setup_fifo();
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}
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else
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{
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result = B_ERROR;
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}
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if (result != B_OK)
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LOG(8,("INFO: coldstart failed.\n"));
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else
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LOG(8,("INFO: coldstart execution completed OK.\n"));
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return result;
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}
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/* This routine is complete for pre-NV10. It's tested on a Elsa Erazor III with TNT2
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/* This routine is complete for pre-NV10. It's tested on a Elsa Erazor III with TNT2
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* (NV05) and on a no-name TNT2-M64. Both cards coldstart perfectly. */
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* (NV05) and on a no-name TNT2-M64. Both cards coldstart perfectly. */
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static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab)
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static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab)
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