intel_extreme: decoupled PIPE/eDP link programming from FDI train, fixed eDP pgm error.
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@@ -1248,31 +1248,31 @@ struct intel_free_graphics_memory {
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
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//(FDI) PIPE M/N DATA AND LINK VALUES (refreshrate)
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#define PCH_FDI_PIPE_A_DATA_M1 0x0030
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#define PCH_FDI_PIPE_A_DATA_M2 0x0038
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#define PCH_FDI_PIPE_B_DATA_M1 0x1030
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#define PCH_FDI_PIPE_B_DATA_M2 0x1038
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#define PCH_FDI_PIPE_C_DATA_M1 0x2030
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#define PCH_FDI_PIPE_C_DATA_M2 0x2038
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#define PCH_FDI_PIPE_A_DATA_N1 0x0034
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#define PCH_FDI_PIPE_A_DATA_N2 0x003c
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#define PCH_FDI_PIPE_B_DATA_N1 0x1034
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#define PCH_FDI_PIPE_B_DATA_N2 0x103c
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#define PCH_FDI_PIPE_C_DATA_N1 0x2034
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#define PCH_FDI_PIPE_C_DATA_N2 0x203c
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#define PCH_FDI_PIPE_A_LINK_M1 0x0040
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#define PCH_FDI_PIPE_A_LINK_M2 0x0048
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#define PCH_FDI_PIPE_B_LINK_M1 0x1040
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#define PCH_FDI_PIPE_B_LINK_M2 0x1048
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#define PCH_FDI_PIPE_C_LINK_M1 0x2040
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#define PCH_FDI_PIPE_C_LINK_M2 0x2048
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#define PCH_FDI_PIPE_A_LINK_N1 0x0044
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#define PCH_FDI_PIPE_A_LINK_N2 0x004c
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#define PCH_FDI_PIPE_B_LINK_N1 0x1044
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#define PCH_FDI_PIPE_B_LINK_N2 0x104c
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#define PCH_FDI_PIPE_C_LINK_N1 0x2044
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#define PCH_FDI_PIPE_C_LINK_N2 0x204c
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// FDI/PIPE M/N DATA AND LINK VALUES (refreshrate)
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#define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT)
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#define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT)
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#define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25)
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#define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0)
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