From ee75f8527bdc29acec852e55c3a28c76e76012e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Fran=C3=A7ois=20Revol?= <revol@free.fr>
Date: Thu, 25 Oct 2007 00:45:01 +0000
Subject: [PATCH] This should handle TLB flushing on m68k (it's called ATC
 though).

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22706 a95241bf-73f2-0310-859d-f6bbb57e9c96
---
 headers/private/kernel/arch/m68k/arch_cpu.h | 17 ++++++++-
 src/system/kernel/arch/m68k/arch_cpu.cpp    | 41 ++++++---------------
 2 files changed, 27 insertions(+), 31 deletions(-)

diff --git a/headers/private/kernel/arch/m68k/arch_cpu.h b/headers/private/kernel/arch/m68k/arch_cpu.h
index e99f71bb95..939de6503c 100644
--- a/headers/private/kernel/arch/m68k/arch_cpu.h
+++ b/headers/private/kernel/arch/m68k/arch_cpu.h
@@ -142,7 +142,7 @@ enum machine_state {
 	MSR_DATA_ADDRESS_TRANSLATION	= 1L << 4,		// DR
 };
 
-struct block_address_translation;
+//struct block_address_translation;
 
 typedef struct arch_cpu_info {
 	int null;
@@ -153,6 +153,8 @@ typedef struct arch_cpu_info {
 extern "C" {
 #endif
 
+#if 0
+//PPC stuff
 extern uint32 get_sdr1(void);
 extern void set_sdr1(uint32 value);
 extern uint32 get_sr(void *virtualAddress);
@@ -181,6 +183,7 @@ extern void get_dbat3(struct block_address_translation *bat);
 
 extern void reset_ibats(void);
 extern void reset_dbats(void);
+#endif
 
 //extern void sethid0(unsigned int val);
 //extern unsigned int getl2cr(void);
@@ -201,6 +204,12 @@ extern bool m68k_set_fault_handler(addr_t *handlerLocation, addr_t handler)
 }
 #endif
 
+#define m68k_nop() asm volatile("nop") /* flushes insn pipeline */
+#define pflush(addr) asm volatile("pflush (%0)" :: "a" (addr))
+#define pflusha() asm volatile("pflusha")
+//#define
+
+#if 0
 #define eieio()	asm volatile("eieio")
 #define isync() asm volatile("isync")
 #define tlbsync() asm volatile("tlbsync")
@@ -243,11 +252,17 @@ enum m68k_processor_version {
 	MPC7410		= 0x800c,
 	MPC8245		= 0x8081,
 };
+#endif
 
 
 /*
 	Use of (some) special purpose registers.
 
+	SRP[63-32]: current struct thread*
+	SRP[31-0] :
+	CAAR      : can we use it ??
+
+	PPC:
 	SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context
 	       structure
 	SPRG1: scratch
diff --git a/src/system/kernel/arch/m68k/arch_cpu.cpp b/src/system/kernel/arch/m68k/arch_cpu.cpp
index d1da694171..f824a36b4b 100644
--- a/src/system/kernel/arch/m68k/arch_cpu.cpp
+++ b/src/system/kernel/arch/m68k/arch_cpu.cpp
@@ -85,15 +85,13 @@ arch_cpu_sync_icache(void *address, size_t len)
 void 
 arch_cpu_invalidate_TLB_range(addr_t start, addr_t end)
 {
-	asm volatile("sync");
+	m68k_nop();
 	while (start < end) {
-		asm volatile("tlbie %0" :: "r" (start));
-		asm volatile("eieio");
-		asm volatile("sync");
+		pflush(start);
+		m68k_nop();
 		start += B_PAGE_SIZE;
 	}
-	asm volatile("tlbsync");
-	asm volatile("sync");
+	m68k_nop();
 }
 
 
@@ -102,39 +100,22 @@ arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)
 {
 	int i;
 
-	asm volatile("sync");
+	m68k_nop();
 	for (i = 0; i < num_pages; i++) {
 		asm volatile("tlbie %0" :: "r" (pages[i]));
-		asm volatile("eieio");
-		asm volatile("sync");
+		pflush(pages[i]);
+		m68k_nop();
 	}
-	asm volatile("tlbsync");
-	asm volatile("sync");
+	m68k_nop();
 }
 
 
 void 
 arch_cpu_global_TLB_invalidate(void)
 {
-	if (sHasTlbia) {
-		m68k_sync();
-		tlbia();
-		m68k_sync();
-	} else {
-		addr_t address = 0;
-		unsigned long i;
-
-		m68k_sync();
-		for (i = 0; i < 0x100000; i++) {
-			tlbie(address);
-			eieio();
-			m68k_sync();
-	
-			address += B_PAGE_SIZE;
-		}
-		tlbsync();
-		m68k_sync();
-	}
+	m68k_nop();
+	pflush();
+	m68k_nop();
 }