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intel_extreme: add haswell/skylake PLL calcs, no functional change yet.

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This commit is contained in:
Rudolf Cornelissen
2021-11-22 11:14:36 +00:00
parent 4106e3f146
commit efde34c2fc
6 changed files with 544 additions and 9 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+12 -1
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@@ -512,7 +512,7 @@ struct intel_free_graphics_memory {
#define LVDS_18BIT_DITHER (1UL << 25)
#define LVDS_PORT_EN (1UL << 31)
// PLL flags
// PLL flags (pre-DDI)
#define DISPLAY_PLL_ENABLED (1UL << 31)
#define DISPLAY_PLL_2X_CLOCK (1UL << 30)
#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
@@ -540,6 +540,17 @@ struct intel_free_graphics_memory {
#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
#define DISPLAY_PLL_PULSE_PHASE_SHIFT 9
// Skylake PLLs
#define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT)
#define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT)
// display
#define INTEL_DISPLAY_OFFSET 0x1000