diff --git a/src/add-ons/accelerants/nvidia/SetDisplayMode.c b/src/add-ons/accelerants/nvidia/SetDisplayMode.c index 639a5fa32a..258847d7d9 100644 --- a/src/add-ons/accelerants/nvidia/SetDisplayMode.c +++ b/src/add-ons/accelerants/nvidia/SetDisplayMode.c @@ -6,7 +6,7 @@ Other authors: Mark Watson, Apsed, - Rudolf Cornelissen 11/2002-10/2003 + Rudolf Cornelissen 11/2002-12/2003 */ #define MODULE_BIT 0x00200000 @@ -88,7 +88,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) // if (si->ps.secondary_head) g400_crtc2_dpms(0,0,0); /*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/ - startadd = si->fbc.frame_buffer - si->framebuffer; + startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; /* calculate and set new mode bytes_per_row */ nv_general_validate_pic_size (&target, &si->fbc.bytes_per_row); @@ -480,7 +480,7 @@ status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) { //fixme: seperate both heads: we need a secondary si->fbc! startadd = v_display_start * si->fbc.bytes_per_row; startadd += h_display_start * (colour_depth >> 3); - startadd += si->fbc.frame_buffer - si->framebuffer; + startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3); /* account for switched CRTC's */ diff --git a/src/add-ons/accelerants/nvidia/be_driver_proto.h b/src/add-ons/accelerants/nvidia/be_driver_proto.h index c3dc1b9c2c..5c1f741656 100644 --- a/src/add-ons/accelerants/nvidia/be_driver_proto.h +++ b/src/add-ons/accelerants/nvidia/be_driver_proto.h @@ -47,9 +47,9 @@ status_t SYNC_TO_TOKEN(sync_token *st); void SCREEN_TO_SCREEN_BLIT(engine_token *et, blit_params *list, uint32 count); void SCREEN_TO_SCREEN_TRANSPARENT_BLIT(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count); +void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT(engine_token *et, scaled_blit_params *list, uint32 count); void FILL_RECTANGLE(engine_token *et, uint32 color, fill_rect_params *list, uint32 count); void INVERT_RECTANGLE(engine_token *et, fill_rect_params *list, uint32 count); - void FILL_SPAN(engine_token *et, uint32 color, uint16 *list, uint32 count); /* video_overlay */ diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc.c b/src/add-ons/accelerants/nvidia/engine/nv_acc.c index ce4012e14c..9ad761e948 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc.c @@ -1,6 +1,6 @@ /* NV Acceleration functions */ /* Author: - Rudolf Cornelissen 8/2003-10/2003. + Rudolf Cornelissen 8/2003-12/2003. This code was possible thanks to the Linux NV driver. */ @@ -516,12 +516,12 @@ status_t nv_acc_init() case NV04A: case NV10A: /* location of active screen in framebuffer */ - ACCW(OFFSET0, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(OFFSET1, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(OFFSET2, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(OFFSET3, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(OFFSET4, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(OFFSET5, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(OFFSET4, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(OFFSET5, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); /* setup buffer pitch */ ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); @@ -533,10 +533,10 @@ status_t nv_acc_init() case NV20A: case NV30A: /* location of active screen in framebuffer */ - ACCW(NV20_OFFSET0, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(NV20_OFFSET1, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(NV20_OFFSET2, (si->fbc.frame_buffer - si->framebuffer)); - ACCW(NV20_OFFSET3, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(NV20_OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); + ACCW(NV20_OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); /* setup buffer pitch */ ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index 1d161033c7..630d50014f 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -9,7 +9,7 @@ #include "nv_std.h" //apsed #include "memory" -status_t test_ram(); +status_t test_ram(void); static status_t nvxx_general_powerup (void); static status_t nv_general_bios_to_powergraphics(void); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_i2c.c b/src/add-ons/accelerants/nvidia/engine/nv_i2c.c index d40d07377f..1e12005f7a 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_i2c.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_i2c.c @@ -9,13 +9,24 @@ * * Other authors: * Mark Watson 6/2000, - * Rudolf Cornelissen 12/2002 + * Rudolf Cornelissen 12/2002-12/2003 */ #define MODULE_BIT 0x00004000 #include "nv_std.h" +int i2c_set_lines(int clock, int data); +int i2c_get_data(void); +void i2c_start(void); +void i2c_stop(void); +void i2c_high(void); +void i2c_low(void); +int i2c_get_ack(void); +void i2c_send_ack(void); +int i2c_sendbyte(unsigned char data); +unsigned char i2c_readbyte(int ack_required); + /*which device on the bus is the MAVEN?*/ #define MAVEN_WRITE (0x1B<<1) #define MAVEN_READ ((0x1B<<1)|1) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_maventv.c b/src/add-ons/accelerants/nvidia/engine/nv_maventv.c index f99ba9976a..8bb0981700 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_maventv.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_maventv.c @@ -1,6 +1,6 @@ /* Authors: Mark Watson 2000, - Rudolf Cornelissen 1/2003-3/2003 + Rudolf Cornelissen 1/2003-12/2003 Thanx to Petr Vandrovec for writing matroxfb. */ @@ -20,6 +20,11 @@ typedef struct { float chroma_subcarrier; } gx50_maven_timing; +void gxx0_maventv_PAL_init(uint8* buffer); +void gxx0_maventv_NTSC_init(uint8* buffer); +void gx50_maventv_PAL_timing(gx50_maven_timing *m_timing); +void gx50_maventv_NTSC_timing(gx50_maven_timing *m_timing); + //fixme: setup fixed CRTC2 modes for all modes and block other modes: // - 640x480, 800x600, 1024x768 NTSC and PAL overscan compensated modes (desktop) // - 640x480, 720x480 NTSC and 768x576, 720x576 non-overscan compensated modes (video)