From f6623f4d99a12567feec0ec63f8336bb45585e4c Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Thu, 26 Nov 2015 22:57:57 -0600 Subject: [PATCH] intel_extreme: program both pll divisors --- src/add-ons/accelerants/intel_extreme/Pipes.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index 17425ac449..80a97533e5 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -185,11 +185,17 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock, write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8)); } + // XXX: For now we assume no LVDS downclocking and program the same divisor + // value to both divisor 0 (standard) and 1 (reduced divisor) if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) { write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_IGD_N_DIVISOR_MASK) | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); + write32(pllDivisorB, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) + & DISPLAY_PLL_IGD_N_DIVISOR_MASK) + | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) + & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); } else { write32(pllDivisorA, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK) @@ -197,6 +203,12 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock, & DISPLAY_PLL_M1_DIVISOR_MASK) | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); + write32(pllDivisorB, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) + & DISPLAY_PLL_N_DIVISOR_MASK) + | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) + & DISPLAY_PLL_M1_DIVISOR_MASK) + | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) + & DISPLAY_PLL_M2_DIVISOR_MASK)); } uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags;