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* fix TODO style due to ML

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* rename bpc to bitsPerChannel
* remove un-needed / unused PCI BAR reference
* no functional change


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42861 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-10-16 14:12:03 +00:00
parent 7117b2ea25
commit f66a1a8d71
7 changed files with 54 additions and 57 deletions
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src/add-ons/accelerants/radeon_hd/bios.cpp
+2 -7
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@@ -127,15 +127,10 @@ radeon_init_bios(uint8* bios)
atom_card_info->reg_read = Read32Cail; atom_card_info->reg_read = Read32Cail;
atom_card_info->reg_write = Write32Cail; atom_card_info->reg_write = Write32Cail;
if (false) { // use MMIO instead of PCI I/O BAR
// TODO : if rio_mem, use ioreg
//atom_card_info->ioreg_read = cail_ioreg_read;
//atom_card_info->ioreg_write = cail_ioreg_write;
} else {
TRACE("%s: Cannot find PCI I/O BAR; using MMIO\n", __func__);
atom_card_info->ioreg_read = Read32Cail; atom_card_info->ioreg_read = Read32Cail;
atom_card_info->ioreg_write = Write32Cail; atom_card_info->ioreg_write = Write32Cail;
}
atom_card_info->mc_read = _read32; atom_card_info->mc_read = _read32;
atom_card_info->mc_write = _write32; atom_card_info->mc_write = _write32;
atom_card_info->pll_read = _read32; atom_card_info->pll_read = _read32;
src/add-ons/accelerants/radeon_hd/display.cpp
+2 -1
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@@ -775,7 +775,8 @@ display_get_encoder_mode(uint32 connectorIndex)
return ATOM_ENCODER_MODE_LVDS; return ATOM_ENCODER_MODE_LVDS;
case VIDEO_CONNECTOR_DP: case VIDEO_CONNECTOR_DP:
// dig_connector = radeon_connector->con_priv; // dig_connector = radeon_connector->con_priv;
// if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) // if ((dig_connector->dp_sink_type
// == CONNECTOR_OBJECT_ID_DISPLAYPORT)
// || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { // || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
// return ATOM_ENCODER_MODE_DP; // return ATOM_ENCODER_MODE_DP;
// } // }
src/add-ons/accelerants/radeon_hd/mode.h
+1
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@@ -15,6 +15,7 @@
#include "gpu.h" #include "gpu.h"
#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC) #define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC)
#define D1_REG_OFFSET 0x0000 #define D1_REG_OFFSET 0x0000
src/add-ons/accelerants/radeon_hd/pll.cpp
+4 -4
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@@ -436,8 +436,8 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor); atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor);
uint32 bpc = 8; uint32 bitsPerChannel = 8;
// TODO : BPC == Digital Depth, EDID 1.4+ on digital displays // TODO: Digital Depth, EDID 1.4+ on digital displays
// isn't in Haiku edid common code? // isn't in Haiku edid common code?
switch (tableMinor) { switch (tableMinor) {
@@ -490,7 +490,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) // if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
// args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; // args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
switch (bpc) { switch (bitsPerChannel) {
case 8: case 8:
default: default:
args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
@@ -516,7 +516,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) // if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
// args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; // args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
switch (bpc) { switch (bitsPerChannel) {
case 8: case 8:
default: default:
args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;