* fix TODO style due to ML
* rename bpc to bitsPerChannel * remove un-needed / unused PCI BAR reference * no functional change git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42861 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -127,15 +127,10 @@ radeon_init_bios(uint8* bios)
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atom_card_info->reg_read = Read32Cail;
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atom_card_info->reg_write = Write32Cail;
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if (false) {
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// TODO : if rio_mem, use ioreg
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//atom_card_info->ioreg_read = cail_ioreg_read;
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//atom_card_info->ioreg_write = cail_ioreg_write;
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} else {
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TRACE("%s: Cannot find PCI I/O BAR; using MMIO\n", __func__);
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// use MMIO instead of PCI I/O BAR
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atom_card_info->ioreg_read = Read32Cail;
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atom_card_info->ioreg_write = Write32Cail;
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}
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atom_card_info->mc_read = _read32;
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atom_card_info->mc_write = _write32;
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atom_card_info->pll_read = _read32;
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@@ -775,7 +775,8 @@ display_get_encoder_mode(uint32 connectorIndex)
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return ATOM_ENCODER_MODE_LVDS;
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case VIDEO_CONNECTOR_DP:
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// dig_connector = radeon_connector->con_priv;
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// if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
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// if ((dig_connector->dp_sink_type
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// == CONNECTOR_OBJECT_ID_DISPLAYPORT)
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// || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
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// return ATOM_ENCODER_MODE_DP;
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// }
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@@ -15,6 +15,7 @@
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#include "gpu.h"
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#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC)
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#define D1_REG_OFFSET 0x0000
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@@ -436,8 +436,8 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor);
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uint32 bpc = 8;
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// TODO : BPC == Digital Depth, EDID 1.4+ on digital displays
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uint32 bitsPerChannel = 8;
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// TODO: Digital Depth, EDID 1.4+ on digital displays
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// isn't in Haiku edid common code?
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switch (tableMinor) {
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@@ -490,7 +490,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
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// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
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// args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
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switch (bpc) {
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switch (bitsPerChannel) {
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case 8:
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default:
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args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
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@@ -516,7 +516,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
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// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
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// args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
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switch (bpc) {
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switch (bitsPerChannel) {
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case 8:
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default:
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args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
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