From f6c32ce31051610c37d4978fbd27d588de6944d1 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <alex.vongluck@r1soft.com>
Date: Wed, 20 Jul 2016 00:25:38 -0500
Subject: [PATCH] intel_extreme: Set FDI PLL RX lane count when enabling

---
 .../graphics/intel_extreme/intel_extreme.h     |  4 ++++
 .../intel_extreme/FlexibleDisplayInterface.cpp | 18 +++++++++++++-----
 .../intel_extreme/FlexibleDisplayInterface.h   |  4 ++--
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index 839bdb44f0..ab4e025659 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -878,6 +878,10 @@ struct intel_free_graphics_memory {
 #define FDI_TX_ENHANCE_FRAME_ENABLE		(1 << 18)
 #define FDI_TX_PLL_ENABLED				(1 << 14)
 
+#define FDI_DP_PORT_WIDTH_SHIFT			19
+#define FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
+#define FDI_DP_PORT_WIDTH(width)		(((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
+
 #define FDI_PLL_BIOS_0					0x46000
 #define FDI_PLL_FB_CLOCK_MASK			0xff
 #define FDI_PLL_BIOS_1					0x46004
diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
index c21c6c30ca..f9d3ac067f 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
@@ -84,13 +84,14 @@ FDITransmitter::IsPLLEnabled()
 
 
 void
-FDITransmitter::EnablePLL()
+FDITransmitter::EnablePLL(uint32 lanes)
 {
 	CALLED();
 	uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
 	uint32 value = read32(targetRegister);
 	if ((value & FDI_TX_PLL_ENABLED) != 0) {
 		// already enabled, possibly IronLake where it always is
+		TRACE("%s: Already enabled.\n", __func__);
 		return;
 	}
 
@@ -169,13 +170,20 @@ FDIReceiver::IsPLLEnabled()
 
 
 void
-FDIReceiver::EnablePLL()
+FDIReceiver::EnablePLL(uint32 lanes)
 {
 	CALLED();
 	uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
 	uint32 value = read32(targetRegister);
-	if ((value & FDI_RX_PLL_ENABLED) != 0)
+	if ((value & FDI_RX_PLL_ENABLED) != 0) {
+		// already enabled, possibly IronLake where it always is
+		TRACE("%s: Already enabled.\n", __func__);
 		return;
+	}
+
+	value &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
+	value |= FDI_DP_PORT_WIDTH(lanes);
+	//value |= (read32(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
 
 	write32(targetRegister, value | FDI_RX_PLL_ENABLED);
 	read32(targetRegister);
@@ -248,9 +256,9 @@ FDILink::Train(display_mode* target)
 	TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, lanes);
 
 	// Enable FDI clocks
-	Receiver().EnablePLL();
+	Receiver().EnablePLL(lanes);
 	Receiver().SwitchClock(true);
-	Transmitter().EnablePLL();
+	Transmitter().EnablePLL(lanes);
 
 	status_t result = B_ERROR;
 
diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
index 33502ba076..8f6156f2b2 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
@@ -22,7 +22,7 @@ public:
 		void						Disable();
 
 		bool						IsPLLEnabled();
-		void						EnablePLL();
+		void						EnablePLL(uint32 lanes);
 		void						DisablePLL();
 
 		uint32						Base()
@@ -42,7 +42,7 @@ public:
 		void						Disable();
 
 		bool						IsPLLEnabled();
-		void						EnablePLL();
+		void						EnablePLL(uint32 lanes);
 		void						DisablePLL();
 
 		void						SwitchClock(bool toPCDClock);