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radeon_hd: update DP definitions to match the spec

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Change-Id: Ib653fcf3fef26e17e801ee016e94787c67a64e3c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5173
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Jérôme Duval <[email protected]>
This commit is contained in:
Jérôme Duval
2022-04-05 14:47:59 +00:00
parent f0a63f1888
commit f6e7d9dfbc
2 changed files with 58 additions and 62 deletions
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headers/private/graphics/common/dp_raw.h
+40 -44
View File
@@ -36,7 +36,6 @@
/* *** DPCD Receiver Compatibility Field (0x0000) *** */ /* *** DPCD Receiver Compatibility Field (0x0000) *** */
/* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */
// DPCD Version (0x0) // DPCD Version (0x0)
#define DP_DPCD_SIZE 0xf // Size
#define DP_DPCD_REV 0x0000 // Reg #define DP_DPCD_REV 0x0000 // Reg
#define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int
#define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int
@@ -48,43 +47,40 @@
// Use DP_LINK_RATE_* for speed. // Use DP_LINK_RATE_* for speed.
// DP Maximum Lane Count (0x2) // DP Maximum Lane Count (0x2)
#define DP_MAX_LANE_COUNT 0x0002 // Reg #define DP_MAX_LANE_COUNT 0x0002 // Reg
#define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count #define DP_MAX_LANE_COUNT_MASK 0x1f // Count
#define DP_MAX_LANE_COUNT_1 (1 << 0) // Value #define DP_ENHANCED_FRAME_CAP (1 << 7) // Bool, Rev 1.1
#define DP_MAX_LANE_COUNT_2 (2 << 0) // Value
#define DP_MAX_LANE_COUNT_4 (4 << 0) // Value
#define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1
// DP Maximum Downspread (0x3) // DP Maximum Downspread (0x3)
#define DP_MAX_DOWNSPREAD 0x0003 // Reg #define DP_MAX_DOWNSPREAD 0x0003 // Reg
#define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool #define DP_MAX_DOWNSPREAD_0_5 (1 << 0) // Bool
#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool #define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) // Bool
// DP Number of Receiver Ports (0x4) // DP Number of Receiver Ports (0x4)
#define DP_NORP 0x0004 // Reg #define DP_NORP 0x0004 // Reg
#define DP_NORP_MASK (1 << 0) // Count #define DP_NORP_MASK 0x1 // Count
// DP Downstream Port Present (0x5) // DP Downstream Port Present (0x5)
#define DP_DOWNSTREAMPORT 0x0005 // Reg #define DP_DOWNSTREAMPORT_PRESENT 0x0005 // Reg
#define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool #define DP_DWN_STRM_PORT_PRESENT (1 << 0) // Bool
#define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask #define DP_DWN_STRM_PORT_TYPE_MASK (3 << 1) // Mask
#define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value #define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value #define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value #define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) // Value
#define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value #define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) // Value
#define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool #define DP_FORMAT_CONVERSION (1 << 3) // Bool
#define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) // Bool
// DP Main Link Channel Coding (0x6) // DP Main Link Channel Coding (0x6)
#define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x0006 // Reg
#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool #define DP_CAP_ANSI_8B10B (1 << 0) // Bool
// DP Downstream Port Count (0x7) (Only 1.1+) // DP Downstream Port Count (0x7) (Only 1.1+)
#define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg #define DP_DOWN_STREAM_PORT_COUNT 0x0007 // Reg
#define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count #define DP_PORT_COUNT_MASK 0xf // Count
#define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool #define DP_OUI_SUPPORT (1 << 7) // Bool
// DP Port Capability 0 // DP Port Capability 0
#define DP_PORT0_CAPABILITY0 0x0008 // Reg #define DP_RECEIVE_PORT_0_CAP_0 0x0008 // Reg
#define DP_PORT1_CAPABILITY0 0x000A // Reg #define DP_RECEIVE_PORT_1_CAP_0 0x000a // Reg
#define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool #define DP_LOCAL_EDID_PRESENT (1 << 1) // Bool
#define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool #define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) // Bool
// DP Port Capability 1 // DP Port Buffer Size
#define DP_PORT0_CAPABILITY1 0x0009 // Reg #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x0009 // Reg
#define DP_PORT1_CAPABILITY1 0x000B // Reg #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x000b // Reg
#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size
// (value + 1) * 32 bytes per lane // (value + 1) * 32 bytes per lane
/* *** DPCD Link Configuration Field (0x0100) *** */ /* *** DPCD Link Configuration Field (0x0100) *** */
@@ -100,12 +96,12 @@
#define DP_LANE_COUNT_MASK (31 << 0) // Count #define DP_LANE_COUNT_MASK (31 << 0) // Count
#define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1
// DP Training Pattern (0x0102) // DP Training Pattern (0x0102)
#define DP_TRAIN 0x0102 // Reg #define DP_TRAINING_PATTERN_SET 0x0102 // Reg
#define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask #define DP_TRAINING_PATTERN_MASK (3 << 0) // Mask
#define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value #define DP_TRAINING_PATTERN_DISABLE (0 << 0) // Value
#define DP_TRAIN_PATTERN_1 (1 << 0) // Value #define DP_TRAINING_PATTERN_1 (1 << 0) // Value
#define DP_TRAIN_PATTERN_2 (2 << 0) // Value #define DP_TRAINING_PATTERN_2 (2 << 0) // Value
#define DP_TRAIN_PATTERN_3 (3 << 0) // Value #define DP_TRAINING_PATTERN_3 (3 << 0) // Value
#define DP_TRAIN_QUAL_MASK (3 << 2) // Mask #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask
#define DP_TRAIN_QUAL_NONE (0 << 2) // Value #define DP_TRAIN_QUAL_NONE (0 << 2) // Value
@@ -120,10 +116,10 @@
#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value
#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value
// DP Training Lane n (0x0103 - 0x0106) // DP Training Lane n (0x0103 - 0x0106)
#define DP_TRAIN_LANE0 0x0103 // Reg #define DP_TRAINING_LANE0_SET 0x0103 // Reg
#define DP_TRAIN_LANE1 0x0104 // Reg #define DP_TRAINING_LANE1_SET 0x0104 // Reg
#define DP_TRAIN_LANE2 0x0105 // Reg #define DP_TRAINING_LANE2_SET 0x0105 // Reg
#define DP_TRAIN_LANE3 0x0106 // Reg #define DP_TRAINING_LANE3_SET 0x0106 // Reg
#define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift
#define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask
@@ -177,10 +173,10 @@
| DP_LANE_STATUS_CHEQ_DONE_B \ | DP_LANE_STATUS_CHEQ_DONE_B \
| DP_LANE_STATUS_SYMB_LOCK_B) | DP_LANE_STATUS_SYMB_LOCK_B)
// DP Lane Align Status (0x0204) // DP Lane Align Status (0x0204)
#define DP_LANE_ALIGN 0x0204 // Reg #define DP_LANE_ALIGN_STATUS_UPDATED 0x0204 // Reg
#define DP_LANE_ALIGN_DONE (1 << 0) // Bool #define DP_INTERLANE_ALIGN_DONE (1 << 0) // Bool
#define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) // Bool
#define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool #define DP_LINK_STATUS_UPDATED (1 << 7) // Bool
// DP Sink Status (0x0205) // DP Sink Status (0x0205)
#define DP_SINK_STATUS 0x0205 // Reg #define DP_SINK_STATUS 0x0205 // Reg
#define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool #define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool
src/add-ons/accelerants/radeon_hd/displayport.cpp
+18 -18
View File
@@ -531,9 +531,9 @@ static bool
dp_clock_equalization_ok(dp_info* dp) dp_clock_equalization_ok(dp_info* dp)
{ {
uint8 laneAlignment uint8 laneAlignment
= dp->linkStatus[DP_LANE_ALIGN - DP_LANE_STATUS_0_1]; = dp->linkStatus[DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE_STATUS_0_1];
if ((laneAlignment & DP_LANE_ALIGN_DONE) == 0) { if ((laneAlignment & DP_INTERLANE_ALIGN_DONE) == 0) {
TRACE("%s: false. Lane alignment incomplete.\n", __func__); TRACE("%s: false. Lane alignment incomplete.\n", __func__);
return false; return false;
} }
@@ -565,7 +565,7 @@ dp_update_vs_emph(uint32 connectorIndex)
memset(&message, 0, sizeof(message)); memset(&message, 0, sizeof(message));
message.request = DP_AUX_NATIVE_WRITE; message.request = DP_AUX_NATIVE_WRITE;
message.address = DP_TRAIN_LANE0; message.address = DP_TRAINING_LANE0_SET;
message.buffer = dp->trainingSet; message.buffer = dp->trainingSet;
message.size = dp->laneCount; message.size = dp->laneCount;
// TODO: Review laneCount as it sounds strange. // TODO: Review laneCount as it sounds strange.
@@ -654,23 +654,23 @@ dp_set_tp(uint32 connectorIndex, int trainingPattern)
if (info.dceMajor >= 4) { if (info.dceMajor >= 4) {
TRACE("%s: Training with encoder...\n", __func__); TRACE("%s: Training with encoder...\n", __func__);
switch (trainingPattern) { switch (trainingPattern) {
case DP_TRAIN_PATTERN_1: case DP_TRAINING_PATTERN_1:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
break; break;
case DP_TRAIN_PATTERN_2: case DP_TRAINING_PATTERN_2:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
break; break;
case DP_TRAIN_PATTERN_3: case DP_TRAINING_PATTERN_3:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
break; break;
} }
encoder_dig_setup(connectorIndex, pll->pixelClock, rawTrainingPattern); encoder_dig_setup(connectorIndex, pll->pixelClock, rawTrainingPattern);
} else { } else {
switch (trainingPattern) { switch (trainingPattern) {
case DP_TRAIN_PATTERN_1: case DP_TRAINING_PATTERN_1:
rawTrainingPattern = 0; rawTrainingPattern = 0;
break; break;
case DP_TRAIN_PATTERN_2: case DP_TRAINING_PATTERN_2:
rawTrainingPattern = 1; rawTrainingPattern = 1;
break; break;
} }
@@ -680,7 +680,7 @@ dp_set_tp(uint32 connectorIndex, int trainingPattern)
} }
// Enable training pattern on the sink // Enable training pattern on the sink
dpcd_reg_write(connectorIndex, DP_TRAIN, trainingPattern); dpcd_reg_write(connectorIndex, DP_TRAINING_PATTERN_SET, trainingPattern);
} }
@@ -697,7 +697,7 @@ dp_link_train_cr(uint32 connectorIndex)
uint8 voltage = 0xff; uint8 voltage = 0xff;
int lane; int lane;
dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_1); dp_set_tp(connectorIndex, DP_TRAINING_PATTERN_1);
memset(dp->trainingSet, 0, 4); memset(dp->trainingSet, 0, 4);
dp_update_vs_emph(connectorIndex); dp_update_vs_emph(connectorIndex);
snooze(400); snooze(400);
@@ -764,9 +764,9 @@ dp_link_train_ce(uint32 connectorIndex, bool tp3Support)
dp_info* dp = &gConnector[connectorIndex]->dpInfo; dp_info* dp = &gConnector[connectorIndex]->dpInfo;
if (tp3Support) if (tp3Support)
dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_3); dp_set_tp(connectorIndex, DP_TRAINING_PATTERN_3);
else else
dp_set_tp(connectorIndex, DP_TRAIN_PATTERN_2); dp_set_tp(connectorIndex, DP_TRAINING_PATTERN_2);
dp->trainingAttempts = 0; dp->trainingAttempts = 0;
bool channelEqual = false; bool channelEqual = false;
@@ -858,7 +858,7 @@ dp_link_train(uint8 crtcID)
sandbox = dpcd_reg_read(connectorIndex, DP_LANE_COUNT); sandbox = dpcd_reg_read(connectorIndex, DP_LANE_COUNT);
if (dp->revision >= DP_DPCD_REV_11 if (dp->revision >= DP_DPCD_REV_11
&& (dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT) && (dpcd_reg_read(connectorIndex, DP_MAX_LANE_COUNT)
& DP_ENHANCED_FRAME_CAP_EN)) { & DP_ENHANCED_FRAME_CAP)) {
sandbox |= DP_ENHANCED_FRAME_EN; sandbox |= DP_ENHANCED_FRAME_EN;
} }
dpcd_reg_write(connectorIndex, DP_LANE_COUNT, sandbox); dpcd_reg_write(connectorIndex, DP_LANE_COUNT, sandbox);
@@ -879,7 +879,7 @@ dp_link_train(uint8 crtcID)
} }
// Disable the training pattern on the sink // Disable the training pattern on the sink
dpcd_reg_write(connectorIndex, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED); dpcd_reg_write(connectorIndex, DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
dp_link_train_cr(connectorIndex); dp_link_train_cr(connectorIndex);
dp_link_train_ce(connectorIndex, dpTPS3Supported); dp_link_train_ce(connectorIndex, dpTPS3Supported);
@@ -888,7 +888,7 @@ dp_link_train(uint8 crtcID)
snooze(400); snooze(400);
// Disable the training pattern on the sink // Disable the training pattern on the sink
dpcd_reg_write(connectorIndex, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED); dpcd_reg_write(connectorIndex, DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
// Disable the training pattern on the source // Disable the training pattern on the source
if (info.dceMajor >= 4) { if (info.dceMajor >= 4) {
@@ -1016,11 +1016,11 @@ debug_dp_info()
ERROR(" - receiver port count: %d\n", ERROR(" - receiver port count: %d\n",
dpcd_reg_read(id, DP_NORP) & DP_NORP_MASK); dpcd_reg_read(id, DP_NORP) & DP_NORP_MASK);
ERROR(" - downstream port present: %s\n", ERROR(" - downstream port present: %s\n",
dpcd_reg_read(id, DP_DOWNSTREAMPORT) & DP_DOWNSTREAMPORT_EN dpcd_reg_read(id, DP_DOWNSTREAMPORT_PRESENT) & DP_DWN_STRM_PORT_PRESENT
? "yes" : "no"); ? "yes" : "no");
ERROR(" - downstream port count: %d\n", ERROR(" - downstream port count: %d\n",
dpcd_reg_read(id, DP_DOWNSTREAMPORT_COUNT) dpcd_reg_read(id, DP_DOWN_STREAM_PORT_COUNT)
& DP_DOWNSTREAMPORT_COUNT_MASK); & DP_PORT_COUNT_MASK);
ERROR(" + Training\n"); ERROR(" + Training\n");
ERROR(" - attempts: %" B_PRIu8 "\n", ERROR(" - attempts: %" B_PRIu8 "\n",
dp->trainingAttempts); dp->trainingAttempts);