From f979e62e54bf6d6150597a4bf1b8f0cf354a9c9d Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <kallisti5@unixzen.com>
Date: Thu, 12 Nov 2015 18:30:21 -0600
Subject: [PATCH] intel_extreme: Program more LVDS regs. Set +/- @ lvds port

---
 .../graphics/intel_extreme/intel_extreme.h    |  8 +++++++-
 .../accelerants/intel_extreme/DisplayPipe.cpp |  9 +++++++++
 .../accelerants/intel_extreme/Ports.cpp       | 20 ++++++++++++++-----
 src/add-ons/accelerants/intel_extreme/pll.cpp |  3 ++-
 4 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index 1f50ac94d1..fe13f39a16 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -442,10 +442,16 @@ struct intel_free_graphics_memory {
 #define LVDS_POST2_RATE_FAST			7
 #define LVDS_CLKB_POWER_MASK			(3 << 4)
 #define LVDS_CLKB_POWER_UP				(3 << 4)
-#define LVDS_PORT_EN					(1 << 31)
+#define LVDS_A3_POWER_MASK				(3 << 6)
+#define LVDS_A3_POWER_UP				(3 << 6)
 #define LVDS_A0A2_CLKA_POWER_UP			(3 << 8)
 #define LVDS_B0B3PAIRS_POWER_UP			(3 << 2)
+#define LVDS_BORDER_ENABLE				(1 << 15)
+#define LVDS_HSYNC_POLARITY				(1 << 20)
+#define LVDS_VSYNC_POLARITY				(1 << 21)
 #define LVDS_18BIT_DITHER				(1 << 25)
+#define LVDS_PORT_EN					(1 << 31)
+
 
 // PLL flags
 #define DISPLAY_PLL_ENABLED				(1UL << 31)
diff --git a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
index ce0e3ad927..27e9db07f2 100644
--- a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
+++ b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
@@ -202,6 +202,15 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
 	//		pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
 	//			& DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
 		}
+		#if 0
+		// TODO: ??? LVDS?
+		switch (divisors.post2) {
+			case 5:
+			case 7:
+				pll |= DISPLAY_PLL_DIVIDE_HIGH;
+				break;
+		}
+		#endif
 		if (divisors.post2_high)
 			pll |= DISPLAY_PLL_DIVIDE_HIGH;
 
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index 8f8a4437b9..51348d5881 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -452,9 +452,12 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	uint32 lvds = read32(_PortRegister())
 		| LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 
-	lvds |= LVDS_18BIT_DITHER;
-		// TODO: do not do this if the connected panel is 24-bit
-		// (I don't know how to detect that)
+	if (gInfo->shared_info->device_type.Generation() == 4) {
+		// LVDS_A3_POWER_UP == 24bpp
+		// otherwise, 18bpp
+		if ((lvds & LVDS_A3_POWER_MASK) != LVDS_A3_POWER_UP)
+			lvds |= LVDS_18BIT_DITHER;
+	}
 
 	// Set the B0-B3 data pairs corresponding to whether we're going to
 	// set the DPLLs for dual-channel mode or not.
@@ -463,6 +466,13 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	else
 		lvds &= ~(LVDS_B0B3PAIRS_POWER_UP | LVDS_CLKB_POWER_UP);
 
+	// Set LVDS sync polarity
+	lvds &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+	if ((target->timing.flags & B_POSITIVE_HSYNC) != 0)
+		lvds |= LVDS_HSYNC_POLARITY;
+	if ((target->timing.flags & B_POSITIVE_VSYNC) != 0)
+		lvds |= LVDS_VSYNC_POLARITY;
+
 	write32(_PortRegister(), lvds);
 	read32(_PortRegister());
 
@@ -486,9 +496,9 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	write32(panelControl, read32(panelControl) | PANEL_CONTROL_POWER_TARGET_ON);
 
 	// TODO: A wait_for power on status to be set would be better here
-	spin(1000);
+	spin(750);
 	if ((read32(panelStatus) & PANEL_STATUS_POWER_ON) == 0)
-		ERROR("%s: %s didn't power on in 250ms!\n", __func__, PortName());
+		ERROR("%s: %s didn't power on in 750ms!\n", __func__, PortName());
 
 	// Program target display mode
 	fDisplayPipe->Enable(target, _PortRegister());
diff --git a/src/add-ons/accelerants/intel_extreme/pll.cpp b/src/add-ons/accelerants/intel_extreme/pll.cpp
index 9eb0323ae6..8a06633a60 100644
--- a/src/add-ons/accelerants/intel_extreme/pll.cpp
+++ b/src/add-ons/accelerants/intel_extreme/pll.cpp
@@ -138,7 +138,8 @@ compute_pll_divisors(display_mode* current, pll_divisors* divisors,
 	TRACE("%s: required MHz: %g\n", __func__, requestedPixelClock);
 
 	if (isLVDS) {
-		if ((read32(INTEL_DIGITAL_LVDS_PORT) & LVDS_CLKB_POWER_MASK)
+		if (requestedPixelClock >= 112.199
+			|| (read32(INTEL_DIGITAL_LVDS_PORT) & LVDS_CLKB_POWER_MASK)
 				== LVDS_CLKB_POWER_UP)
 			divisors->post2 = LVDS_POST2_RATE_FAST;
 		else