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riscv: use atomic CSR bit set/clear operations, refactor

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Fix race conditions that cause broken timer interrupts.

Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883
Reviewed-by: X512 <[email protected]>
Reviewed-by: Alex von Gluck IV <[email protected]>
Tested-by: Commit checker robot <[email protected]>
This commit is contained in:
X512
2022-12-11 18:43:15 +00:00
committed by Alex von Gluck IV
parent 09b2fc9e11
commit fa557843f2
14 changed files with 148 additions and 236 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/kernel/arch/riscv64/arch_cpu.h
+3 -10
View File
@@ -19,28 +19,21 @@
static inline bool
get_ac()
{
SstatusReg status(Sstatus());
return status.sum != 0;
return SstatusReg{.val = Sstatus()}.sum;
}
static inline void
set_ac()
{
// TODO: Could be done atomically via CSRRS?
SstatusReg status(Sstatus());
status.sum = 1;
SetSstatus(status.val);
SetBitsSstatus(SstatusReg{.sum = 1}.val);
}
static inline void
clear_ac()
{
// TODO: Could be done atomically with CSRRC?
SstatusReg status(Sstatus());
status.sum = 0;
SetSstatus(status.val);
ClearBitsSstatus(SstatusReg{.sum = 1}.val);
}
headers/private/kernel/arch/riscv64/arch_int.h
+4 -11
View File
@@ -20,22 +20,15 @@
static inline void
arch_int_enable_interrupts_inline(void)
{
// TODO: Use atomic CSRRS?
SstatusReg status(Sstatus());
status.ie |= (1 << modeS);
SetSstatus(status.val);
SetBitsSstatus(SstatusReg{.ie = 1 << modeS}.val);
}
static inline int
arch_int_disable_interrupts_inline(void)
{
// TODO: Use atomic CSRRC?
SstatusReg status(Sstatus());
int oldState = ((1 << modeS) & status.ie) != 0;
status.ie &= ~(1 << modeS);
SetSstatus(status.val);
return oldState;
SstatusReg oldStatus{.val = GetAndClearBitsSstatus(SstatusReg{.ie = 1 << modeS}.val)};
return ((1 << modeS) & oldStatus.ie) != 0;
}
@@ -50,7 +43,7 @@ arch_int_restore_interrupts_inline(int oldState)
static inline bool
arch_int_are_interrupts_enabled_inline(void)
{
SstatusReg status(Sstatus());
SstatusReg status{.val = Sstatus()};
return ((1 << modeS) & status.ie) != 0;
}
headers/private/system/arch/riscv64/arch_cpu_defs.h
+99 -170
View File
@@ -27,59 +27,49 @@ enum {
extStatusDirty = 3,
};
struct MstatusReg {
union {
struct {
uint64 ie: 4; // interrupt enable
uint64 pie: 4; // previous interrupt enable
uint64 spp: 1; // previous mode (supervisor)
uint64 unused1: 2;
uint64 mpp: 2; // previous mode (machine)
uint64 fs: 2; // FPU status
uint64 xs: 2; // extensions status
uint64 mprv: 1; // modify privilege
uint64 sum: 1; // permit supervisor user memory access
uint64 mxr: 1; // make executable readable
uint64 tvm: 1; // trap virtual memory
uint64 tw: 1; // timeout wait (trap WFI)
uint64 tsr: 1; // trap SRET
uint64 unused2: 9;
uint64 uxl: 2; // U-mode XLEN
uint64 sxl: 2; // S-mode XLEN
uint64 unused3: 27;
uint64 sd: 1; // status dirty
};
uint64 val;
union MstatusReg {
struct {
uint64 ie: 4; // interrupt enable
uint64 pie: 4; // previous interrupt enable
uint64 spp: 1; // previous mode (supervisor)
uint64 unused1: 2;
uint64 mpp: 2; // previous mode (machine)
uint64 fs: 2; // FPU status
uint64 xs: 2; // extensions status
uint64 mprv: 1; // modify privilege
uint64 sum: 1; // permit supervisor user memory access
uint64 mxr: 1; // make executable readable
uint64 tvm: 1; // trap virtual memory
uint64 tw: 1; // timeout wait (trap WFI)
uint64 tsr: 1; // trap SRET
uint64 unused2: 9;
uint64 uxl: 2; // U-mode XLEN
uint64 sxl: 2; // S-mode XLEN
uint64 unused3: 27;
uint64 sd: 1; // status dirty
};
MstatusReg() {}
MstatusReg(uint64 val): val(val) {}
uint64 val;
};
struct SstatusReg {
union {
struct {
uint64 ie: 2; // interrupt enable
uint64 unused1: 2;
uint64 pie: 2; // previous interrupt enable
uint64 unused2: 2;
uint64 spp: 1; // previous mode (supervisor)
uint64 unused3: 4;
uint64 fs: 2; // FPU status
uint64 xs: 2; // extensions status
uint64 unused4: 1;
uint64 sum: 1; // permit supervisor user memory access
uint64 mxr: 1; // make executable readable
uint64 unused5: 12;
uint64 uxl: 2; // U-mode XLEN
uint64 unused6: 29;
uint64 sd: 1; // status dirty
};
uint64 val;
union SstatusReg {
struct {
uint64 ie: 2; // interrupt enable
uint64 unused1: 2;
uint64 pie: 2; // previous interrupt enable
uint64 unused2: 2;
uint64 spp: 1; // previous mode (supervisor)
uint64 unused3: 4;
uint64 fs: 2; // FPU status
uint64 xs: 2; // extensions status
uint64 unused4: 1;
uint64 sum: 1; // permit supervisor user memory access
uint64 mxr: 1; // make executable readable
uint64 unused5: 12;
uint64 uxl: 2; // U-mode XLEN
uint64 unused6: 29;
uint64 sd: 1; // status dirty
};
SstatusReg() {}
SstatusReg(uint64 val): val(val) {}
uint64 val;
};
enum {
@@ -129,7 +119,6 @@ enum {
};
enum {
pageSize = 4096,
pageBits = 12,
pteCount = 512,
pteIdxBits = 9,
@@ -146,19 +135,14 @@ enum {
pteDirty = 7,
};
struct Pte {
union {
struct {
uint64 flags: 8;
uint64 rsw: 2;
uint64 ppn: 44;
uint64 reserved: 10;
};
uint64 val;
union Pte {
struct {
uint64 flags: 8;
uint64 rsw: 2;
uint64 ppn: 44;
uint64 reserved: 10;
};
Pte() {}
Pte(uint64 val): val(val) {}
uint64 val;
};
enum {
@@ -169,18 +153,13 @@ enum {
satpModeSv64 = 11,
};
struct SatpReg {
union {
struct {
uint64 ppn: 44;
uint64 asid: 16;
uint64 mode: 4;
};
uint64 val;
union SatpReg {
struct {
uint64 ppn: 44;
uint64 asid: 16;
uint64 mode: 4;
};
SatpReg() {}
SatpReg(uint64 val): val(val) {}
uint64 val;
};
static B_ALWAYS_INLINE uint64 VirtAdrPte(uint64 physAdr, uint32 level)
@@ -190,134 +169,84 @@ static B_ALWAYS_INLINE uint64 VirtAdrPte(uint64 physAdr, uint32 level)
static B_ALWAYS_INLINE uint64 VirtAdrOfs(uint64 physAdr)
{
return physAdr % pageSize;
return physAdr % PAGESIZE;
}
#define CSR_REG_MACRO(Name, value) \
static B_ALWAYS_INLINE uint64 Name() { \
uint64 x; asm volatile("csrr %0, " #value : "=r" (x)); return x;} \
static B_ALWAYS_INLINE void Set##Name(uint64 x) { \
asm volatile("csrw " #value ", %0" : : "r" (x));} \
static B_ALWAYS_INLINE void SetBits##Name(uint64 x) { \
asm volatile("csrs " #value ", %0" : : "r" (x));} \
static B_ALWAYS_INLINE void ClearBits##Name(uint64 x) { \
asm volatile("csrc " #value ", %0" : : "r" (x));} \
static B_ALWAYS_INLINE uint64 GetAndSetBits##Name(uint64 x) { \
uint64 res; \
asm volatile("csrrs %0, " #value ", %1" : "=r" (res) : "r" (x)); \
return res; \
} \
static B_ALWAYS_INLINE uint64 GetAndClearBits##Name(uint64 x) { \
uint64 res; \
asm volatile("csrrc %0, " #value ", %1" : "=r" (res) : "r" (x)); \
return res; \
} \
// CPU core ID
static B_ALWAYS_INLINE uint64 Mhartid() {
uint64 x; asm volatile("csrr %0, mhartid" : "=r" (x)); return x;}
CSR_REG_MACRO(Mhartid, mhartid)
// status register
static B_ALWAYS_INLINE uint64 Mstatus() {
uint64 x; asm volatile("csrr %0, mstatus" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMstatus(uint64 x) {
asm volatile("csrw mstatus, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Sstatus() {
uint64 x; asm volatile("csrr %0, sstatus" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSstatus(uint64 x) {
asm volatile("csrw sstatus, %0" : : "r" (x));}
CSR_REG_MACRO(Mstatus, mstatus)
CSR_REG_MACRO(Sstatus, sstatus)
// exception program counter
static B_ALWAYS_INLINE uint64 Mepc() {
uint64 x; asm volatile("csrr %0, mepc" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMepc(uint64 x) {
asm volatile("csrw mepc, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Sepc() {
uint64 x; asm volatile("csrr %0, sepc" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSepc(uint64 x) {
asm volatile("csrw sepc, %0" : : "r" (x));}
CSR_REG_MACRO(Mepc, mepc)
CSR_REG_MACRO(Sepc, sepc)
// interrupt pending
static B_ALWAYS_INLINE uint64 Mip() {
uint64 x; asm volatile("csrr %0, mip" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMip(uint64 x) {
asm volatile("csrw mip, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Sip() {
uint64 x; asm volatile("csrr %0, sip" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSip(uint64 x) {
asm volatile("csrw sip, %0" : : "r" (x));}
CSR_REG_MACRO(Mip, mip)
CSR_REG_MACRO(Sip, sip)
// interrupt enable
static B_ALWAYS_INLINE uint64 Sie() {
uint64 x; asm volatile("csrr %0, sie" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSie(uint64 x) {
asm volatile("csrw sie, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Mie() {
uint64 x; asm volatile("csrr %0, mie" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMie(uint64 x) {
asm volatile("csrw mie, %0" : : "r" (x));}
CSR_REG_MACRO(Mie, mie)
CSR_REG_MACRO(Sie, sie)
// exception delegation
static B_ALWAYS_INLINE uint64 Medeleg() {
uint64 x; asm volatile("csrr %0, medeleg" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMedeleg(uint64 x) {
asm volatile("csrw medeleg, %0" : : "r" (x));}
CSR_REG_MACRO(Medeleg, medeleg)
// interrupt delegation
static B_ALWAYS_INLINE uint64 Mideleg() {
uint64 x; asm volatile("csrr %0, mideleg" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMideleg(uint64 x) {
asm volatile("csrw mideleg, %0" : : "r" (x));}
CSR_REG_MACRO(Mideleg, mideleg)
// trap vector, 2 low bits: mode
static B_ALWAYS_INLINE uint64 Mtvec() {
uint64 x; asm volatile("csrr %0, mtvec" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMtvec(uint64 x) {
asm volatile("csrw mtvec, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Stvec() {
uint64 x; asm volatile("csrr %0, stvec" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetStvec(uint64 x) {
asm volatile("csrw stvec, %0" : : "r" (x));}
CSR_REG_MACRO(Mtvec, mtvec)
CSR_REG_MACRO(Stvec, stvec)
// address translation and protection (pointer to page table and flags)
static B_ALWAYS_INLINE uint64 Satp() {
uint64 x; asm volatile("csrr %0, satp" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSatp(uint64 x) {
asm volatile("csrw satp, %0" : : "r" (x) : "memory");}
CSR_REG_MACRO(Satp, satp)
// scratch register
static B_ALWAYS_INLINE uint64 Mscratch() {
uint64 x; asm volatile("csrr %0, mscratch" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMscratch(uint64 x) {
asm volatile("csrw mscratch, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Sscratch() {
uint64 x; asm volatile("csrr %0, sscratch" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetSscratch(uint64 x) {
asm volatile("csrw sscratch, %0" : : "r" (x));}
CSR_REG_MACRO(Mscratch, mscratch)
CSR_REG_MACRO(Sscratch, sscratch)
// trap cause
static B_ALWAYS_INLINE uint64 Mcause() {
uint64 x; asm volatile("csrr %0, mcause" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMcause(uint64 x) {
asm volatile("csrw mcause, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Scause() {
uint64 x; asm volatile("csrr %0, scause" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetScause(uint64 x) {
asm volatile("csrw scause, %0" : : "r" (x));}
CSR_REG_MACRO(Mcause, mcause)
CSR_REG_MACRO(Scause, scause)
// trap value
static B_ALWAYS_INLINE uint64 Mtval() {
uint64 x; asm volatile("csrr %0, mtval" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMtval(uint64 x) {
asm volatile("csrw mtval, %0" : : "r" (x));}
static B_ALWAYS_INLINE uint64 Stval() {
uint64 x; asm volatile("csrr %0, stval" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetStval(uint64 x) {
asm volatile("csrw stval, %0" : : "r" (x));}
CSR_REG_MACRO(Mtval, mtval)
CSR_REG_MACRO(Stval, stval)
// machine-mode counter enable
static B_ALWAYS_INLINE uint64 Mcounteren() {
uint64 x; asm volatile("csrr %0, mcounteren" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetMcounteren(uint64 x) {
asm volatile("csrw mcounteren, %0" : : "r" (x));}
CSR_REG_MACRO(Mcounteren, mcounteren)
// cycle counter
static B_ALWAYS_INLINE uint64 CpuMcycle() {
uint64 x; asm volatile("csrr %0, mcycle" : "=r" (x)); return x;}
static B_ALWAYS_INLINE uint64 CpuCycle() {
uint64 x; asm volatile("csrr %0, cycle" : "=r" (x)); return x;}
CSR_REG_MACRO(CpuMcycle, mcycle)
CSR_REG_MACRO(CpuCycle, cycle)
// monotonic timer
static B_ALWAYS_INLINE uint64 CpuTime() {
uint64 x; asm volatile("csrr %0, time" : "=r" (x)); return x;}
CSR_REG_MACRO(CpuTime, time)
// physical memory protection
static B_ALWAYS_INLINE uint64 Pmpaddr0() {
uint64 x; asm volatile("csrr %0, pmpaddr0" : "=r" (x)); return x;}
static B_ALWAYS_INLINE uint64 Pmpcfg0() {
uint64 x; asm volatile("csrr %0, pmpcfg0" : "=r" (x)); return x;}
static B_ALWAYS_INLINE void SetPmpaddr0(uint64 x) {
asm volatile("csrw pmpaddr0, %0" : : "r" (x));}
static B_ALWAYS_INLINE void SetPmpcfg0(uint64 x) {
asm volatile("csrw pmpcfg0, %0" : : "r" (x));}
CSR_REG_MACRO(Pmpaddr0, pmpaddr0)
CSR_REG_MACRO(Pmpcfg0, pmpcfg0)
// flush the TLB
static B_ALWAYS_INLINE void FlushTlbAll() {
src/system/boot/platform/efi/arch/riscv64/arch_mmu.cpp
+8 -8
View File
@@ -111,7 +111,7 @@ DumpPageTableInt(Pte* pte, uint64_t virtAdr, uint32_t level, uint64& firstVirt,
if (level == 0)
panic("internal page table on level 0");
DumpPageTableInt((Pte*)VirtFromPhys(pageSize*pte[i].ppn),
DumpPageTableInt((Pte*)VirtFromPhys(B_PAGE_SIZE*pte[i].ppn),
virtAdr + ((uint64_t)i << (pageBits + pteIdxBits*level)),
level - 1, firstVirt, firstPhys, firstFlags, len);
} else {
@@ -130,7 +130,7 @@ DumpPageTableInt(Pte* pte, uint64_t virtAdr, uint32_t level, uint64& firstVirt,
static int
DumpPageTable(uint64 satp)
{
SatpReg satpReg(satp);
SatpReg satpReg{.val = satp};
Pte* root = (Pte*)VirtFromPhys(satpReg.ppn * B_PAGE_SIZE);
dprintf("PageTable:\n");
@@ -237,14 +237,14 @@ PreallocKernelRange()
}
uint64
static uint64
GetSatp()
{
SatpReg satp;
satp.ppn = sPageTable / B_PAGE_SIZE;
satp.asid = 0;
satp.mode = satpModeSv39;
return satp.val;
return SatpReg{
.ppn = sPageTable / B_PAGE_SIZE,
.asid = 0,
.mode = satpModeSv39
}.val;
}
src/system/boot/platform/efi/arch/riscv64/arch_traps.cpp
+1 -1
View File
@@ -47,7 +47,7 @@ WriteExt(uint64_t val)
void
WriteSstatus(uint64_t val)
{
SstatusReg status(val);
SstatusReg status{.val = val};
dprintf("%#" B_PRIx64, val);
dprintf(" (");
dprintf("ie: "); WriteModeSet(status.ie);
src/system/boot/platform/riscv/cpu.cpp
+1 -1
View File
@@ -35,7 +35,7 @@ cpu_init()
{
gKernelArgs.num_cpus = 1;
SstatusReg status(Sstatus());
SstatusReg status{.val = Sstatus()};
status.fs = extStatusInitial; // enable FPU
status.xs = extStatusOff;
SetSstatus(status.val);
src/system/boot/platform/riscv/mmu.cpp
+5 -5
View File
@@ -270,11 +270,11 @@ SetupPageTable()
static uint64
GetSatp()
{
SatpReg satp;
satp.ppn = sPageTable / B_PAGE_SIZE;
satp.asid = 0;
satp.mode = satpModeSv39;
return satp.val;
return SatpReg{
.ppn = sPageTable / B_PAGE_SIZE,
.asid = 0,
.mode = satpModeSv39
}.val;
}
src/system/boot/platform/riscv/traps.cpp
+7 -7
View File
@@ -104,7 +104,7 @@ MTrap(iframe* frame)
frame->a0 = B_NOT_ALLOWED;
return;
}
MstatusReg status(Mstatus());
MstatusReg status{.val = Mstatus()};
status.mpp = modeS;
SetMedeleg(
0xffff & ~((1 << causeMEcall) | (1 << causeSEcall)));
@@ -125,12 +125,12 @@ MTrap(iframe* frame)
enable, frame->a2);
*/
// dprintf(" mtime: %" B_PRIu64 "\n", gClintRegs->mTime);
SetMip(Mip() & ~(1 << sTimerInt));
ClearBitsMip(1 << sTimerInt);
if (!enable) {
SetMie(Mie() & ~(1 << mTimerInt));
ClearBitsMie(1 << mTimerInt);
} else {
gClintRegs->mtimecmp[0] = frame->a2;
SetMie(Mie() | (1 << mTimerInt));
SetBitsMie(1 << mTimerInt);
}
frame->a0 = B_OK;
return;
@@ -142,8 +142,8 @@ MTrap(iframe* frame)
break;
}
case causeInterrupt + mTimerInt: {
SetMie(Mie() & ~(1 << mTimerInt));
SetMip(Mip() | (1 << sTimerInt));
ClearBitsMie(1 << mTimerInt);
SetBitsMip(1 << sTimerInt);
return;
}
}
@@ -156,7 +156,7 @@ void
traps_init()
{
SetMtvec((uint64)MVec);
MstatusReg mstatus(Mstatus());
MstatusReg mstatus{.val = Mstatus()};
mstatus.ie = 1 << modeM;
SetMstatus(mstatus.val);
InitPmp();
src/system/kernel/arch/riscv64/RISCV64VMTranslationMap.cpp
+4 -4
View File
@@ -363,7 +363,7 @@ RISCV64VMTranslationMap::Unmap(addr_t start, addr_t end)
Pte* pte = LookupPte(page, false, NULL);
if (pte != NULL) {
fMapCount--;
Pte oldPte((uint64)atomic_get_and_set64((int64*)&pte->val, 0));
Pte oldPte{.val = (uint64)atomic_get_and_set64((int64*)&pte->val, 0)};
if ((oldPte.flags & (1 << pteAccessed)) != 0)
InvalidatePage(page);
}
@@ -410,7 +410,7 @@ RISCV64VMTranslationMap::UnmapPage(VMArea* area, addr_t address,
RecursiveLocker locker(fLock);
Pte oldPte((uint64)atomic_get_and_set64((int64*)&pte->val, 0));
Pte oldPte{.val = (uint64)atomic_get_and_set64((int64*)&pte->val, 0)};
fMapCount--;
pinner.Unlock();
@@ -448,7 +448,7 @@ RISCV64VMTranslationMap::UnmapPages(VMArea* area, addr_t base, size_t size,
if (pte == NULL)
continue;
Pte oldPte((uint64)atomic_get_and_set64((int64*)&pte->val, 0));
Pte oldPte{.val = (uint64)atomic_get_and_set64((int64*)&pte->val, 0)};
if ((oldPte.flags & (1 << pteValid)) == 0)
continue;
@@ -579,7 +579,7 @@ RISCV64VMTranslationMap::UnmapArea(VMArea* area, bool deletingAddressSpace,
continue;
}
Pte oldPte((uint64)atomic_get_and_set64((int64*)&pte->val, 0));
Pte oldPte{.val = (uint64)atomic_get_and_set64((int64*)&pte->val, 0)};
// transfer the accessed/dirty flags to the page and
// invalidate the mapping, if necessary
src/system/kernel/arch/riscv64/arch_cpu.cpp
+2 -2
View File
@@ -32,12 +32,12 @@ status_t
arch_cpu_init_percpu(kernel_args *args, int curr_cpu)
{
SetStvec((uint64)SVec);
SstatusReg sstatus(Sstatus());
SstatusReg sstatus{.val = Sstatus()};
sstatus.ie = 0;
sstatus.fs = extStatusInitial; // enable FPU
sstatus.xs = extStatusOff;
SetSstatus(sstatus.val);
SetSie(Sie() | (1 << sTimerInt) | (1 << sSoftInt) | (1 << sExternInt));
SetBitsSie((1 << sTimerInt) | (1 << sSoftInt) | (1 << sExternInt));
return B_OK;
}
src/system/kernel/arch/riscv64/arch_int.cpp
+7 -7
View File
@@ -75,7 +75,7 @@ WriteExt(uint64_t val)
static void
WriteSstatus(uint64_t val)
{
SstatusReg status(val);
SstatusReg status{.val = val};
dprintf("(");
dprintf("ie: "); WriteModeSet(status.ie);
dprintf(", pie: "); WriteModeSet(status.pie);
@@ -253,7 +253,7 @@ static void
SendSignal(debug_exception_type type, uint32 signalNumber, int32 signalCode,
addr_t signalAddress = 0, int32 signalError = B_ERROR)
{
if (SstatusReg(Sstatus()).spp == modeU) {
if (SstatusReg{.val = Sstatus()}.spp == modeU) {
struct sigaction action;
Thread* thread = thread_get_current_thread();
@@ -390,13 +390,13 @@ STrap(iframe* frame)
}
}
if (SstatusReg(frame->status).spp == modeU) {
if (SstatusReg{.val = frame->status}.spp == modeU) {
thread_get_current_thread()->arch_info.userFrame = frame;
thread_get_current_thread()->arch_info.oldA0 = frame->a0;
thread_at_kernel_entry(system_time());
}
const auto& kernelExit = ScopeExit([&]() {
if (SstatusReg(frame->status).spp == modeU) {
if (SstatusReg{.val = frame->status}.spp == modeU) {
disable_interrupts();
atomic_and(&thread_get_current_thread()->flags, ~THREAD_FLAGS_SYSCALL_RESTARTED);
if ((thread_get_current_thread()->flags
@@ -431,7 +431,7 @@ STrap(iframe* frame)
Stval());
}
case causeBreakpoint: {
if (SstatusReg(frame->status).spp == modeU) {
if (SstatusReg{.val = frame->status}.spp == modeU) {
user_debug_breakpoint_hit(false);
} else {
panic("hit kernel breakpoint");
@@ -478,7 +478,7 @@ STrap(iframe* frame)
return;
}
if (SstatusReg(frame->status).pie == 0) {
if (SstatusReg{.val = frame->status}.pie == 0) {
// user_memcpy() failure
Thread* thread = thread_get_current_thread();
if (thread != NULL && thread->fault_handler != 0) {
@@ -496,7 +496,7 @@ STrap(iframe* frame)
vm_page_fault(stval, frame->epc, frame->cause == causeStorePageFault,
frame->cause == causeExecPageFault,
SstatusReg(frame->status).spp == modeU, &newIP);
SstatusReg{.val = frame->status}.spp == modeU, &newIP);
if (newIP != 0)
frame->epc = newIP;
src/system/kernel/arch/riscv64/arch_thread.cpp
+2 -2
View File
@@ -148,7 +148,7 @@ arch_thread_enter_userspace(Thread *thread, addr_t entry, void *arg1,
iframe frame;
memset(&frame, 0, sizeof(frame));
SstatusReg status(Sstatus());
SstatusReg status{.val = Sstatus()};
status.pie = (1 << modeS); // enable interrupts when enter userspace
status.spp = modeU;
@@ -381,7 +381,7 @@ arch_restore_fork_frame(struct arch_fork_arg *arg)
arch_stack* stackHeader = (arch_stack*)thread_get_current_thread()->kernel_stack_top - 1;
stackHeader->thread = thread_get_current_thread();
SstatusReg status(Sstatus());
SstatusReg status{.val = Sstatus()};
status.pie = (1 << modeS); // enable interrupts when enter userspace
status.spp = modeU;
arg->frame.status = status.val;
src/system/kernel/arch/riscv64/arch_vm.cpp
+1 -1
View File
@@ -147,7 +147,7 @@ DumpPageTableInt(Pte* pte, uint64_t virtAdr, uint32_t level, PageTableDumper& du
if (level == 0)
kprintf(" internal page table on level 0\n");
DumpPageTableInt((Pte*)VirtFromPhys(pageSize*pte[i].ppn),
DumpPageTableInt((Pte*)VirtFromPhys(B_PAGE_SIZE*pte[i].ppn),
virtAdr + ((uint64_t)i << (pageBits + pteIdxBits * level)),
level - 1, dumper);
} else {
src/system/kernel/arch/riscv64/arch_vm_translation_map.cpp
+1 -4
View File
@@ -117,10 +117,7 @@ arch_vm_translation_map_init(kernel_args *args,
}
#endif
{
SatpReg satp(Satp());
sPageTable = satp.ppn * B_PAGE_SIZE;
}
sPageTable = SatpReg{.val = Satp()}.ppn * B_PAGE_SIZE;
dprintf("physMapBase: %#" B_PRIxADDR "\n", args->arch_args.physMap.start);
dprintf("physMemBase: %#" B_PRIxADDR "\n", args->physical_memory_range[0].start);