i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel_extreme: Correct generations based on some Intel help

Browse Source
This commit is contained in:
Alexander von Gluck IV
2015-11-04 16:11:22 -06:00
parent fa1d593323
commit fb255821eb
6 changed files with 21 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/intel_extreme/intel_extreme.h
+11 -12
View File
@@ -47,9 +47,9 @@
#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
#define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell #define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell
#define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont #define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont
#define INTEL_GROUP_SLV (INTEL_FAMILY_SOC0 | 0x0010) // Silvermont #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
#define INTEL_GROUP_AIR (INTEL_FAMILY_SOC0 | 0x0020) // Airmont #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
#define INTEL_GROUP_GOL (INTEL_FAMILY_SOC0 | 0x0040) // Goldmont #define INTEL_GROUP_BXT (INTEL_FAMILY_SOC0 | 0x0040) // Broxton
// models // models
#define INTEL_TYPE_SERVER 0x0004 #define INTEL_TYPE_SERVER 0x0004
#define INTEL_TYPE_MOBILE 0x0008 #define INTEL_TYPE_MOBILE 0x0008
@@ -74,8 +74,8 @@
#define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
#define INTEL_MODEL_HAS (INTEL_GROUP_HAS) #define INTEL_MODEL_HAS (INTEL_GROUP_HAS)
#define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_VLV (INTEL_GROUP_SLV) #define INTEL_MODEL_VLV (INTEL_GROUP_VLV)
#define INTEL_MODEL_VLVM (INTEL_GROUP_SLV | INTEL_TYPE_MOBILE) #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
// ValleyView MMIO offset // ValleyView MMIO offset
#define VLV_DISPLAY_BASE 0x180000 #define VLV_DISPLAY_BASE 0x180000
@@ -177,14 +177,12 @@ struct DeviceType {
return 5; return 5;
if (InGroup(INTEL_GROUP_SNB)) if (InGroup(INTEL_GROUP_SNB))
return 6; return 6;
if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_SLV)) if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
return 7; return 7;
if (InGroup(INTEL_GROUP_CHV))
// TODO: Groups below here might need some tweaking
if (InGroup(INTEL_GROUP_AIR) || InGroup(INTEL_GROUP_GOL))
return 8; return 8;
if (InGroup(INTEL_GROUP_BXT))
// TODO: SkyLake, Broxton is gen 9 return 9;
// Generation 0 means somethins is wrong :-) // Generation 0 means somethins is wrong :-)
return 0; return 0;
@@ -305,7 +303,6 @@ struct intel_free_graphics_memory {
// PCI bridge memory management // PCI bridge memory management
#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+
#define SNB_GRAPHICS_MEMORY_CONTROL 0x50
// GGC - (G)MCH Graphics Control Register // GGC - (G)MCH Graphics Control Register
#define MEMORY_CONTROL_ENABLED 0x0004 #define MEMORY_CONTROL_ENABLED 0x0004
@@ -341,6 +338,8 @@ struct intel_free_graphics_memory {
// SandyBridge (SNB) // SandyBridge (SNB)
#define SNB_GRAPHICS_MEMORY_CONTROL 0x50
#define SNB_STOLEN_MEMORY_MASK 0xf8 #define SNB_STOLEN_MEMORY_MASK 0xf8
#define SNB_STOLEN_MEMORY_32MB (1 << 3) #define SNB_STOLEN_MEMORY_32MB (1 << 3)
#define SNB_STOLEN_MEMORY_64MB (2 << 3) #define SNB_STOLEN_MEMORY_64MB (2 << 3)
src/add-ons/accelerants/intel_extreme/Ports.cpp
+4 -6
View File
@@ -418,11 +418,9 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
compute_pll_divisors(target, &divisors, true); compute_pll_divisors(target, &divisors, true);
uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_ENABLED; uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_ENABLED;
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx) if (gInfo->shared_info->device_type.Generation() >= 4) {
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5) // DPLL mode LVDS for i915+
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
dpll |= LVDS_PLL_MODE_LVDS; dpll |= LVDS_PLL_MODE_LVDS;
// DPLL mode LVDS for i915+
} }
// Compute bitmask from p1 value // Compute bitmask from p1 value
@@ -702,7 +700,7 @@ HDMIPort::_PortRegister()
{ {
// on PCH there's an additional port sandwiched in // on PCH there's an additional port sandwiched in
bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub(); bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub();
bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SLV); bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV);
switch (PortIndex()) { switch (PortIndex()) {
case INTEL_PORT_B: case INTEL_PORT_B:
@@ -714,7 +712,7 @@ HDMIPort::_PortRegister()
return GEN4_HDMI_PORT_C; return GEN4_HDMI_PORT_C;
return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C; return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C;
case INTEL_PORT_D: case INTEL_PORT_D:
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_AIR)) if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
return CHV_HDMI_PORT_D; return CHV_HDMI_PORT_D;
return hasPCH ? PCH_HDMI_PORT_D : 0; return hasPCH ? PCH_HDMI_PORT_D : 0;
default: default:
src/add-ons/accelerants/intel_extreme/mode.cpp
+3 -3
View File
@@ -35,12 +35,12 @@
#undef TRACE #undef TRACE
#define TRACE_MODE #define TRACE_MODE
#ifdef TRACE_MODE #ifdef TRACE_MODE
# define TRACE(x...) _sPrintf("intel_extreme accelerant:" x) # define TRACE(x...) _sPrintf("intel_extreme:" x)
#else #else
# define TRACE(x...) # define TRACE(x...)
#endif #endif
#define ERROR(x...) _sPrintf("intel_extreme accelerant: " x) #define ERROR(x...) _sPrintf("intel_extreme: " x)
#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
@@ -77,7 +77,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE; imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE;
controlRegister = INTEL_DISPLAY_B_CONTROL; controlRegister = INTEL_DISPLAY_B_CONTROL;
} else { } else {
// TODO: not supported ERROR("%s: PLL not supported\n", __func__);
return; return;
} }
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+1 -4
View File
@@ -393,18 +393,15 @@ static void
set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress) set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress)
{ {
if (info.type->Generation() >= 8) { if (info.type->Generation() >= 8) {
// Airmont, Goldmont // CHV + BXT
physicalAddress |= (physicalAddress >> 28) & 0x07f0; physicalAddress |= (physicalAddress >> 28) & 0x07f0;
// TODO: cache control? // TODO: cache control?
} else if (info.type->Generation() >= 6) { } else if (info.type->Generation() >= 6) {
// SandyBridge, IronLake, IvyBridge, Haswell // SandyBridge, IronLake, IvyBridge, Haswell
physicalAddress |= (physicalAddress >> 28) & 0x0ff0; physicalAddress |= (physicalAddress >> 28) & 0x0ff0;
physicalAddress |= 0x02; // cache control, l3 cacheable physicalAddress |= 0x02; // cache control, l3 cacheable
} else if (info.type->Generation() >= 4) { } else if (info.type->Generation() >= 4) {
// Intel 9xx minus 91x, 94x, G33 // Intel 9xx minus 91x, 94x, G33
// possible high bits are stored in the lower end // possible high bits are stored in the lower end
physicalAddress |= (physicalAddress >> 28) & 0x00f0; physicalAddress |= (physicalAddress >> 28) & 0x00f0;
// TODO: cache control? // TODO: cache control?
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+1 -1
View File
@@ -347,7 +347,7 @@ intel_extreme_init(intel_info &info)
= ICH_PORT_REGISTER_BASE; = ICH_PORT_REGISTER_BASE;
} }
if (info.device_type.InGroup(INTEL_GROUP_SLV)) { if (info.device_type.InGroup(INTEL_GROUP_VLV)) {
// "I nearly got violent with the hw guys when they told me..." // "I nearly got violent with the hw guys when they told me..."
blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE; blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE; blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+1 -1
View File
@@ -37,7 +37,7 @@ intel_en_gating(intel_info &info)
} else if (info.device_type.InGroup(INTEL_GROUP_IVB)) { } else if (info.device_type.InGroup(INTEL_GROUP_IVB)) {
TRACE("IvyBridge clock gating\n"); TRACE("IvyBridge clock gating\n");
write32(info, 0x42020, (1L << 28)); write32(info, 0x42020, (1L << 28));
} else if (info.device_type.InGroup(INTEL_GROUP_SLV)) { } else if (info.device_type.InGroup(INTEL_GROUP_VLV)) {
TRACE("ValleyView clock gating\n"); TRACE("ValleyView clock gating\n");
write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28)); write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));
} else if (info.device_type.InGroup(INTEL_GROUP_ILK)) { } else if (info.device_type.InGroup(INTEL_GROUP_ILK)) {