kernel/x86: Use MWAITX or TPAUSE in arch_debug_snooze, if available.

These instructions are only available on more recent CPUs (MWAITX
on AMD since around 2015 or so, TPAUSE on Intel since around 2020.)
They allow idly waiting on the TSC even when interrupts are
disabled.

Most hypervisors do not have these available (KVM does provide
them, though not on all configurations), but on bare metal this
should make a nice difference to KDL power consumption: I tested
with a Ryzen 3700X, according to my UPS (so including monitor
and peripherals) the system used ~106 W at idle, 160 W in KDL
before this patch, and 125 W in KDL after it.

Change-Id: Id7a22ecd33f3fc005b2c312f945dc3cd364e96fa
Reviewed-on: https://review.haiku-os.org/c/haiku/+/9604
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Augustin Cavalier
2025-08-25 20:16:16 +00:00
committed by waddlesplash
parent 2082e1b86e
commit fb6c279a24
3 changed files with 64 additions and 3 deletions
+4 -2
View File
@@ -265,8 +265,9 @@
#define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor
// x86 features from cpuid eax 0x80000001, ecx register (AMD)
#define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode
#define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions
#define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode
#define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions
#define IA32_FEATURE_AMD_EXT_MWAITX (1 << 29) // MWAITX, MONITORX instructions
// x86 features from cpuid eax 0x80000001, edx register (AMD)
// only care about the ones that are unique to this register
@@ -354,6 +355,7 @@
#define IA32_FEATURE_UMIP (1 << 2) // User-mode Instruction Prevention
#define IA32_FEATURE_PKU (1 << 3) // Memory Protection Keys for User-mode pages
#define IA32_FEATURE_OSPKE (1 << 4) // PKU enabled by OS
#define IA32_FEATURE_WAITPKG (1 << 5) // TPAUSE, UMONITOR, UMWAIT instructions
#define IA32_FEATURE_AVX512VMBI2 (1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2
#define IA32_FEATURE_GFNI (1 << 8) // Galois Field instructions
#define IA32_FEATURE_VAES (1 << 9) // AES instruction set (VEX-256/EVEX)