kernel/x86_64: configure LFENCE as a serializing instruction on AMD

Change-Id: I152bf41c3479f81fc458abdf8d89874ffa3a08d7 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5691 Reviewed-by: Jérôme Duval <[email protected]>
2022-09-25 08:15:15 +00:00
parent a6e9176bc5
commit fbca1c4088
2 changed files with 14 additions and 0 deletions
@@ -122,6 +122,9 @@

 // K8 MSR registers
 #define K8_MSR_IPM						0xc0010055
+#define MSR_F10H_DE_CFG					0xc0011029
+#define DE_CFG_SERIALIZE_LFENCE			(1 << 1)
+

 // Hardware P-States MSR registers §14.4.1
 // reference https://software.intel.com/content/dam/develop/public/us/en/documents/253669-sdm-vol-3b.pdf