intel_extreme: vblank interrupt support for Gen8+
Change-Id: I8e7e68786cc4a626cb386929600715a6a6b1917d Reviewed-on: https://review.haiku-os.org/c/haiku/+/4760 Tested-by: Commit checker robot <[email protected]> Reviewed-by: Axel Dörfler <[email protected]> Reviewed-by: Adrien Destugues <[email protected]>
This commit is contained in:
Kacper Kasper
committed by
Adrien Destugues
Adrien Destugues
parent
6117e0c29c
commit
fd876ad749
@@ -341,6 +341,40 @@ enum pipe_index {
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INTEL_PIPE_D
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};
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class pipes {
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public:
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pipes() : bitmask(0) {}
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bool HasPipe(pipe_index pipe)
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{
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if (pipe == INTEL_PIPE_ANY)
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return bitmask != 0;
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return (bitmask & (1 << pipe)) != 0;
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}
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void SetPipe(pipe_index pipe)
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{
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if (pipe == INTEL_PIPE_ANY) {
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bitmask = ~1;
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// first bit corresponds to INTEL_PIPE_ANY but it's never used,
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// so it should be 0
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}
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bitmask |= (1 << pipe);
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}
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void ClearPipe(pipe_index pipe)
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{
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if (pipe == INTEL_PIPE_ANY)
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bitmask = 0;
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bitmask &= ~(1 << pipe);
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}
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private:
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uint8 bitmask;
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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@@ -554,6 +588,18 @@ struct intel_free_graphics_memory {
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#define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
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#define PCH_INTERRUPT_GLOBAL_SNB (1 << 31)
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#define PCH_MASTER_INT_CTL_BDW 0x44200
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#define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe))
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#define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31)
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#define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10)
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#define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10)
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#define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10)
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#define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10)
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#define PCH_INTERRUPT_VBLANK_BDW (1 << 0)
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// graphics port control (i.e. G45)
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#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
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#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
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@@ -84,18 +84,94 @@ release_vblank_sem(intel_info &info)
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}
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static void
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bdw_enable_interrupts(intel_info& info, pipe_index pipe, bool enable)
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{
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ASSERT(pipe != INTEL_PIPE_ANY);
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ASSERT(info.device_type.Generation() >= 12 || pipe != INTEL_PIPE_D);
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const uint32 regMask = PCH_INTERRUPT_PIPE_MASK_BDW(pipe);
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const uint32 regEnabled = PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe);
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const uint32 regIdentity = PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe);
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const uint32 value = enable ? PCH_INTERRUPT_VBLANK_BDW : 0;
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write32(info, regIdentity, ~0);
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write32(info, regEnabled, value);
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write32(info, regMask, ~value);
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}
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static void
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bdw_enable_global_interrupts(intel_info& info, bool enable)
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{
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const uint32 bit = PCH_MASTER_INT_CTL_GLOBAL_BDW;
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const uint32 mask = enable ? bit : 0;
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const uint32 value = read32(info, PCH_MASTER_INT_CTL_BDW);
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write32(info, PCH_MASTER_INT_CTL_BDW, (value & ~bit) | mask);
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}
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/*!
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Checks interrupt status in master interrupt control register.
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For Gen8 to Gen11. From Gen11 the register is called DISPLAY_INT_CTL.
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*/
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static bool
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bdw_check_interrupt(intel_info& info, pipes& which)
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{
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ASSERT(info.device_type.Generation() >= 12 || !which.HasPipe(INTEL_PIPE_D));
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which.ClearPipe(INTEL_PIPE_ANY);
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const uint32 interrupt = read32(info, PCH_MASTER_INT_CTL_BDW);
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if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_A)) != 0)
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which.SetPipe(INTEL_PIPE_A);
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if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_B)) != 0)
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which.SetPipe(INTEL_PIPE_B);
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if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_C)) != 0)
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which.SetPipe(INTEL_PIPE_C);
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if ((interrupt & PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(INTEL_PIPE_D)) != 0)
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which.SetPipe(INTEL_PIPE_D);
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return which.HasPipe(INTEL_PIPE_ANY);
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}
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/*!
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Checks vblank interrupt status for a specified pipe.
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Gen8 to Gen12.
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*/
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static bool
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bdw_check_pipe_interrupt(intel_info& info, pipe_index pipe)
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{
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ASSERT(pipe != INTEL_PIPE_ANY);
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ASSERT(info.device_type.Generation() >= 12 || pipe != INTEL_PIPE_D);
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const uint32 identity = read32(info, PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe));
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return (identity & PCH_INTERRUPT_VBLANK_BDW) != 0;
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}
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static void
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bdw_clear_pipe_interrupt(intel_info& info, pipe_index pipe)
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{
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ASSERT(pipe != INTEL_PIPE_ANY);
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ASSERT(info.device_type.Generation() >= 12 || pipe != INTEL_PIPE_D);
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const uint32 regIdentity = PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe);
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const uint32 identity = read32(info, regIdentity);
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write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW);
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}
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/** Get the appropriate interrupt mask for enabling or testing interrupts on
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* the given pipes.
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* the given pipe.
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*
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* The bits to test or set are different depending on the hardware generation.
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*
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* \param info Intel_extreme driver information
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* \param pipes bit mask of the pipes to use
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* \param pipe pipe to use
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* \param enable true to get the mask for enabling the interrupts, false to get
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* the mask for testing them.
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*/
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static uint32
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intel_get_interrupt_mask(intel_info& info, int pipes, bool enable)
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intel_get_interrupt_mask(intel_info& info, pipe_index pipe, bool enable)
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{
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uint32 mask = 0;
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bool hasPCH = info.pch_info != INTEL_PCH_NONE;
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@@ -105,7 +181,7 @@ intel_get_interrupt_mask(intel_info& info, int pipes, bool enable)
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// The PCH register itself does not exist in pre-PCH platforms, and the
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// previous interrupt register of course also had a different mapping.
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if ((pipes & INTEL_PIPE_A) != 0) {
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if (pipe == INTEL_PIPE_A) {
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if (info.device_type.InGroup(INTEL_GROUP_SNB)
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|| info.device_type.InGroup(INTEL_GROUP_ILK))
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mask |= PCH_INTERRUPT_VBLANK_PIPEA_SNB;
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@@ -115,7 +191,7 @@ intel_get_interrupt_mask(intel_info& info, int pipes, bool enable)
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mask |= INTERRUPT_VBLANK_PIPEA;
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}
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if ((pipes & INTEL_PIPE_B) != 0) {
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if (pipe == INTEL_PIPE_B) {
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if (info.device_type.InGroup(INTEL_GROUP_SNB)
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|| info.device_type.InGroup(INTEL_GROUP_ILK))
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mask |= PCH_INTERRUPT_VBLANK_PIPEB_SNB;
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@@ -126,7 +202,7 @@ intel_get_interrupt_mask(intel_info& info, int pipes, bool enable)
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}
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#if 0 // FIXME enable when we support the 3rd pipe
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if ((pipes & INTEL_PIPE_C) != 0) {
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if (pipe == INTEL_PIPE_C) {
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// Older generations only had two pipes
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if (hasPCH && info.device_type.Generation() > 6)
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mask |= PCH_INTERRUPT_VBLANK_PIPEC;
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@@ -142,58 +218,164 @@ intel_get_interrupt_mask(intel_info& info, int pipes, bool enable)
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}
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static void
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intel_enable_interrupts(intel_info& info, pipes which, bool enable)
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{
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uint32 finalMask = 0;
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const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, true);
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const uint32 pipeBMask = intel_get_interrupt_mask(info, INTEL_PIPE_B, true);
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if (which.HasPipe(INTEL_PIPE_A))
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finalMask |= pipeAMask;
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if (which.HasPipe(INTEL_PIPE_B))
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finalMask |= pipeBMask;
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const uint32 value = enable ? finalMask : 0;
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// Clear all the interrupts
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write32(info, find_reg(info, INTEL_INTERRUPT_IDENTITY), ~0);
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// enable interrupts - we only want VBLANK interrupts
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write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), value);
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write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~value);
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}
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static bool
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intel_check_interrupt(intel_info& info, pipes& which)
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{
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which.ClearPipe(INTEL_PIPE_ANY);
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const uint32 pipeAMask = intel_get_interrupt_mask(info, INTEL_PIPE_A, false);
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const uint32 pipeBMask = intel_get_interrupt_mask(info, INTEL_PIPE_B, false);
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const uint32 regIdentity = find_reg(info, INTEL_INTERRUPT_IDENTITY);
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const uint32 interrupt = read32(info, regIdentity);
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if ((interrupt & pipeAMask) != 0)
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which.SetPipe(INTEL_PIPE_A);
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if ((interrupt & pipeBMask) != 0)
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which.SetPipe(INTEL_PIPE_B);
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return which.HasPipe(INTEL_PIPE_ANY);
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}
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static void
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g35_clear_interrupt_status(intel_info& info, pipe_index pipe)
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{
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// These registers do not exist on later GPUs.
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if (info.device_type.Generation() > 4)
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return;
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const uint32 value = DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED;
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switch (pipe) {
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case INTEL_PIPE_A:
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write32(info, INTEL_DISPLAY_A_PIPE_STATUS, value);
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break;
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case INTEL_PIPE_B:
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write32(info, INTEL_DISPLAY_B_PIPE_STATUS, value);
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break;
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default:
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break;
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}
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}
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static void
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intel_clear_pipe_interrupt(intel_info& info, pipe_index pipe)
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{
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// On G35/G45, prior to clearing Display Pipe interrupt in IIR
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// the corresponding interrupt status must first be cleared.
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g35_clear_interrupt_status(info, pipe);
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const uint32 regIdentity = find_reg(info, INTEL_INTERRUPT_IDENTITY);
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const uint32 bit = intel_get_interrupt_mask(info, pipe, false);
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const uint32 identity = read32(info, regIdentity);
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write32(info, regIdentity, identity | bit);
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}
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/*!
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Interrupt routine for Gen8 and Gen9.
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TODO: Gen11 and 12 require one additional check at the beginning.
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See Gen12 Display Engine: Interrupt Service Routine chapter.
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*/
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static int32
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bdw_interrupt_handler(void* data)
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{
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intel_info& info = *(intel_info*)data;
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bdw_enable_global_interrupts(info, false);
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pipes which;
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bool shouldHandle = bdw_check_interrupt(info, which);
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if (!shouldHandle) {
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bdw_enable_global_interrupts(info, true);
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return B_UNHANDLED_INTERRUPT;
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}
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int32 handled = B_HANDLED_INTERRUPT;
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while (shouldHandle) {
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if (which.HasPipe(INTEL_PIPE_A) && bdw_check_pipe_interrupt(info, INTEL_PIPE_A)) {
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handled = release_vblank_sem(info);
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bdw_clear_pipe_interrupt(info, INTEL_PIPE_A);
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}
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if (which.HasPipe(INTEL_PIPE_B) && bdw_check_pipe_interrupt(info, INTEL_PIPE_B)) {
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handled = release_vblank_sem(info);
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bdw_clear_pipe_interrupt(info, INTEL_PIPE_B);
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}
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if (which.HasPipe(INTEL_PIPE_C) && bdw_check_pipe_interrupt(info, INTEL_PIPE_C)) {
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handled = release_vblank_sem(info);
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bdw_clear_pipe_interrupt(info, INTEL_PIPE_C);
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}
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shouldHandle = bdw_check_interrupt(info, which);
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}
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bdw_enable_global_interrupts(info, true);
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return handled;
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}
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static int32
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intel_interrupt_handler(void* data)
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{
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intel_info &info = *(intel_info*)data;
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uint32 reg = find_reg(info, INTEL_INTERRUPT_IDENTITY);
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uint32 identity;
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identity = read32(info, reg);
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pipes which;
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bool shouldHandle = intel_check_interrupt(info, which);
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if (identity == 0)
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if (!shouldHandle)
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return B_UNHANDLED_INTERRUPT;
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int32 handled = B_HANDLED_INTERRUPT;
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while (identity != 0) {
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uint32 mask = intel_get_interrupt_mask(info, INTEL_PIPE_A, false);
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if ((identity & mask) != 0) {
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while (shouldHandle) {
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if (which.HasPipe(INTEL_PIPE_A)) {
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handled = release_vblank_sem(info);
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// make sure we'll get another one of those
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write32(info, INTEL_DISPLAY_A_PIPE_STATUS,
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DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED);
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intel_clear_pipe_interrupt(info, INTEL_PIPE_A);
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}
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mask = intel_get_interrupt_mask(info, INTEL_PIPE_B, false);
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if ((identity & mask) != 0) {
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if (which.HasPipe(INTEL_PIPE_B)) {
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handled = release_vblank_sem(info);
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// make sure we'll get another one of those
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write32(info, INTEL_DISPLAY_B_PIPE_STATUS,
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DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED);
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intel_clear_pipe_interrupt(info, INTEL_PIPE_B);
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}
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#if 0
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// FIXME we don't have support for the 3rd pipe yet
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mask = hasPCH ? PCH_INTERRUPT_VBLANK_PIPEC
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: 0;
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if ((identity & mask) != 0) {
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if (which.HasPipe(INTEL_PIPE_C)) {
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handled = release_vblank_sem(info);
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// make sure we'll get another one of those
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write32(info, INTEL_DISPLAY_C_PIPE_STATUS,
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DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED);
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intel_clear_pipe_interrupt(info, INTEL_PIPE_C);
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}
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#endif
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// setting the bit clears it!
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write32(info, reg, identity);
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// update our identity register with the remaining interupts
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identity = read32(info, reg);
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shouldHandle = intel_check_interrupt(info, which);
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}
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return handled;
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@@ -242,23 +424,26 @@ init_interrupt_handler(intel_info &info)
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info.fake_interrupts = false;
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if (info.device_type.Generation() >= 8) {
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status = install_io_interrupt_handler(info.irq,
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&bdw_interrupt_handler, (void*)&info, 0);
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if (status == B_OK) {
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bdw_enable_global_interrupts(info, true);
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bdw_enable_interrupts(info, INTEL_PIPE_A, true);
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bdw_enable_interrupts(info, INTEL_PIPE_B, true);
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}
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} else {
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status = install_io_interrupt_handler(info.irq,
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&intel_interrupt_handler, (void*)&info, 0);
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if (status == B_OK) {
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write32(info, INTEL_DISPLAY_A_PIPE_STATUS,
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DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED);
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write32(info, INTEL_DISPLAY_B_PIPE_STATUS,
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DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED);
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g35_clear_interrupt_status(info, INTEL_PIPE_A);
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g35_clear_interrupt_status(info, INTEL_PIPE_B);
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uint32 enable = intel_get_interrupt_mask(info,
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INTEL_PIPE_A | INTEL_PIPE_B, true);
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// Clear all the interrupts
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write32(info, find_reg(info, INTEL_INTERRUPT_IDENTITY), ~0);
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// enable interrupts - we only want VBLANK interrupts
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write32(info, find_reg(info, INTEL_INTERRUPT_ENABLED), enable);
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write32(info, find_reg(info, INTEL_INTERRUPT_MASK), ~enable);
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pipes which;
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which.SetPipe(INTEL_PIPE_A);
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which.SetPipe(INTEL_PIPE_B);
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intel_enable_interrupts(info, which, true);
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}
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}
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}
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if (status < B_OK) {
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