From ff20b3ad82db39ce92c282f35b7a74c236d818a0 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Fri, 24 Dec 2004 22:43:06 +0000 Subject: [PATCH] fixed GeForce AGP/PCIe 6600 PLL trouble (refreshrate), added fifo assignment usage remark. Note that GeForce 6600 and 6800 have the acc and overlay engines still down. Apart from that, they work (if you try the code now, the driver will still hang though..) Hope to fix these remaining issues soon.. git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10531 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_acc.c | 10 ++++++++-- src/add-ons/accelerants/nvidia/engine/nv_info.c | 4 +++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc.c b/src/add-ons/accelerants/nvidia/engine/nv_acc.c index 9ecda311eb..f5eabe1443 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc.c @@ -26,8 +26,7 @@ blit nVidia hardware info: We should be able to do FIFO assignment setup changes on-the-fly now, using all the engine-command-handles that are pre-defined on any FIFO channel. - (check channel to be emptied, then re-assign to new command, then use: etc.) - + Maybe we can even setup new additional handles to previously unused engine commands now, and there might even be a chance DMA can be setup(?). */ @@ -1060,6 +1059,13 @@ static void nv_init_for_3D(void) } } +/* fixme? (check this out..) + * Looks like this stuff can be very much simplified and speed-up, as it seems it's not + * nessesary to wait for the engine to become idle before re-assigning channels. + * Because the cmd handles are actually programmed _inside_ the fifo channels, it might + * well be that the assignment is buffered along with the commands that still have to + * be executed! + * (sounds very plausible to me :) */ void nv_acc_assert_fifo(void) { /* does every engine cmd this accelerant needs have a FIFO channel? */ diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c index f65c921929..6c4392ce8a 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c @@ -1,7 +1,7 @@ /* Read initialisation information from card */ /* some bits are hacks, where PINS is not known */ /* Author: - Rudolf Cornelissen 7/2003-10/2004 + Rudolf Cornelissen 7/2003-12/2004 */ #define MODULE_BIT 0x00002000 @@ -2807,7 +2807,9 @@ static void pinsnv30_arch_fake(void) { case NV31: case NV36: + /* fixme? could be all >= NV40 cards have extended PLL's... (these 2 are confirmed) */ case NV40: + case NV43: /* we have a extended PLL */ si->ps.ext_pll = true; break;