diff --git a/src/add-ons/accelerants/radeon/CP.c b/src/add-ons/accelerants/radeon/CP.c
index cfe219121d..dbcdb4a08b 100644
--- a/src/add-ons/accelerants/radeon/CP.c
+++ b/src/add-ons/accelerants/radeon/CP.c
@@ -330,7 +330,7 @@ void Radeon_SendIndirectBuffer( accelerator_info *ai,
 	// (this code is a bit of a overkill - currently, only some WinChip/Cyrix 
 	//  CPU's support out-of-order writes, but we are prepared)
 	// TODO : Other Architectures? PowerPC?
-	#if defined(__x86__) || defined(__x86_64__)
+	#ifdef __INTEL__
 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory");
 	#endif
 	// make sure the motherboard chipset has flushed its write buffer by
diff --git a/src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c b/src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c
index 8016c8b617..b9d9c7b208 100644
--- a/src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c
+++ b/src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c
@@ -234,9 +234,9 @@ static status_t initGATT( GART_info *gart )
 	// back to real live - some chipsets have write buffers that
 	// proove all previous assumptions wrong
 	// (don't know whether this really helps though)
-	#if defined(__x86__) || defined(__x86_64__)
+	#if defined(__INTEL__)
 	asm volatile ( "wbinvd" ::: "memory" );
-	#elif defined(__powerpc__)
+	#elif defined(__POWERPC__)
 	// TODO : icbi on PowerPC to flush instruction cache?
 	#endif
 	return B_OK;