David Karoly
60b19d7eac
Change-Id: I24219b83d90710ef719190183ba6f069f82dae61 Reviewed-on: https://review.haiku-os.org/c/haiku/+/6198 Tested-by: Automation <[email protected]> Reviewed-by: Adrien Destugues <[email protected]>
91 lines
1.6 KiB
C
91 lines
1.6 KiB
C
/*
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** Copyright 2003-2004, Axel Dörfler, [email protected]. All rights reserved.
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** Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_ARM_CPU_H
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#define _KERNEL_ARCH_ARM_CPU_H
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 64
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// TODO: Could be 32-bits sometimes?
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#define set_ac()
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#define clear_ac()
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#ifndef _ASSEMBLER
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#include <arch/arm/arch_thread_types.h>
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#include <kernel.h>
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/**! Values for arch_cpu_info.arch */
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enum {
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ARCH_ARM_PRE_ARM7,
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ARCH_ARM_v3,
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ARCH_ARM_v4,
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ARCH_ARM_v4T,
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ARCH_ARM_v5,
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ARCH_ARM_v5T,
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ARCH_ARM_v5TE,
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ARCH_ARM_v5TEJ,
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ARCH_ARM_v6,
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ARCH_ARM_v7
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};
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typedef struct arch_cpu_info {
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/* For a detailed interpretation of these values,
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see "The System Control coprocessor",
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"Main ID register" in your ARM ARM */
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int implementor;
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int part_number;
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int revision;
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int variant;
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int arch;
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} arch_cpu_info;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint32 arm_get_dfsr(void);
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extern uint32 arm_get_ifsr(void);
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extern addr_t arm_get_dfar(void);
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extern addr_t arm_get_ifar(void);
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extern addr_t arm_get_fp(void);
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extern int mmu_read_c1(void);
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extern int mmu_write_c1(int val);
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void arch_cpu_invalidate_TLB_page(addr_t page);
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static inline void
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arch_cpu_pause(void)
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{
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// TODO: ARM Priority pause call
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}
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static inline void
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arch_cpu_idle(void)
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{
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uint32 Rd = 0;
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asm volatile("mcr p15, 0, %[c7format], c7, c0, 4"
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: : [c7format] "r" (Rd) );
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}
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#ifdef __cplusplus
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};
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#endif
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#endif // !_ASSEMBLER
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#endif /* _KERNEL_ARCH_ARM_CPU_H */
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