Augustin Cavalier
6f88de113d
These are architecture-specific routines, so they deserve proper architecture-specific naming. The user memory access routines are already under arch_cpu (arch_cpu_user_memcpy, etc.), and the methods usually change a CPU flag, so it makes sense to put these there too. RISC-V had get_ac but nothing else defined or used it, so it's removed. No functional change intended. Change-Id: Id4715214e32f73d4a93bc7ba8249411a0878d174 Reviewed-on: https://review.haiku-os.org/c/haiku/+/8106 Reviewed-by: waddlesplash <[email protected]> Reviewed-by: X512 X512 <[email protected]> Reviewed-by: Jérôme Duval <[email protected]> Tested-by: Commit checker robot <[email protected]>
137 lines
2.9 KiB
C
137 lines
2.9 KiB
C
/*
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** Copyright 2003-2004, Axel Dörfler, [email protected]. All rights reserved.
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** Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_ARM_CPU_H
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#define _KERNEL_ARCH_ARM_CPU_H
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 64
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// TODO: Could be 32-bits sometimes?
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#define wfi() __asm__ __volatile__("wfi" : : : "memory")
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#define arch_cpu_enable_user_access()
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#define arch_cpu_disable_user_access()
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#ifndef _ASSEMBLER
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#include <arch/arm/arch_thread_types.h>
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#include <kernel.h>
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/**! Values for arch_cpu_info.arch */
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enum {
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ARCH_ARM_PRE_ARM7,
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ARCH_ARM_v3,
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ARCH_ARM_v4,
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ARCH_ARM_v4T,
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ARCH_ARM_v5,
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ARCH_ARM_v5T,
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ARCH_ARM_v5TE,
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ARCH_ARM_v5TEJ,
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ARCH_ARM_v6,
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ARCH_ARM_v7
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};
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typedef struct arch_cpu_info {
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/* For a detailed interpretation of these values,
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see "The System Control coprocessor",
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"Main ID register" in your ARM ARM */
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int implementor;
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int part_number;
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int revision;
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int variant;
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int arch;
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} arch_cpu_info;
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DEFINE_ARM_GET_REG(name, cp, opc1, crn, crm, opc2) \
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static inline uint32 \
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arm_get_##name(void) \
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{ \
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uint32 res; \
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asm volatile ("mrc " #cp ", " #opc1 ", %0, " #crn ", " #crm ", " #opc2 : "=r" (res)); \
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return res; \
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}
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#define DEFINE_ARM_SET_REG(name, cp, opc1, crn, crm, opc2) \
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static inline void \
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arm_set_##name(uint32 val) \
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{ \
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asm volatile ("mcr " #cp ", " #opc1 ", %0, " #crn ", " #crm ", " #opc2 :: "r" (val)); \
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}
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/* CP15 c1, System Control Register */
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DEFINE_ARM_GET_REG(sctlr, p15, 0, c1, c0, 0)
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DEFINE_ARM_SET_REG(sctlr, p15, 0, c1, c0, 0)
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/* CP15 c2, Translation table support registers */
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DEFINE_ARM_GET_REG(ttbr0, p15, 0, c2, c0, 0)
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DEFINE_ARM_SET_REG(ttbr0, p15, 0, c2, c0, 0)
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DEFINE_ARM_GET_REG(ttbr1, p15, 0, c2, c0, 1)
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DEFINE_ARM_SET_REG(ttbr1, p15, 0, c2, c0, 1)
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DEFINE_ARM_GET_REG(ttbcr, p15, 0, c2, c0, 2)
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DEFINE_ARM_SET_REG(ttbcr, p15, 0, c2, c0, 2)
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/* CP15 c5 and c6, Memory system fault registers */
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DEFINE_ARM_GET_REG(dfsr, p15, 0, c5, c0, 0)
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DEFINE_ARM_GET_REG(ifsr, p15, 0, c5, c0, 1)
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DEFINE_ARM_GET_REG(dfar, p15, 0, c6, c0, 0)
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DEFINE_ARM_GET_REG(ifar, p15, 0, c6, c0, 2)
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/* CP15 c13, Process, context and thread ID registers */
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DEFINE_ARM_GET_REG(tpidruro, p15, 0, c13, c0, 3)
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DEFINE_ARM_SET_REG(tpidruro, p15, 0, c13, c0, 3)
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DEFINE_ARM_GET_REG(tpidrprw, p15, 0, c13, c0, 4)
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DEFINE_ARM_SET_REG(tpidrprw, p15, 0, c13, c0, 4)
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#undef DEFINE_ARM_GET_REG
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#undef DEFINE_ARM_SET_REG
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static inline addr_t
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arm_get_fp(void)
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{
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uint32 res;
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asm volatile ("mov %0, fp": "=r" (res));
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return res;
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}
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void arch_cpu_invalidate_TLB_page(addr_t page);
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static inline void
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arch_cpu_pause(void)
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{
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// TODO: ARM Priority pause call
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}
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static inline void
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arch_cpu_idle(void)
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{
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wfi();
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}
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#ifdef __cplusplus
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};
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#endif
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#endif // !_ASSEMBLER
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#endif /* _KERNEL_ARCH_ARM_CPU_H */
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