Stephan Aßmus
7749d0bb0c
by "jarz" to rewrite the last remaining (?) headers in order to get rid of the Be copyright. Thanks a lot and sorry for the long delay. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42958 a95241bf-73f2-0310-859d-f6bbb57e9c96
578 lines
18 KiB
C
578 lines
18 KiB
C
/*
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* Copyright 2010-2011, Haiku Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef _PCI_H
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#define _PCI_H
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#include <SupportDefs.h>
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#include <bus_manager.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* pci device info */
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typedef struct pci_info pci_info;
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typedef struct pci_info {
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uint16 vendor_id; /* vendor id */
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uint16 device_id; /* device id */
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uchar bus; /* bus number */
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uchar device; /* device number on bus */
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uchar function; /* function number in device */
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uchar revision; /* revision id */
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uchar class_api; /* specific register interface type */
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uchar class_sub; /* specific device function */
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uchar class_base; /* device type (display vs network, etc) */
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uchar line_size; /* cache line size in 32 bit words */
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uchar latency; /* latency timer */
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uchar header_type; /* header type */
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uchar bist; /* built-in self-test */
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uchar reserved; /* filler, for alignment */
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union {
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struct {
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uint32 cardbus_cis; /* CardBus CIS pointer */
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uint16 subsystem_id; /* subsystem (add-in card) id */
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uint16 subsystem_vendor_id; /* subsystem vendor id */
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uint32 rom_base; /* rom base addr, view from host */
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uint32 rom_base_pci; /* rom base addr, viewed from pci */
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uint32 rom_size; /* rom size */
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uint32 base_registers[6]; /* base registers, view from host */
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uint32 base_registers_pci[6]; /* base registers, view from pci */
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uint32 base_register_sizes[6]; /* size of what base regs point */
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uchar base_register_flags[6]; /* flags from base address fields */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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uchar min_grant; /* burst period @ 33 Mhz */
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uchar max_latency; /* how often PCI access needed */
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} h0;
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struct {
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uint32 base_registers[2]; /* base registers, view from host */
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uint32 base_registers_pci[2]; /* base registers, view from pci */
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uint32 base_register_sizes[2]; /* size of what base regs point */
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uchar base_register_flags[2]; /* flags from base address fields */
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uchar primary_bus;
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uchar secondary_bus;
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uchar subordinate_bus;
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uchar secondary_latency;
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uchar io_base;
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uchar io_limit;
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uint16 secondary_status;
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uint16 memory_base;
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uint16 memory_limit;
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uint16 prefetchable_memory_base;
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uint16 prefetchable_memory_limit;
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uint32 prefetchable_memory_base_upper32;
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uint32 prefetchable_memory_limit_upper32;
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uint16 io_base_upper16;
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uint16 io_limit_upper16;
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uint32 rom_base; /* rom base addr, view from host */
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uint32 rom_base_pci; /* rom base addr, view from pci */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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uint16 bridge_control;
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uint16 subsystem_id; /* subsystem (add-in card) id */
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uint16 subsystem_vendor_id; /* subsystem vendor id */
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} h1;
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struct {
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uint16 subsystem_id; /* subsystem (add-in card) id */
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uint16 subsystem_vendor_id; /* subsystem vendor id */
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#ifdef __HAIKU_PCI_BUS_MANAGER_TESTING
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// for testing only, not final (do not use!):
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uchar primary_bus;
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uchar secondary_bus;
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uchar subordinate_bus;
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uchar secondary_latency;
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uint16 reserved;
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uint32 memory_base;
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uint32 memory_limit;
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uint32 memory_base_upper32;
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uint32 memory_limit_upper32;
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uint32 io_base;
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uint32 io_limit;
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uint32 io_base_upper32;
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uint32 io_limit_upper32;
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uint16 secondary_status;
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uint16 bridge_control;
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#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
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} h2;
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} u;
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};
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typedef struct pci_module_info pci_module_info;
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typedef struct pci_module_info {
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bus_manager_info binfo;
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uint8 (*read_io_8) (int32 mapped_io_addr);
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void (*write_io_8) (int32 mapped_io_addr, uint8 value);
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uint16 (*read_io_16) (int32 mapped_io_addr);
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void (*write_io_16) (int32 mapped_io_addr, uint16 value);
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uint32 (*read_io_32) (int32 mapped_io_addr);
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void (*write_io_32) (int32 mapped_io_addr, uint32 value);
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int32 (*get_nth_pci_info) (
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int32 index, /* index into pci device table */
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pci_info *info /* caller-supplied buf for info */
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);
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uint32 (*read_pci_config) (
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uchar bus, /* bus number */
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uchar device, /* device # on bus */
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uchar function, /* function # in device */
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uchar offset, /* offset in configuration space */
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uchar size /* # bytes to read (1, 2 or 4) */
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);
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void (*write_pci_config) (
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uchar bus, /* bus number */
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uchar device, /* device # on bus */
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uchar function, /* function # in device */
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uchar offset, /* offset in configuration space */
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uchar size, /* # bytes to write (1, 2 or 4) */
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uint32 value /* value to write */
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);
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void* (*ram_address)
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(const void* physical_address_in_system_memory);
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status_t (*find_pci_capability) (
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uchar bus,
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uchar device,
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uchar function,
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uchar cap_id,
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uchar *offset
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);
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status_t (*reserve_device) (
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uchar bus,
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uchar device,
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uchar function,
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const char* driver_name,
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void* cookie);
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status_t (*unreserve_device) (
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uchar bus,
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uchar device,
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uchar function,
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const char* driver_name,
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void* cookie);
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status_t (*update_interrupt_line) (
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uchar bus,
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uchar device,
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uchar function,
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uchar newInterruptLineValue);
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};
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#define B_PCI_MODULE_NAME "bus_managers/pci/v1"
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/* offsets in PCI config space to the elements of the predefined header */
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/* offsets common to all header types */
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#define PCI_vendor_id 0x00 /* vendor id */
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#define PCI_device_id 0x02 /* device id */
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#define PCI_command 0x04 /* command */
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#define PCI_status 0x06 /* status */
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#define PCI_revision 0x08 /* revision id */
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#define PCI_class_api 0x09 /* specific register interface type */
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#define PCI_class_sub 0x0A /* specific device function */
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#define PCI_class_base 0x0B /* device type */
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#define PCI_line_size 0x0C /* cache line size in 32 bit words */
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#define PCI_latency 0x0D /* latency timer */
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#define PCI_header_type 0x0E /* header type */
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#define PCI_bist 0x0F /* built-in self-test */
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/* offsets common to header types 0x00 and 0x01 */
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#define PCI_base_registers 0x10 /* base registers */
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#define PCI_interrupt_line 0x3C /* interrupt line */
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#define PCI_interrupt_pin 0x3D /* interrupt pin */
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/* offsets common to header type 0x00 */
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#define PCI_cardbus_cis 0x28 /* CardBus CIS pointer */
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#define PCI_subsystem_vendor_id 0x2C /* subsystem vendor id */
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#define PCI_subsystem_id 0x2E /* subsystem id */
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#define PCI_rom_base 0x30 /* expansion rom base address */
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#define PCI_capabilities_ptr 0x34 /* point to start of cap list */
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#define PCI_min_grant 0x3E /* burst period @ 33 Mhz */
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#define PCI_max_latency 0x3F /* how often need PCI access */
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/* offsets common to the elements of header type 0x01 (PCI-to-PCI bridge) */
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#define PCI_primary_bus 0x18
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#define PCI_secondary_bus 0x19
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#define PCI_subordinate_bus 0x1A
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#define PCI_secondary_latency 0x1B
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#define PCI_io_base 0x1C
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#define PCI_io_limit 0x1D
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#define PCI_secondary_status 0x1E
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#define PCI_memory_base 0x20
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#define PCI_memory_limit 0x22
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#define PCI_prefetchable_memory_base 0x24
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#define PCI_prefetchable_memory_limit 0x26
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#define PCI_prefetchable_memory_base_upper32 0x28
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#define PCI_prefetchable_memory_limit_upper32 0x2C
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#define PCI_io_base_upper16 0x30
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#define PCI_io_limit_upper16 0x32
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#define PCI_sub_vendor_id_1 0x34
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#define PCI_sub_device_id_1 0x36
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#define PCI_bridge_rom_base 0x38
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#define PCI_bridge_control 0x3E
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/* PCI type 2 header offsets */
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#define PCI_capabilities_ptr_2 0x14
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#define PCI_secondary_status_2 0x16
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#define PCI_primary_bus_2 0x18
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#define PCI_secondary_bus_2 0x19
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#define PCI_subordinate_bus_2 0x1A
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#define PCI_secondary_latency_2 0x1B
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#define PCI_memory_base0_2 0x1C
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#define PCI_memory_limit0_2 0x20
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#define PCI_memory_base1_2 0x24
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#define PCI_memory_limit1_2 0x28
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#define PCI_io_base0_2 0x2C
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#define PCI_io_limit0_2 0x30
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#define PCI_io_base1_2 0x34
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#define PCI_io_limit1_2 0x38
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#define PCI_bridge_control_2 0x3E
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#define PCI_sub_vendor_id_2 0x40
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#define PCI_sub_device_id_2 0x42
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#define PCI_card_interface_2 0x44
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/* values for the class_base field in the common header */
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#define PCI_early 0x00
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#define PCI_mass_storage 0x01
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#define PCI_network 0x02
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#define PCI_display 0x03
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#define PCI_multimedia 0x04
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#define PCI_memory 0x05
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#define PCI_bridge 0x06
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#define PCI_simple_communications 0x07
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#define PCI_base_peripheral 0x08
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#define PCI_input 0x09
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#define PCI_docking_station 0x0A
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#define PCI_processor 0x0B
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#define PCI_serial_bus 0x0C
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#define PCI_wireless 0x0D
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#define PCI_intelligent_io 0x0E
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#define PCI_satellite_communications 0x0F
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#define PCI_encryption_decryption 0x10
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#define PCI_data_acquisition 0x11
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#define PCI_undefined 0xFF
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/* values for the class_sub field for class_base = 0x00 (early) */
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#define PCI_early_not_vga 0x00
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#define PCI_early_vga 0x01
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/* values for the class_sub field for class_base = 0x01 (mass storage) */
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#define PCI_scsi 0x00
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#define PCI_ide 0x01
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#define PCI_floppy 0x02
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#define PCI_ipi 0x03
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#define PCI_raid 0x04
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#define PCI_ata 0x05
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#define PCI_sata 0x06
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#define PCI_sas 0x07
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#define PCI_mass_storage_other 0x80
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/* values of the class_api field for class_base = 0x01, class_sub = 0x06 */
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#define PCI_sata_other 0x00
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#define PCI_sata_ahci 0x01
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/* values for the class_sub field for class_base = 0x02 (network) */
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#define PCI_ethernet 0x00
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#define PCI_token_ring 0x01
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#define PCI_fddi 0x02
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#define PCI_atm 0x03
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#define PCI_isdn 0x04
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#define PCI_network_other 0x80
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/* values for the class_sub field for class_base = 0x03 (display) */
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#define PCI_vga 0x00
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#define PCI_xga 0x01
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#define PCI_3d 0x02
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#define PCI_display_other 0x80
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/* values for the class_sub field for class_base = 0x04 (multimedia device) */
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#define PCI_video 0x00
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#define PCI_audio 0x01
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#define PCI_telephony 0x02
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#define PCI_hd_audio 0x03
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#define PCI_multimedia_other 0x80
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/* values for the class_sub field for class_base = 0x05 (memory) */
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#define PCI_ram 0x00
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#define PCI_flash 0x01
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#define PCI_memory_other 0x80
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/* values for the class_sub field for class_base = 0x06 (bridge) */
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#define PCI_host 0x00
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#define PCI_isa 0x01
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#define PCI_eisa 0x02
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#define PCI_microchannel 0x03
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#define PCI_pci 0x04
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#define PCI_pcmcia 0x05
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#define PCI_nubus 0x06
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#define PCI_cardbus 0x07
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#define PCI_raceway 0x08
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#define PCI_bridge_transparent 0x09
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#define PCI_bridge_infiniband 0x0A
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#define PCI_bridge_other 0x80
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/* values for the class_sub field for class_base = 0x07 (simple comm ctrlers) */
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#define PCI_serial 0x00
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#define PCI_parallel 0x01
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#define PCI_multiport_serial 0x02
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#define PCI_modem 0x03
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#define PCI_simple_communications_other 0x80
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/* values of the class_api field for class_base = 0x07 and class_sub = 0x00 */
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#define PCI_serial_xt 0x00
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#define PCI_serial_16450 0x01
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#define PCI_serial_16550 0x02
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/* values of the class_api field for class_base = 0x07 and class_sub = 0x01 */
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#define PCI_parallel_simple 0x00
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#define PCI_parallel_bidirectional 0x01
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#define PCI_parallel_ecp 0x02
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/* values for the class_sub field for class_base = 0x08 (system peripherals) */
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#define PCI_pic 0x00
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#define PCI_dma 0x01
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#define PCI_timer 0x02
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#define PCI_rtc 0x03
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#define PCI_generic_hot_plug 0x04
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#define PCI_system_peripheral_other 0x80
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/* values of the class_api field for class_base = 0x08 and class_sub = 0x00 */
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#define PCI_pic_8259 0x00
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#define PCI_pic_isa 0x01
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#define PCI_pic_eisa 0x02
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/* values of the class_api field for class_base = 0x08 and class_sub = 0x01 */
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#define PCI_dma_8237 0x00
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#define PCI_dma_isa 0x01
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#define PCI_dma_eisa 0x02
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/* values of the class_api field for class_base = 0x08 and class_sub = 0x02 */
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#define PCI_timer_8254 0x00
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#define PCI_timer_isa 0x01
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#define PCI_timer_eisa 0x02
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/* values of the class_api field for class_base = 0x08 and class_sub = 0x03 */
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#define PCI_rtc_generic 0x00
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#define PCI_rtc_isa 0x01
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/* values for the class_sub field for class_base = 0x09 (input devices) */
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#define PCI_keyboard 0x00
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#define PCI_pen 0x01
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#define PCI_mouse 0x02
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#define PCI_scanner 0x03
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#define PCI_gameport 0x04
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#define PCI_input_other 0x80
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/* values for the class_sub field for class_base = 0x0A (docking stations) */
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#define PCI_docking_generic 0x00
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#define PCI_docking_other 0x80
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/* values for the class_sub field for class_base = 0x0B (processor) */
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#define PCI_386 0x00
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#define PCI_486 0x01
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#define PCI_pentium 0x02
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#define PCI_alpha 0x10
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#define PCI_PowerPC 0x20
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#define PCI_mips 0x30
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#define PCI_coprocessor 0x40
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/* values for the class_sub field for class_base = 0x0C (serial bus ctrlr) */
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#define PCI_firewire 0x00
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#define PCI_access 0x01
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#define PCI_ssa 0x02
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#define PCI_usb 0x03
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#define PCI_fibre_channel 0x04
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#define PCI_smbus 0x05
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#define PCI_infiniband 0x06
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#define PCI_ipmi 0x07
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#define PCI_sercos 0x08
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#define PCI_canbus 0x09
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/* values of the class_api field for class_base = 0x0C and class_sub = 0x03 */
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#define PCI_usb_uhci 0x00
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#define PCI_usb_ohci 0x10
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#define PCI_usb_ehci 0x20
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#define PCI_usb_xhci 0x30 /* Extensible Host Controller Interface */
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/* values for the class_sub field for class_base = 0x0d (wireless controller) */
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#define PCI_wireless_irda 0x00
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#define PCI_wireless_consumer_ir 0x01
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#define PCI_wireless_rf 0x02
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#define PCI_wireless_bluetooth 0x03
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#define PCI_wireless_broadband 0x04
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#define PCI_wireless_80211A 0x10
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#define PCI_wireless_80211B 0x20
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#define PCI_wireless_other 0x80
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/* masks for command register bits */
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#define PCI_command_io 0x001
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#define PCI_command_memory 0x002
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#define PCI_command_master 0x004
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#define PCI_command_special 0x008
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#define PCI_command_mwi 0x010
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#define PCI_command_vga_snoop 0x020
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#define PCI_command_parity 0x040
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#define PCI_command_address_step 0x080
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#define PCI_command_serr 0x100
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#define PCI_command_fastback 0x200
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#define PCI_command_int_disable 0x400
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/* masks for status register bits */
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#define PCI_status_capabilities 0x0010
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#define PCI_status_66_MHz_capable 0x0020
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#define PCI_status_udf_supported 0x0040
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#define PCI_status_fastback 0x0080
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#define PCI_status_parity_signalled 0x0100
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#define PCI_status_devsel 0x0600
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#define PCI_status_target_abort_signalled 0x0800
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#define PCI_status_target_abort_received 0x1000
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#define PCI_status_master_abort_received 0x2000
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#define PCI_status_serr_signalled 0x4000
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#define PCI_status_parity_error_detected 0x8000
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/* masks for devsel field in status register */
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#define PCI_status_devsel_fast 0x0000
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#define PCI_status_devsel_medium 0x0200
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#define PCI_status_devsel_slow 0x0400
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/* masks for header type register */
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#define PCI_header_type_mask 0x7F
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#define PCI_multifunction 0x80
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/* types of PCI header */
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#define PCI_header_type_generic 0x00
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#define PCI_header_type_PCI_to_PCI_bridge 0x01
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#define PCI_header_type_cardbus 0x02
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/* masks for built in self test (bist) register bits */
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#define PCI_bist_code 0x0F
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#define PCI_bist_start 0x40
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#define PCI_bist_capable 0x80
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/* masks for flags in the various base address registers */
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#define PCI_address_space 0x01
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#define PCI_register_start 0x10
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#define PCI_register_end 0x24
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#define PCI_register_ppb_end 0x18
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#define PCI_register_pcb_end 0x14
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/* masks for flags in memory space base address registers */
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#define PCI_address_type_32 0x00
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#define PCI_address_type_32_low 0x02
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#define PCI_address_type_64 0x04
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#define PCI_address_type 0x06
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#define PCI_address_prefetchable 0x08
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#define PCI_address_memory_32_mask 0xFFFFFFF0
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/* masks for flags in i/o space base address registers */
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#define PCI_address_io_mask 0xFFFFFFFC
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/* masks for flags in expansion rom base address registers */
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#define PCI_rom_enable 0x00000001
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#define PCI_rom_shadow 0x00000010 /* 2 rom copied at shadow (C0000) */
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#define PCI_rom_copy 0x00000100 /* 4 rom is allocated copy */
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#define PCI_rom_bios 0x00001000 /* 8 rom is bios copy */
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#define PCI_rom_address_mask 0xFFFFF800
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/* PCI interrupt pin values */
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#define PCI_pin_mask 0x07
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#define PCI_pin_none 0x00
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#define PCI_pin_a 0x01
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#define PCI_pin_b 0x02
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#define PCI_pin_c 0x03
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#define PCI_pin_d 0x04
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#define PCI_pin_max 0x04
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/* PCI Capability Codes */
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#define PCI_cap_id_reserved 0x00
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#define PCI_cap_id_pm 0x01
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#define PCI_cap_id_agp 0x02
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#define PCI_cap_id_vpd 0x03
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#define PCI_cap_id_slotid 0x04
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#define PCI_cap_id_msi 0x05
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#define PCI_cap_id_chswp 0x06
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#define PCI_cap_id_pcix 0x07
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#define PCI_cap_id_ldt 0x08
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#define PCI_cap_id_vendspec 0x09
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#define PCI_cap_id_debugport 0x0a
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#define PCI_cap_id_cpci_rsrcctl 0x0b
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#define PCI_cap_id_hotplug 0x0c
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#define PCI_cap_id_subvendor 0x0d
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#define PCI_cap_id_agp8x 0x0e
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#define PCI_cap_id_secure_dev 0x0f
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#define PCI_cap_id_pcie 0x10
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#define PCI_cap_id_msix 0x11
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#define PCI_cap_id_sata 0x12
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#define PCI_cap_id_pciaf 0x13
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/* Power Management Control Status Register settings */
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#define PCI_pm_mask 0x03
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#define PCI_pm_ctrl 0x02
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#define PCI_pm_d1supp 0x0200
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#define PCI_pm_d2supp 0x0400
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#define PCI_pm_status 0x04
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#define PCI_pm_state_d0 0x00
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#define PCI_pm_state_d1 0x01
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#define PCI_pm_state_d2 0x02
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#define PCI_pm_state_d3 0x03
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/* MSI registers */
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#define PCI_msi_control 0x02
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#define PCI_msi_address 0x04
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#define PCI_msi_address_high 0x08
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#define PCI_msi_data 0x08
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#define PCI_msi_data_64bit 0x0c
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#define PCI_msi_mask 0x10
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#define PCI_msi_pending 0x14
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/* MSI control register values */
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#define PCI_msi_control_enable 0x0001
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#define PCI_msi_control_vector 0x0100
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#define PCI_msi_control_64bit 0x0080
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#define PCI_msi_control_mme_mask 0x0070
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#define PCI_msi_control_mme_1 0x0000
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#define PCI_msi_control_mme_2 0x0010
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#define PCI_msi_control_mme_4 0x0020
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#define PCI_msi_control_mme_8 0x0030
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#define PCI_msi_control_mme_16 0x0040
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#define PCI_msi_control_mme_32 0x0050
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#define PCI_msi_control_mmc_mask 0x000e
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#define PCI_msi_control_mmc_1 0x0000
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#define PCI_msi_control_mmc_2 0x0002
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#define PCI_msi_control_mmc_4 0x0004
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#define PCI_msi_control_mmc_8 0x0006
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#define PCI_msi_control_mmc_16 0x0008
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#define PCI_msi_control_mmc_32 0x000a
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#ifdef __cplusplus
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}
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#endif
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#endif /* _PCI_H */
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