asix88xxx: Import drivers from FreeBSD to replace usb_asix.
The homegrown usb_asix was partially based on the upstream FreeBSD driver anyway, and hasn't seen much maintenance in recent years. We might as well replace it with the FreeBSD version. In the process, also add the "axge" driver, supporting the Gigabit version of this hardware. Tested by smrobtzz with the AX88179A: "it seems to work perfectly". Change-Id: I37fdfc2cef6100916d6034817f117286f7f443b2 Reviewed-on: https://review.haiku-os.org/c/haiku/+/9600 Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Augustin Cavalier
committed by
waddlesplash
waddlesplash
parent
9936387223
commit
000c32a568
@@ -312,6 +312,7 @@ SYSTEM_ADD_ONS_DRIVERS_MIDI = ;
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SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
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SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
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x86,x86_64,riscv64 @{
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x86,x86_64,riscv64 @{
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3com
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3com
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asix88xxx
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atheros813x
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atheros813x
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atheros81xx
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atheros81xx
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attansic_l1
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attansic_l1
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@@ -339,7 +340,6 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
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etherpci
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etherpci
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pegasus
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pegasus
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usb_asix
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usb_davicom
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usb_davicom
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usb_rndis
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usb_rndis
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wb840
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wb840
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@@ -4,7 +4,6 @@ SubDir HAIKU_TOP src add-ons kernel drivers network ether ;
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HaikuSubInclude etherpci ;
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HaikuSubInclude etherpci ;
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HaikuSubInclude pegasus ;
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HaikuSubInclude pegasus ;
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HaikuSubInclude virtio ;
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HaikuSubInclude virtio ;
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HaikuSubInclude usb_asix ;
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HaikuSubInclude usb_davicom ;
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HaikuSubInclude usb_davicom ;
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HaikuSubInclude usb_ecm ;
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HaikuSubInclude usb_ecm ;
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HaikuSubInclude usb_rndis ;
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HaikuSubInclude usb_rndis ;
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@@ -12,6 +11,7 @@ HaikuSubInclude wb840 ;
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# FreeBSD drivers
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# FreeBSD drivers
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HaikuSubInclude 3com ;
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HaikuSubInclude 3com ;
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HaikuSubInclude asix88xxx ;
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HaikuSubInclude atheros81xx ;
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HaikuSubInclude atheros81xx ;
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HaikuSubInclude atheros813x ;
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HaikuSubInclude atheros813x ;
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HaikuSubInclude attansic_l1 ;
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HaikuSubInclude attansic_l1 ;
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@@ -0,0 +1,32 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network ether asix88xxx ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ]
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: true ;
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UsePrivateHeaders net system ;
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UsePrivateKernelHeaders ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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UseHeaders [ FDirName $(SUBDIR) ] : true ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) dev mii ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) dev usb net ] ;
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KernelAddon asix88xxx :
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glue.c
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axphy.c
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if_axe.c
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if_axge.c
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:
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freebsd_mii.a
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freebsd_usb.a
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libfreebsd_network.a
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;
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ObjectHdrs [ FGristFiles if_axe$(SUFOBJ) if_axge$(SUFOBJ) ]
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: [ FDirName $(HAIKU_COMMON_PLATFORM_OBJECT_DIR) libs compat freebsd_network ] ;
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Includes [ FGristFiles if_axe.c if_axge.c ] : <src!libs!compat!freebsd_network>usbdevs.h ;
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ObjectHdrs [ FGristFiles axphy$(SUFOBJ) ]
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: [ FDirName $(HAIKU_COMMON_PLATFORM_OBJECT_DIR) libs compat freebsd_network ] ;
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Includes [ FGristFiles axphy.c ] : <src!libs!compat!freebsd_network>miidevs.h ;
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@@ -0,0 +1,174 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2009 M. Warner Losh <[email protected]>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* driver for internal phy in the AX88x9x chips.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include "miibus_if.h"
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static int axphy_probe(device_t dev);
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static int axphy_attach(device_t dev);
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static device_method_t axphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, axphy_probe),
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DEVMETHOD(device_attach, axphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t axphy_driver = {
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"axphy",
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axphy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(axphy, miibus, axphy_driver, 0, 0);
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static int axphy_service(struct mii_softc *, struct mii_data *, int);
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static void axphy_status(struct mii_softc *);
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static const struct mii_phydesc axphys[] = {
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MII_PHY_DESC(xxASIX, AX88X9X),
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MII_PHY_END
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};
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static const struct mii_phy_funcs axphy_funcs = {
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axphy_service,
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axphy_status,
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mii_phy_reset
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};
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static int
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axphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, axphys, BUS_PROBE_DEFAULT));
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}
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static int
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axphy_attach(device_t dev)
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{
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struct mii_softc *sc;
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sc = device_get_softc(dev);
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mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
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&axphy_funcs, 1);
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mii_phy_setmedia(sc);
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return (0);
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}
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static int
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axphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return (0);
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break;
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}
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/* Update the media status. */
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PHY_STATUS(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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axphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (bmsr & BMSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if (bmcr & BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & BMCR_AUTOEN) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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#if 0
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scr = PHY_READ(sc, MII_AXPHY_SCR);
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if (scr & SCR_S100)
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mii->mii_media_active |= IFM_100_TX;
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else
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mii->mii_media_active |= IFM_10_T;
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if (scr & SCR_FDX)
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mii->mii_media_active |=
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IFM_FDX | mii_phy_flowstatus(sc);
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else
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mii->mii_media_active |= IFM_HDX;
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#endif
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} else
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mii->mii_media_active = ife->ifm_media;
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,363 @@
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/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1997, 1998, 1999, 2000-2003
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* Bill Paul <[email protected]>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||||
|
* notice, this list of conditions and the following disclaimer.
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||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
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||||||
|
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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||||||
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for the ASIX Electronics AX88172, AX88178
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* and AX88772 to ethernet controllers.
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*/
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/*
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* Vendor specific commands. ASIX conveniently doesn't document the 'set
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* NODEID' command in their datasheet (thanks a lot guys).
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* To make handling these commands easier, I added some extra data which is
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* decided by the axe_cmd() routine. Commands are encoded in 16 bits, with
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* the format: LDCC. L and D are both nibbles in the high byte. L represents
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* the data length (0 to 15) and D represents the direction (0 for vendor read,
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* 1 for vendor write). CC is the command byte, as specified in the manual.
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*/
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#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
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#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
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#define AXE_CMD_CMD(x) ((x) & 0x00FF)
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#define AXE_172_CMD_READ_RXTX_SRAM 0x2002
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#define AXE_182_CMD_READ_RXTX_SRAM 0x8002
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#define AXE_172_CMD_WRITE_RX_SRAM 0x0103
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#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
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#define AXE_172_CMD_WRITE_TX_SRAM 0x0104
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#define AXE_CMD_MII_OPMODE_SW 0x0106
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#define AXE_CMD_MII_READ_REG 0x2007
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#define AXE_CMD_MII_WRITE_REG 0x2108
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#define AXE_CMD_MII_READ_OPMODE 0x1009
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#define AXE_CMD_MII_OPMODE_HW 0x010A
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#define AXE_CMD_SROM_READ 0x200B
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#define AXE_CMD_SROM_WRITE 0x010C
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#define AXE_CMD_SROM_WR_ENABLE 0x010D
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#define AXE_CMD_SROM_WR_DISABLE 0x010E
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#define AXE_CMD_RXCTL_READ 0x200F
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#define AXE_CMD_RXCTL_WRITE 0x0110
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#define AXE_CMD_READ_IPG012 0x3011
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#define AXE_172_CMD_WRITE_IPG0 0x0112
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#define AXE_178_CMD_WRITE_IPG012 0x0112
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#define AXE_172_CMD_WRITE_IPG1 0x0113
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#define AXE_178_CMD_READ_NODEID 0x6013
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||||||
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#define AXE_172_CMD_WRITE_IPG2 0x0114
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||||||
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#define AXE_178_CMD_WRITE_NODEID 0x6114
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#define AXE_CMD_READ_MCAST 0x8015
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#define AXE_CMD_WRITE_MCAST 0x8116
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#define AXE_172_CMD_READ_NODEID 0x6017
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#define AXE_172_CMD_WRITE_NODEID 0x6118
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#define AXE_CMD_READ_PHYID 0x2019
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#define AXE_172_CMD_READ_MEDIA 0x101A
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#define AXE_178_CMD_READ_MEDIA 0x201A
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#define AXE_CMD_WRITE_MEDIA 0x011B
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#define AXE_CMD_READ_MONITOR_MODE 0x101C
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#define AXE_CMD_WRITE_MONITOR_MODE 0x011D
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||||||
|
#define AXE_CMD_READ_GPIO 0x101E
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|
#define AXE_CMD_WRITE_GPIO 0x011F
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||||||
|
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||||||
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#define AXE_CMD_SW_RESET_REG 0x0120
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||||||
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#define AXE_CMD_SW_PHY_STATUS 0x0021
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||||||
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#define AXE_CMD_SW_PHY_SELECT 0x0122
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||||||
|
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||||||
|
/* AX88772A and AX88772B only. */
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||||||
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#define AXE_CMD_READ_VLAN_CTRL 0x4027
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||||||
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#define AXE_CMD_WRITE_VLAN_CTRL 0x4028
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||||||
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#define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A
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#define AXE_772B_CMD_READ_RXCSUM 0x002B
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||||||
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#define AXE_772B_CMD_WRITE_RXCSUM 0x012C
|
||||||
|
#define AXE_772B_CMD_READ_TXCSUM 0x002D
|
||||||
|
#define AXE_772B_CMD_WRITE_TXCSUM 0x012E
|
||||||
|
|
||||||
|
#define AXE_SW_RESET_CLEAR 0x00
|
||||||
|
#define AXE_SW_RESET_RR 0x01
|
||||||
|
#define AXE_SW_RESET_RT 0x02
|
||||||
|
#define AXE_SW_RESET_PRTE 0x04
|
||||||
|
#define AXE_SW_RESET_PRL 0x08
|
||||||
|
#define AXE_SW_RESET_BZ 0x10
|
||||||
|
#define AXE_SW_RESET_IPRL 0x20
|
||||||
|
#define AXE_SW_RESET_IPPD 0x40
|
||||||
|
|
||||||
|
/* AX88178 documentation says to always write this bit... */
|
||||||
|
#define AXE_178_RESET_MAGIC 0x40
|
||||||
|
|
||||||
|
#define AXE_178_MEDIA_GMII 0x0001
|
||||||
|
#define AXE_MEDIA_FULL_DUPLEX 0x0002
|
||||||
|
#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004
|
||||||
|
|
||||||
|
/* AX88178/88772 documentation says to always write 1 to bit 2 */
|
||||||
|
#define AXE_178_MEDIA_MAGIC 0x0004
|
||||||
|
/* AX88772 documentation says to always write 0 to bit 3 */
|
||||||
|
#define AXE_178_MEDIA_ENCK 0x0008
|
||||||
|
#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010
|
||||||
|
#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010
|
||||||
|
#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020
|
||||||
|
#define AXE_178_MEDIA_JUMBO_EN 0x0040
|
||||||
|
#define AXE_178_MEDIA_LTPF_ONLY 0x0080
|
||||||
|
#define AXE_178_MEDIA_RX_EN 0x0100
|
||||||
|
#define AXE_178_MEDIA_100TX 0x0200
|
||||||
|
#define AXE_178_MEDIA_SBP 0x0800
|
||||||
|
#define AXE_178_MEDIA_SUPERMAC 0x1000
|
||||||
|
|
||||||
|
#define AXE_RXCMD_PROMISC 0x0001
|
||||||
|
#define AXE_RXCMD_ALLMULTI 0x0002
|
||||||
|
#define AXE_172_RXCMD_UNICAST 0x0004
|
||||||
|
#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004
|
||||||
|
#define AXE_RXCMD_BROADCAST 0x0008
|
||||||
|
#define AXE_RXCMD_MULTICAST 0x0010
|
||||||
|
#define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */
|
||||||
|
#define AXE_RXCMD_ENABLE 0x0080
|
||||||
|
#define AXE_178_RXCMD_MFB_MASK 0x0300
|
||||||
|
#define AXE_178_RXCMD_MFB_2048 0x0000
|
||||||
|
#define AXE_178_RXCMD_MFB_4096 0x0100
|
||||||
|
#define AXE_178_RXCMD_MFB_8192 0x0200
|
||||||
|
#define AXE_178_RXCMD_MFB_16384 0x0300
|
||||||
|
#define AXE_772B_RXCMD_HDR_TYPE_0 0x0000
|
||||||
|
#define AXE_772B_RXCMD_HDR_TYPE_1 0x0100
|
||||||
|
#define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200
|
||||||
|
#define AXE_772B_RXCMD_ADD_CHKSUM 0x0400
|
||||||
|
#define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */
|
||||||
|
|
||||||
|
#define AXE_PHY_SEL_PRI 1
|
||||||
|
#define AXE_PHY_SEL_SEC 0
|
||||||
|
#define AXE_PHY_TYPE_MASK 0xE0
|
||||||
|
#define AXE_PHY_TYPE_SHIFT 5
|
||||||
|
#define AXE_PHY_TYPE(x) \
|
||||||
|
(((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT)
|
||||||
|
|
||||||
|
#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */
|
||||||
|
#define PHY_TYPE_GIG 1 /* Gigabit PHY */
|
||||||
|
#define PHY_TYPE_SPECIAL 4 /* Special case */
|
||||||
|
#define PHY_TYPE_RSVD 5 /* Reserved */
|
||||||
|
#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */
|
||||||
|
|
||||||
|
#define AXE_PHY_NO_MASK 0x1F
|
||||||
|
#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK)
|
||||||
|
|
||||||
|
#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */
|
||||||
|
|
||||||
|
#define AXE_GPIO0_EN 0x01
|
||||||
|
#define AXE_GPIO0 0x02
|
||||||
|
#define AXE_GPIO1_EN 0x04
|
||||||
|
#define AXE_GPIO1 0x08
|
||||||
|
#define AXE_GPIO2_EN 0x10
|
||||||
|
#define AXE_GPIO2 0x20
|
||||||
|
#define AXE_GPIO_RELOAD_EEPROM 0x80
|
||||||
|
|
||||||
|
#define AXE_PHY_MODE_MARVELL 0x00
|
||||||
|
#define AXE_PHY_MODE_CICADA 0x01
|
||||||
|
#define AXE_PHY_MODE_AGERE 0x02
|
||||||
|
#define AXE_PHY_MODE_CICADA_V2 0x05
|
||||||
|
#define AXE_PHY_MODE_AGERE_GMII 0x06
|
||||||
|
#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09
|
||||||
|
#define AXE_PHY_MODE_REALTEK_8211CL 0x0C
|
||||||
|
#define AXE_PHY_MODE_REALTEK_8211BN 0x0D
|
||||||
|
#define AXE_PHY_MODE_REALTEK_8251CL 0x0E
|
||||||
|
#define AXE_PHY_MODE_ATTANSIC 0x40
|
||||||
|
|
||||||
|
/* AX88772A/AX88772B only. */
|
||||||
|
#define AXE_SW_PHY_SELECT_EXT 0x0000
|
||||||
|
#define AXE_SW_PHY_SELECT_EMBEDDED 0x0001
|
||||||
|
#define AXE_SW_PHY_SELECT_AUTO 0x0002
|
||||||
|
#define AXE_SW_PHY_SELECT_SS_MII 0x0004
|
||||||
|
#define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008
|
||||||
|
#define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C
|
||||||
|
#define AXE_SW_PHY_SELECT_SS_ENB 0x0010
|
||||||
|
|
||||||
|
/* AX88772A/AX88772B VLAN control. */
|
||||||
|
#define AXE_VLAN_CTRL_ENB 0x00001000
|
||||||
|
#define AXE_VLAN_CTRL_STRIP 0x00002000
|
||||||
|
#define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF
|
||||||
|
#define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000
|
||||||
|
|
||||||
|
#define AXE_RXCSUM_IP 0x0001
|
||||||
|
#define AXE_RXCSUM_IPVE 0x0002
|
||||||
|
#define AXE_RXCSUM_IPV6E 0x0004
|
||||||
|
#define AXE_RXCSUM_TCP 0x0008
|
||||||
|
#define AXE_RXCSUM_UDP 0x0010
|
||||||
|
#define AXE_RXCSUM_ICMP 0x0020
|
||||||
|
#define AXE_RXCSUM_IGMP 0x0040
|
||||||
|
#define AXE_RXCSUM_ICMP6 0x0080
|
||||||
|
#define AXE_RXCSUM_TCPV6 0x0100
|
||||||
|
#define AXE_RXCSUM_UDPV6 0x0200
|
||||||
|
#define AXE_RXCSUM_ICMPV6 0x0400
|
||||||
|
#define AXE_RXCSUM_IGMPV6 0x0800
|
||||||
|
#define AXE_RXCSUM_ICMP6V6 0x1000
|
||||||
|
#define AXE_RXCSUM_FOPC 0x8000
|
||||||
|
|
||||||
|
#define AXE_RXCSUM_64TE 0x0100
|
||||||
|
#define AXE_RXCSUM_PPPOE 0x0200
|
||||||
|
#define AXE_RXCSUM_RPCE 0x8000
|
||||||
|
|
||||||
|
#define AXE_TXCSUM_IP 0x0001
|
||||||
|
#define AXE_TXCSUM_TCP 0x0002
|
||||||
|
#define AXE_TXCSUM_UDP 0x0004
|
||||||
|
#define AXE_TXCSUM_ICMP 0x0008
|
||||||
|
#define AXE_TXCSUM_IGMP 0x0010
|
||||||
|
#define AXE_TXCSUM_ICMP6 0x0020
|
||||||
|
#define AXE_TXCSUM_TCPV6 0x0100
|
||||||
|
#define AXE_TXCSUM_UDPV6 0x0200
|
||||||
|
#define AXE_TXCSUM_ICMPV6 0x0400
|
||||||
|
#define AXE_TXCSUM_IGMPV6 0x0800
|
||||||
|
#define AXE_TXCSUM_ICMP6V6 0x1000
|
||||||
|
|
||||||
|
#define AXE_TXCSUM_64TE 0x0001
|
||||||
|
#define AXE_TXCSUM_PPPOE 0x0002
|
||||||
|
|
||||||
|
#define AXE_BULK_BUF_SIZE 16384 /* bytes */
|
||||||
|
|
||||||
|
#define AXE_CTL_READ 0x01
|
||||||
|
#define AXE_CTL_WRITE 0x02
|
||||||
|
|
||||||
|
#define AXE_CONFIG_IDX 0 /* config number 1 */
|
||||||
|
#define AXE_IFACE_IDX 0
|
||||||
|
|
||||||
|
/* EEPROM Map. */
|
||||||
|
#define AXE_EEPROM_772B_NODE_ID 0x04
|
||||||
|
#define AXE_EEPROM_772B_PHY_PWRCFG 0x18
|
||||||
|
|
||||||
|
struct ax88772b_mfb {
|
||||||
|
int byte_cnt;
|
||||||
|
int threshold;
|
||||||
|
int size;
|
||||||
|
};
|
||||||
|
#define AX88772B_MFB_2K 0
|
||||||
|
#define AX88772B_MFB_4K 1
|
||||||
|
#define AX88772B_MFB_6K 2
|
||||||
|
#define AX88772B_MFB_8K 3
|
||||||
|
#define AX88772B_MFB_16K 4
|
||||||
|
#define AX88772B_MFB_20K 5
|
||||||
|
#define AX88772B_MFB_24K 6
|
||||||
|
#define AX88772B_MFB_32K 7
|
||||||
|
|
||||||
|
struct axe_sframe_hdr {
|
||||||
|
uint16_t len;
|
||||||
|
#define AXE_HDR_LEN_MASK 0xFFFF
|
||||||
|
uint16_t ilen;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
#define AXE_TX_CSUM_PSEUDO_HDR 0x4000
|
||||||
|
#define AXE_TX_CSUM_DIS 0x8000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When RX checksum offloading is enabled, AX88772B uses new RX header
|
||||||
|
* format and it's not compatible with previous RX header format. In
|
||||||
|
* addition, IP header align option should be enabled to get correct
|
||||||
|
* frame size including RX header. Total transferred size including
|
||||||
|
* the RX header is multiple of 4 and controller will pad necessary
|
||||||
|
* bytes if the length is not multiple of 4.
|
||||||
|
* This driver does not enable partial checksum feature which will
|
||||||
|
* compute 16bit checksum from 14th byte to the end of the frame. If
|
||||||
|
* this feature is enabled, computed checksum value is embedded into
|
||||||
|
* RX header which in turn means it uses different RX header format.
|
||||||
|
*/
|
||||||
|
struct axe_csum_hdr {
|
||||||
|
uint16_t len;
|
||||||
|
#define AXE_CSUM_HDR_LEN_MASK 0x07FF
|
||||||
|
#define AXE_CSUM_HDR_CRC_ERR 0x1000
|
||||||
|
#define AXE_CSUM_HDR_MII_ERR 0x2000
|
||||||
|
#define AXE_CSUM_HDR_RUNT 0x4000
|
||||||
|
#define AXE_CSUM_HDR_BMCAST 0x8000
|
||||||
|
uint16_t ilen;
|
||||||
|
uint16_t cstatus;
|
||||||
|
#define AXE_CSUM_HDR_VLAN_MASK 0x0007
|
||||||
|
#define AXE_CSUM_HDR_VLAN_STRIP 0x0008
|
||||||
|
#define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070
|
||||||
|
#define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100
|
||||||
|
#define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400
|
||||||
|
#define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00
|
||||||
|
#define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000
|
||||||
|
#define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000
|
||||||
|
|
||||||
|
#ifdef AXE_APPEND_PARTIAL_CSUM
|
||||||
|
/*
|
||||||
|
* These members present only when partial checksum
|
||||||
|
* offloading is enabled. The checksum value is simple
|
||||||
|
* 16bit sum of received frame starting at offset 14 of
|
||||||
|
* the frame to the end of the frame excluding FCS bytes.
|
||||||
|
*/
|
||||||
|
uint16_t csum_value;
|
||||||
|
uint16_t dummy;
|
||||||
|
#endif
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
#define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK)
|
||||||
|
|
||||||
|
#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
|
||||||
|
|
||||||
|
/* The interrupt endpoint is currently unused by the ASIX part. */
|
||||||
|
enum {
|
||||||
|
AXE_BULK_DT_WR,
|
||||||
|
AXE_BULK_DT_RD,
|
||||||
|
AXE_N_TRANSFER,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct axe_softc {
|
||||||
|
struct usb_ether sc_ue;
|
||||||
|
struct mtx sc_mtx;
|
||||||
|
struct usb_xfer *sc_xfer[AXE_N_TRANSFER];
|
||||||
|
int sc_phyno;
|
||||||
|
|
||||||
|
int sc_flags;
|
||||||
|
#define AXE_FLAG_LINK 0x0001
|
||||||
|
#define AXE_FLAG_STD_FRAME 0x0010
|
||||||
|
#define AXE_FLAG_CSUM_FRAME 0x0020
|
||||||
|
#define AXE_FLAG_772 0x1000 /* AX88772 */
|
||||||
|
#define AXE_FLAG_772A 0x2000 /* AX88772A */
|
||||||
|
#define AXE_FLAG_772B 0x4000 /* AX88772B */
|
||||||
|
#define AXE_FLAG_178 0x8000 /* AX88178 */
|
||||||
|
|
||||||
|
uint8_t sc_ipgs[3];
|
||||||
|
uint8_t sc_phyaddrs[2];
|
||||||
|
uint16_t sc_pwrcfg;
|
||||||
|
uint16_t sc_lenmask;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define AXE_IS_178_FAMILY(sc) \
|
||||||
|
((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \
|
||||||
|
AXE_FLAG_178))
|
||||||
|
|
||||||
|
#define AXE_IS_772(sc) \
|
||||||
|
((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B))
|
||||||
|
|
||||||
|
#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
||||||
|
#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
||||||
|
#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,216 @@
|
|||||||
|
/*-
|
||||||
|
* SPDX-License-Identifier: BSD-2-Clause
|
||||||
|
*
|
||||||
|
* Copyright (c) 2013-2014 Kevin Lo
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AXGE_ACCESS_MAC 0x01
|
||||||
|
#define AXGE_ACCESS_PHY 0x02
|
||||||
|
#define AXGE_ACCESS_WAKEUP 0x03
|
||||||
|
#define AXGE_ACCESS_EEPROM 0x04
|
||||||
|
#define AXGE_ACCESS_EFUSE 0x05
|
||||||
|
#define AXGE_RELOAD_EEPROM_EFUSE 0x06
|
||||||
|
#define AXGE_FW_MODE 0x08
|
||||||
|
#define AXGE_WRITE_EFUSE_EN 0x09
|
||||||
|
#define AXGE_WRITE_EFUSE_DIS 0x0A
|
||||||
|
#define AXGE_ACCESS_MFAB 0x10
|
||||||
|
|
||||||
|
#define AXGE_FW_MODE_178A179 0x0000
|
||||||
|
#define AXGE_FW_MODE_179A 0x0001
|
||||||
|
|
||||||
|
/* Physical link status register */
|
||||||
|
#define AXGE_PLSR 0x02
|
||||||
|
#define PLSR_USB_FS 0x01
|
||||||
|
#define PLSR_USB_HS 0x02
|
||||||
|
#define PLSR_USB_SS 0x04
|
||||||
|
|
||||||
|
/* EEPROM address register */
|
||||||
|
#define AXGE_EAR 0x07
|
||||||
|
|
||||||
|
/* EEPROM data low register */
|
||||||
|
#define AXGE_EDLR 0x08
|
||||||
|
|
||||||
|
/* EEPROM data high register */
|
||||||
|
#define AXGE_EDHR 0x09
|
||||||
|
|
||||||
|
/* EEPROM command register */
|
||||||
|
#define AXGE_ECR 0x0a
|
||||||
|
|
||||||
|
/* Rx control register */
|
||||||
|
#define AXGE_RCR 0x0b
|
||||||
|
#define RCR_STOP 0x0000
|
||||||
|
#define RCR_PROMISC 0x0001
|
||||||
|
#define RCR_ACPT_ALL_MCAST 0x0002
|
||||||
|
#define RCR_AUTOPAD_BNDRY 0x0004
|
||||||
|
#define RCR_ACPT_BCAST 0x0008
|
||||||
|
#define RCR_ACPT_MCAST 0x0010
|
||||||
|
#define RCR_ACPT_PHY_MCAST 0x0020
|
||||||
|
#define RCR_START 0x0080
|
||||||
|
#define RCR_DROP_CRCERR 0x0100
|
||||||
|
#define RCR_IPE 0x0200
|
||||||
|
#define RCR_TX_CRC_PAD 0x0400
|
||||||
|
|
||||||
|
/* Node id register */
|
||||||
|
#define AXGE_NIDR 0x10
|
||||||
|
|
||||||
|
/* Multicast filter array */
|
||||||
|
#define AXGE_MFA 0x16
|
||||||
|
|
||||||
|
/* Medium status register */
|
||||||
|
#define AXGE_MSR 0x22
|
||||||
|
#define MSR_GM 0x0001
|
||||||
|
#define MSR_FD 0x0002
|
||||||
|
#define MSR_EN_125MHZ 0x0008
|
||||||
|
#define MSR_RFC 0x0010
|
||||||
|
#define MSR_TFC 0x0020
|
||||||
|
#define MSR_RE 0x0100
|
||||||
|
#define MSR_PS 0x0200
|
||||||
|
|
||||||
|
/* Monitor mode status register */
|
||||||
|
#define AXGE_MMSR 0x24
|
||||||
|
#define MMSR_RWLC 0x02
|
||||||
|
#define MMSR_RWMP 0x04
|
||||||
|
#define MMSR_RWWF 0x08
|
||||||
|
#define MMSR_RW_FLAG 0x10
|
||||||
|
#define MMSR_PME_POL 0x20
|
||||||
|
#define MMSR_PME_TYPE 0x40
|
||||||
|
#define MMSR_PME_IND 0x80
|
||||||
|
|
||||||
|
/* GPIO control/status register */
|
||||||
|
#define AXGE_GPIOCR 0x25
|
||||||
|
|
||||||
|
/* Ethernet PHY power & reset control register */
|
||||||
|
#define AXGE_EPPRCR 0x26
|
||||||
|
#define EPPRCR_BZ 0x0010
|
||||||
|
#define EPPRCR_IPRL 0x0020
|
||||||
|
#define EPPRCR_AUTODETACH 0x1000
|
||||||
|
|
||||||
|
#define AXGE_RX_BULKIN_QCTRL 0x2e
|
||||||
|
|
||||||
|
#define AXGE_CLK_SELECT 0x33
|
||||||
|
#define AXGE_CLK_SELECT_BCS 0x01
|
||||||
|
#define AXGE_CLK_SELECT_ACS 0x02
|
||||||
|
#define AXGE_CLK_SELECT_ACSREQ 0x10
|
||||||
|
#define AXGE_CLK_SELECT_ULR 0x08
|
||||||
|
|
||||||
|
/* COE Rx control register */
|
||||||
|
#define AXGE_CRCR 0x34
|
||||||
|
#define CRCR_IP 0x01
|
||||||
|
#define CRCR_TCP 0x02
|
||||||
|
#define CRCR_UDP 0x04
|
||||||
|
#define CRCR_ICMP 0x08
|
||||||
|
#define CRCR_IGMP 0x10
|
||||||
|
#define CRCR_TCPV6 0x20
|
||||||
|
#define CRCR_UDPV6 0x40
|
||||||
|
#define CRCR_ICMPV6 0x80
|
||||||
|
|
||||||
|
/* COE Tx control register */
|
||||||
|
#define AXGE_CTCR 0x35
|
||||||
|
#define CTCR_IP 0x01
|
||||||
|
#define CTCR_TCP 0x02
|
||||||
|
#define CTCR_UDP 0x04
|
||||||
|
#define CTCR_ICMP 0x08
|
||||||
|
#define CTCR_IGMP 0x10
|
||||||
|
#define CTCR_TCPV6 0x20
|
||||||
|
#define CTCR_UDPV6 0x40
|
||||||
|
#define CTCR_ICMPV6 0x80
|
||||||
|
|
||||||
|
/* Pause water level high register */
|
||||||
|
#define AXGE_PWLHR 0x54
|
||||||
|
|
||||||
|
/* Pause water level low register */
|
||||||
|
#define AXGE_PWLLR 0x55
|
||||||
|
|
||||||
|
#define AXGE_CONFIG_IDX 0 /* config number 1 */
|
||||||
|
#define AXGE_IFACE_IDX 0
|
||||||
|
|
||||||
|
#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
|
||||||
|
|
||||||
|
/* The interrupt endpoint is currently unused by the ASIX part. */
|
||||||
|
enum {
|
||||||
|
AXGE_BULK_DT_WR,
|
||||||
|
AXGE_BULK_DT_RD,
|
||||||
|
AXGE_N_TRANSFER,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define AXGE_N_FRAMES 16
|
||||||
|
|
||||||
|
struct axge_frame_txhdr {
|
||||||
|
uint32_t len;
|
||||||
|
#define AXGE_TXLEN_MASK 0x0001FFFF
|
||||||
|
#define AXGE_VLAN_INSERT 0x20000000
|
||||||
|
#define AXGE_CSUM_DISABLE 0x80000000
|
||||||
|
uint32_t mss;
|
||||||
|
#define AXGE_MSS_MASK 0x00003FFF
|
||||||
|
#define AXGE_PADDING 0x80008000
|
||||||
|
#define AXGE_VLAN_TAG_MASK 0xFFFF0000
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
#define AXGE_TXBYTES(x) ((x) & AXGE_TXLEN_MASK)
|
||||||
|
|
||||||
|
#define AXGE_PHY_ADDR 3
|
||||||
|
|
||||||
|
struct axge_frame_rxhdr {
|
||||||
|
uint32_t status;
|
||||||
|
#define AXGE_RX_L4_CSUM_ERR 0x00000001
|
||||||
|
#define AXGE_RX_L3_CSUM_ERR 0x00000002
|
||||||
|
#define AXGE_RX_L4_TYPE_UDP 0x00000004
|
||||||
|
#define AXGE_RX_L4_TYPE_ICMP 0x00000008
|
||||||
|
#define AXGE_RX_L4_TYPE_IGMP 0x0000000C
|
||||||
|
#define AXGE_RX_L4_TYPE_TCP 0x00000010
|
||||||
|
#define AXGE_RX_L4_TYPE_MASK 0x0000001C
|
||||||
|
#define AXGE_RX_L3_TYPE_IPV4 0x00000020
|
||||||
|
#define AXGE_RX_L3_TYPE_IPV6 0x00000040
|
||||||
|
#define AXGE_RX_L3_TYPE_MASK 0x00000060
|
||||||
|
#define AXGE_RX_VLAN_IND_MASK 0x00000700
|
||||||
|
#define AXGE_RX_GOOD_PKT 0x00000800
|
||||||
|
#define AXGE_RX_VLAN_PRI_MASK 0x00007000
|
||||||
|
#define AXGE_RX_MBCAST 0x00008000
|
||||||
|
#define AXGE_RX_LEN_MASK 0x1FFF0000
|
||||||
|
#define AXGE_RX_CRC_ERR 0x20000000
|
||||||
|
#define AXGE_RX_MII_ERR 0x40000000
|
||||||
|
#define AXGE_RX_DROP_PKT 0x80000000
|
||||||
|
#define AXGE_RX_LEN_SHIFT 16
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
#define AXGE_RXBYTES(x) (((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT)
|
||||||
|
#define AXGE_RX_ERR(x) \
|
||||||
|
((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT))
|
||||||
|
|
||||||
|
struct axge_softc {
|
||||||
|
struct usb_ether sc_ue;
|
||||||
|
struct mtx sc_mtx;
|
||||||
|
struct usb_xfer *sc_xfer[AXGE_N_TRANSFER];
|
||||||
|
|
||||||
|
int sc_flags;
|
||||||
|
#define AXGE_FLAG_LINK 0x0001 /* got a link */
|
||||||
|
#define AXGE_FLAG_178A 0x1000 /* AX88178A */
|
||||||
|
#define AXGE_FLAG_179 0x2000 /* AX88179 */
|
||||||
|
#define AXGE_FLAG_179A 0x4000 /* AX88179A */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
||||||
|
#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
||||||
|
#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
|
||||||
@@ -0,0 +1,44 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2025, Haiku, Inc. All rights reserved.
|
||||||
|
* Distributed under the terms of the MIT license.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <sys/bus.h>
|
||||||
|
|
||||||
|
|
||||||
|
extern driver_t* DRIVER_MODULE_NAME(axe, uhub);
|
||||||
|
extern driver_t* DRIVER_MODULE_NAME(axge, uhub);
|
||||||
|
|
||||||
|
extern driver_t *DRIVER_MODULE_NAME(axphy, miibus);
|
||||||
|
extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
|
||||||
|
|
||||||
|
HAIKU_FBSD_DRIVERS_GLUE(asix88xxx)
|
||||||
|
HAIKU_DRIVER_REQUIREMENTS(0);
|
||||||
|
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
|
||||||
|
NO_HAIKU_REENABLE_INTERRUPTS();
|
||||||
|
|
||||||
|
|
||||||
|
driver_t *
|
||||||
|
__haiku_select_miibus_driver(device_t dev)
|
||||||
|
{
|
||||||
|
driver_t *drivers[] = {
|
||||||
|
DRIVER_MODULE_NAME(axphy, miibus),
|
||||||
|
DRIVER_MODULE_NAME(ukphy, miibus),
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
|
return __haiku_probe_drivers(dev, drivers);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void
|
||||||
|
__haiku_init_hardware()
|
||||||
|
{
|
||||||
|
driver_t *usb_drivers[] = {
|
||||||
|
DRIVER_MODULE_NAME(axe, uhub),
|
||||||
|
DRIVER_MODULE_NAME(axge, uhub),
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
_fbsd_init_hardware_uhub(usb_drivers);
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user