ARM: Initial implementation of interrupt/exception handling.
This contains both the common ARM(v5) vector handling as well as the PXA(verdex) specific interrupt controller code, to be seperated when ARM support for FDT is implemented. Functional enough to handle interrupts, needs work on KDL support.
This commit is contained in:
Ithamar R. Adema
@@ -17,7 +17,7 @@ KernelMergeObject kernel_arch_arm.o :
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arch_debug_console.cpp
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arch_debug.cpp
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arch_elf.cpp
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# arch_exceptions.S
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arch_exceptions.S
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arch_int.cpp
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arch_platform.cpp
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arch_real_time_clock.cpp
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@@ -0,0 +1,176 @@
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/*
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* Copyright 2012, Haiku Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Ithamar R. Adema <ithamar@upgrade-android.com>
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*
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*/
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#include <asm_defs.h>
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.text
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.globl _vectors_start
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_vectors_start:
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ldr pc, _arm_reset
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ldr pc, _arm_undefined
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ldr pc, _arm_syscall
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ldr pc, _arm_prefetch_abort
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ldr pc, _arm_data_abort
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ldr pc, _arm_reserved
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ldr pc, _arm_irq
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ldr pc, _arm_fiq
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_arm_reset:
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.word arm_reserved // actually reset, but not used when mapped
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_arm_undefined:
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.word arm_undefined
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_arm_syscall:
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.word arm_syscall
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_arm_prefetch_abort:
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.word arm_prefetch_abort
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_arm_data_abort:
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.word arm_data_abort
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_arm_reserved:
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.word arm_reserved
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_arm_irq:
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.word arm_irq
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_arm_fiq:
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.word arm_fiq
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.globl _vectors_end
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_vectors_end:
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.rept 64
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.word 0xaabbccdd
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.endr
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abort_stack:
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.word .
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FUNCTION(arm_undefined):
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stmfd sp!, { r0-r12, r14 }
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sub sp, sp, #12
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mov r0, sp
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mrs r1, spsr
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stmia r0, { r1, r13-r14 }
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b arch_arm_undefined
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b .
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FUNCTION(arm_syscall):
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stmfd sp!, { r0-r12, r14 }
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sub sp, sp, #12
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mov r0, sp
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mrs r1, spsr
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stmia r0, { r1, r13-r14 }
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b arch_arm_syscall
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b .
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FUNCTION(arm_prefetch_abort):
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ldr sp, abort_stack
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stmfd sp!, { r0-r12, r14 }
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sub sp, sp, #12
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mov r0, sp
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mrs r1, spsr
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stmia r0, { r1, r13-r14 }
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b arch_arm_prefetch_abort
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b .
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FUNCTION(arm_data_abort):
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ldr sp, abort_stack
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/* XXX only deals with interrupting supervisor mode */
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/* save r4-r6 and use as a temporary place to save while we switch into supervisor mode */
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stmia r13, { r4-r6 }
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mov r4, r13
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sub r5, lr, #8
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mrs r6, spsr
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/* move into supervisor mode. irq/fiq disabled */
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msr cpsr_c, #0x13
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/* save the return address */
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stmfd sp!, { r5 }
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/* save C trashed regs, supervisor lr */
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stmfd sp!, { r0-r3, r12, lr }
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/* save spsr */
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stmfd sp!, { r6 }
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/* restore r4-r6 */
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ldmia r4, { r4-r6 }
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/* call into higher level code */
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mrc p15, 0, r2, c5, c0, 0 @ get FSR
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mrc p15, 0, r3, c6, c0, 0 @ get FAR
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sub sp, sp, #20
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mov r0, sp /* iframe */
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stmia r0, { r6,r2,r3,r4,r5 }
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bl arch_arm_data_abort
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add sp, sp, #20
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/* restore spsr */
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ldmfd sp!, { r0 }
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msr spsr_cxsf, r0
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/* restore back to where we came from */
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ldmfd sp!, { r0-r3, r12, lr, pc }^
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FUNCTION(arm_reserved):
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b .
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FUNCTION(arm_irq):
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ldr sp, abort_stack
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/* XXX only deals with interrupting supervisor mode */
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/* save r4-r6 and use as a temporary place to save while we switch into supervisor mode */
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stmia r13, { r4-r6 }
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mov r4, r13
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sub r5, lr, #4
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mrs r6, spsr
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/* move into supervisor mode. irq/fiq disabled */
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msr cpsr_c, #(3<<6 | 0x13)
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/* save the return address */
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stmfd sp!, { r5 }
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/* save C trashed regs, supervisor lr */
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stmfd sp!, { r0-r3, r12, lr }
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/* save spsr */
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stmfd sp!, { r6 }
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/* restore r4-r6 */
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ldmia r4, { r4-r6 }
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/* call into higher level code */
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mov r0, sp /* iframe */
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bl arch_arm_irq
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/* restore spsr */
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ldmfd sp!, { r0 }
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msr spsr_cxsf, r0
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/* restore back to where we came from */
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ldmfd sp!, { r0-r3, r12, lr, pc }^
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.bss
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.align 2
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.global irq_save_spot
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irq_save_spot:
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.word 0 /* r4 */
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.word 0 /* r5 */
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.word 0 /* r6 */
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.text
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FUNCTION(arm_fiq):
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ldr sp, abort_stack
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sub lr, lr, #4
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stmfd sp!, { r0-r3, r12, lr }
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bl arch_arm_fiq
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ldmfd sp!, { r0-r3, r12, pc }^
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@@ -1,11 +1,12 @@
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/*
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* Copyright 2003-2010, Haiku Inc. All rights reserved.
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* Copyright 2003-2012, Haiku Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler <[email protected]>
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* Ingo Weinhold <[email protected]>
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* François Revol <[email protected]>
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* Ithamar R. Adema <[email protected]>
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*
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* Copyright 2001, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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@@ -30,27 +31,35 @@
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#include <string.h>
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//#define TRACE_ARCH_INT
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#define TRACE_ARCH_INT
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#ifdef TRACE_ARCH_INT
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# define TRACE(x) dprintf x
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#else
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# define TRACE(x) ;
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#endif
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/*typedef void (*m68k_exception_handler)(void);
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#define M68K_EXCEPTION_VECTOR_COUNT 256
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#warning M68K: align on 4 ?
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//m68k_exception_handler gExceptionVectors[M68K_EXCEPTION_VECTOR_COUNT];
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m68k_exception_handler *gExceptionVectors;
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#define VECTORPAGE_SIZE 64
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#define USER_VECTOR_ADDR_LOW 0x00000000
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#define USER_VECTOR_ADDR_HIGH 0xffff0000
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// defined in arch_exceptions.S
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extern "C" void __m68k_exception_noop(void);
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extern "C" void __m68k_exception_common(void);
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*/
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extern int __irqvec_start;
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extern int __irqvec_end;
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#define PXA_INTERRUPT_PHYS_BASE 0x40D00000
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#define PXA_INTERRUPT_SIZE 0x00000034
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//extern"C" void m68k_exception_tail(void);
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#define PXA_ICIP 0x00
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#define PXA_ICMR 0x01
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#define PXA_ICFP 0x03
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#define PXA_ICMR2 0x28
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static area_id sPxaInterruptArea;
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static uint32 *sPxaInterruptBase;
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extern int _vectors_start;
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extern int _vectors_end;
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static area_id sVectorPageArea;
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static void *sVectorPageAddress;
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static area_id sUserVectorPageArea;
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static void *sUserVectorPageAddress;
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// current fault handler
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addr_t gFaultHandler;
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@@ -59,35 +68,48 @@ addr_t gFaultHandler;
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// threads yet.
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struct iframe_stack gBootFrameStack;
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// interrupt controller interface (initialized
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// in arch_int_init_post_device_manager())
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//static struct interrupt_controller_module_info *sPIC;
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//static void *sPICCookie;
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uint32
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mmu_read_c1()
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{
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uint32 controlReg = 0;
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asm volatile("MRC p15, 0, %[c1out], c1, c0, 0":[c1out] "=r" (controlReg));
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return controlReg;
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}
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void
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mmu_write_c1(uint32 value)
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{
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asm volatile("MCR p15, 0, %[c1in], c1, c0, 0"::[c1in] "r" (value));
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}
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void
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arch_int_enable_io_interrupt(int irq)
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{
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#warning ARM WRITEME
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//if (!sPIC)
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// return;
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TRACE(("arch_int_enable_io_interrupt(%d)\n", irq));
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// TODO: I have no idea, what IRQ type is appropriate.
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//sPIC->enable_io_interrupt(sPICCookie, irq, IRQ_TYPE_LEVEL);
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// M68KPlatform::Default()->EnableIOInterrupt(irq);
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if (irq <= 31) {
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sPxaInterruptBase[PXA_ICMR] |= 1 << irq;
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return;
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}
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sPxaInterruptBase[PXA_ICMR2] |= 1 << (irq - 32);
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}
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void
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arch_int_disable_io_interrupt(int irq)
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{
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#warning ARM WRITEME
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TRACE(("arch_int_disable_io_interrupt(%d)\n", irq));
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//if (!sPIC)
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// return;
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if (irq <= 31) {
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sPxaInterruptBase[PXA_ICMR] &= ~(1 << irq);
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return;
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}
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//sPIC->disable_io_interrupt(sPICCookie, irq);
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// M68KPlatform::Default()->DisableIOInterrupt(irq);
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sPxaInterruptBase[PXA_ICMR2] &= ~(1 << (irq - 32));
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}
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@@ -97,60 +119,67 @@ arch_int_disable_io_interrupt(int irq)
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static void
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print_iframe(struct iframe *frame)
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{
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#if 0
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dprintf("r0-r3: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r0, frame->r1,
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frame->r2, frame->r3);
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dprintf("r4-r7: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r4, frame->r5,
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frame->r6, frame->r7);
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dprintf("r8-r11: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r8, frame->r9,
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frame->r10, frame->r11);
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dprintf("r12-r15: 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", frame->r12, frame->r13,
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frame->a6, frame->a7);
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dprintf(" pc 0x%08lx sr 0x%08lx\n", frame->pc, frame->sr);
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#endif
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#warning ARM WRITEME
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}
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status_t
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arch_int_init(kernel_args *args)
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{
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#if 0
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status_t err;
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addr_t vbr;
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int i;
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// see if high vectors are enabled
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if (mmu_read_c1() & (1<<13))
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dprintf("High vectors already enabled\n");
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else {
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mmu_write_c1(mmu_read_c1() | (1<<13));
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gExceptionVectors = (m68k_exception_handler *)args->arch_args.vir_vbr;
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if (!(mmu_read_c1() & (1<<13)))
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dprintf("Unable to enable high vectors!\n");
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else
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dprintf("Enabled high vectors\n");
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}
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/* fill in the vector table */
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for (i = 0; i < M68K_EXCEPTION_VECTOR_COUNT; i++)
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gExceptionVectors[i] = &__m68k_exception_common;
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return B_OK;
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}
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vbr = args->arch_args.phys_vbr;
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/* point VBR to the new table */
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asm volatile ("movec %0,%%vbr" : : "r"(vbr):);
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#endif
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#warning ARM WRITEME
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status_t
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arch_int_init_post_vm(kernel_args *args)
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{
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// create a read/write kernel area
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sVectorPageArea = create_area("vectorpage", (void **)&sVectorPageAddress,
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B_ANY_ADDRESS, VECTORPAGE_SIZE, B_FULL_LOCK,
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B_KERNEL_WRITE_AREA | B_KERNEL_READ_AREA);
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if (sVectorPageArea < 0)
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panic("vector page could not be created!");
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// clone it at a fixed address with user read/only permissions
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sUserVectorPageAddress = (addr_t*)USER_VECTOR_ADDR_HIGH;
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sUserVectorPageArea = clone_area("user_vectorpage",
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(void **)&sUserVectorPageAddress, B_EXACT_ADDRESS,
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B_READ_AREA | B_EXECUTE_AREA, sVectorPageArea);
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if (sUserVectorPageArea < 0)
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panic("user vector page @ %p could not be created (%lx)!", sVectorPageAddress, sUserVectorPageArea);
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// copy vectors into the newly created area
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memcpy(sVectorPageAddress, &_vectors_start, VECTORPAGE_SIZE);
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sPxaInterruptArea = map_physical_memory("pxa_intc", PXA_INTERRUPT_PHYS_BASE,
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PXA_INTERRUPT_SIZE, 0, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&sPxaInterruptBase);
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if (sPxaInterruptArea < 0)
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return sPxaInterruptArea;
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sPxaInterruptBase[PXA_ICMR] = 0;
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sPxaInterruptBase[PXA_ICMR2] = 0;
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return B_OK;
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}
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status_t
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arch_int_init_post_vm(kernel_args *args)
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{
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status_t err;
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// err = M68KPlatform::Default()->InitPIC(args);
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#warning ARM WRITEME
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return err;
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}
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status_t
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arch_int_init_io(kernel_args* args)
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{
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TRACE(("arch_int_init_io(%p)\n", args));
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return B_OK;
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}
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@@ -158,8 +187,53 @@ arch_int_init_io(kernel_args* args)
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status_t
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arch_int_init_post_device_manager(struct kernel_args *args)
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{
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// no PIC found
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panic("arch_int_init_post_device_manager(): Found no supported PIC!");
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return B_ENTRY_NOT_FOUND;
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}
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extern "C" void arch_arm_undefined(struct iframe *iframe)
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{
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panic("Undefined instruction!");
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}
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extern "C" void arch_arm_syscall(struct iframe *iframe)
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{
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panic("Software interrupt!\n");
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}
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extern "C" void arch_arm_data_abort(struct iframe *iframe)
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{
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addr_t newip;
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status_t res = vm_page_fault(iframe->r2 /* FAR */, iframe->r4 /* lr */,
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true /* TODO how to determine read/write? */,
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false /* only kernelspace for now */,
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&newip);
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if (res != B_HANDLED_INTERRUPT) {
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panic("Data Abort: %08x %08x %08x %08x (res=%lx)", iframe->r0 /* spsr */,
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iframe->r1 /* FSR */, iframe->r2 /* FAR */,
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iframe->r4 /* lr */,
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res);
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} else {
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//panic("vm_page_fault was ok (%08lx/%08lx)!", iframe->r2 /* FAR */, iframe->r0 /* spsr */);
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}
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}
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extern "C" void arch_arm_prefetch_abort(struct iframe *iframe)
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{
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panic("Prefetch Abort: %08x %08x %08x", iframe->r0, iframe->r1, iframe->r2);
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}
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extern "C" void arch_arm_irq(struct iframe *iframe)
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{
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for (int i=0; i < 32; i++)
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if (sPxaInterruptBase[PXA_ICIP] & (1 << i))
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int_io_interrupt_handler(i, true);
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}
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extern "C" void arch_arm_fiq(struct iframe *iframe)
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{
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for (int i=0; i < 32; i++)
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if (sPxaInterruptBase[PXA_ICIP] & (1 << i))
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dprintf("arch_arm_fiq: help me, FIQ %d was triggered but no FIQ support!\n", i);
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}
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