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openBeOS_Neomagic_V0.03_src

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5513 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
2003-12-01 05:52:52 +00:00
parent 091b52d5b2
commit 0252982ab0
6 changed files with 1459 additions and 0 deletions
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headers/private/graphics/neomagic/DriverInterface.h
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/*
Copyright 1999, Be Incorporated. All Rights Reserved.
This file may be used under the terms of the Be Sample Code License.
Other authors:
Rudolf Cornelissen 4/2003-
*/
#ifndef DRIVERINTERFACE_H
#define DRIVERINTERFACE_H
#include <Accelerant.h>
#include "video_overlay.h"
#include <Drivers.h>
#include <PCI.h>
#include <OS.h>
#define DRIVER_PREFIX "nm" // apsed
/*
Internal driver state (also for sharing info between driver and accelerant)
*/
#if defined(__cplusplus)
extern "C" {
#endif
typedef struct {
sem_id sem;
int32 ben;
} benaphore;
#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0;
#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
#define DELETE_BEN(x) delete_sem(x.sem);
#define MN_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
/*dualhead extensions to flags*/
#define DUALHEAD_OFF (0<<6)
#define DUALHEAD_CLONE (1<<6)
#define DUALHEAD_ON (2<<6)
#define DUALHEAD_SWITCH (3<<6)
#define DUALHEAD_BITS (3<<6)
#define DUALHEAD_CAPABLE (1<<8)
#define TV_BITS (3<<9)
#define TV_MON (0<<9
#define TV_PAL (1<<9)
#define TV_NTSC (2<<9)
#define TV_CAPABLE (1<<11)
#define SKD_MOVE_CURSOR 0x00000001
#define SKD_PROGRAM_CLUT 0x00000002
#define SKD_SET_START_ADDR 0x00000004
#define SKD_SET_CURSOR 0x00000008
#define SKD_HANDLER_INSTALLED 0x80000000
enum {
MN_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
MN_GET_PCI,
MN_SET_PCI,
MN_DEVICE_NAME,
MN_RUN_INTERRUPTS,
MN_ISA_OUT,
MN_ISA_IN
};
/* max. number of overlay buffers */
#define MAXBUFFERS 3
/* max. pixelclock speed the BES supports */
#define BESMAXSPEED 135000
/* internal used info on overlay buffers */
typedef struct
{
uint16 slopspace;
uint32 size;
} int_buf_info;
typedef struct settings { // apsed, see comments in nm.settings
// for driver
char accelerant[B_FILE_NAME_LENGTH];
bool dumprom;
// for accelerant
uint32 logmask;
uint32 memory;
bool usebios;
bool hardcursor;
} settings;
/*shared info*/
typedef struct {
/*a few ID things*/
uint16 vendor_id; /* PCI vendor ID, from pci_info */
uint16 device_id; /* PCI device ID, from pci_info */
uint8 revision; /* PCI device revsion, from pci_info */
/* bug workaround for 4.5.0 */
uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
uint32 * clone_bugfix_regs;
uint32 * clone_bugfix_regs2;
/*memory mappings*/
area_id regs_area, regs2_area; /* Kernel's area_id for the memory mapped registers.
It will be cloned into the accelerant's address
space. */
area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */
area_id dma_buffer_area; /* Area assigned for dma*/
void *framebuffer; /* As viewed from virtual memory */
void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
void *pseudo_dma; /* As viewed from virtual memory */
void *dma_buffer; /* buffer for dma*/
void *dma_buffer_pci; /* buffer for dma - from PCI bus*/
/*screenmode list*/
area_id mode_area; /* Contains the list of display modes the driver supports */
uint32 mode_count; /* Number of display modes in the list */
/*flags - used by driver*/
uint32 flags;
/*vblank semaphore*/
sem_id vblank; /* The vertical blank semaphore. Ownership will be
transfered to the team opening the device first */
/*cursor information*/
struct {
uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
uint16 hot_y; /* is 0,0 */
uint16 x; /* The location of the cursor hot spot on the */
uint16 y; /* desktop */
uint16 width; /* Width and height of the cursor shape (always 16!) */
uint16 height;
bool is_visible; /* Is the cursor currently displayed? */
} cursor;
/*colour lookup table*/
uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
/*more display mode stuff*/
display_mode dm; /* current display mode configuration: head1 */
bool acc_mode; /* signals (non)accelerated mode */
/*frame buffer config - for BDirectScreen*/
frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
/*acceleration engine*/
struct {
uint32 count; /* last dwgsync slot used */
uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
benaphore lock; /* for serializing access to the acceleration engine */
} engine;
/* card info - information gathered from PINS (and other sources) */
enum
{ // card_type in order of date of nm chip design
NM2070 = 0,
NM2090,
NM2093,
NM2097,
NM2160,
NM2200,
NM2230,
NM2360,
NM2380,
G100,
G200
};
struct
{
/* specialised registers for predefined cardspecs */
/* general card information */
uint32 card_type; /* see card_type enum above */
/* PINS */
float f_ref; /* PLL reference-oscillator frequency (Mhz) */
uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
uint32 min_system_vco;
uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
uint32 min_pixel_vco;
uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
uint32 max_dac1_clock; /* dac1 limits (Mhz) */
uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
uint32 max_dac1_clock_16;
uint32 max_dac1_clock_24;
uint32 memory_size; /* memory (Kbytes) */
uint32 curmem_size; /* memory (bytes) */
uint16 max_crtc_width; /* CRTC max constraints */
uint16 max_crtc_height;
uint8 panel_type; /* panel type */
uint16 panel_width; /* panel size */
uint16 panel_height;
uint8 outputs; /* in BIOS preselected output(s) */
} ps;
/*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/
uint8 rom_mirror[32768];
/* apsed: some configuration settings from ~/config/settings/kernel/drivers/nm.settings if exists */
settings settings;
struct
{
overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
overlay_token myToken; /* scaler is free/in use */
benaphore lock; /* for creating buffers and aquiring overlay unit routines */
} overlay;
} shared_info;
/* Read or write a value in PCI configuration space */
typedef struct {
uint32 magic; /* magic number to make sure the caller groks us */
uint32 offset; /* Offset to read/write */
uint32 size; /* Number of bytes to transfer */
uint32 value; /* The value read or written */
} mn_get_set_pci;
/* Read or write a value in ISA I/O space */
typedef struct {
uint32 magic; /* magic number to make sure the caller groks us */
uint16 adress; /* Offset to read/write */
uint8 size; /* Number of bytes to transfer */
uint16 data; /* The value read or written */
} mn_in_out_isa;
/* Set some boolean condition (like enabling or disabling interrupts) */
typedef struct {
uint32 magic; /* magic number to make sure the caller groks us */
bool do_it; /* state to set */
} mn_set_bool_state;
/* Retrieve the area_id of the kernel/accelerant shared info */
typedef struct {
uint32 magic; /* magic number to make sure the caller groks us */
area_id shared_info_area; /* area_id containing the shared information */
} mn_get_private_data;
/* Retrieve the device name. Usefull for when we have a file handle, but want
to know the device name (like when we are cloning the accelerant) */
typedef struct {
uint32 magic; /* magic number to make sure the caller groks us */
char *name; /* The name of the device, less the /dev root */
} mn_device_name;
enum {
_WAIT_FOR_VBLANK = (1 << 0)
};
#if defined(__cplusplus)
}
#endif
#endif
headers/private/graphics/neomagic/nm_macros.h
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/* NM registers definitions and macros for access to */
/* PCI_config_space */
#define NMCFG_DEVID 0x00
#define NMCFG_DEVCTRL 0x04
#define NMCFG_CLASS 0x08
#define NMCFG_HEADER 0x0c
#define NMCFG_NMBASE2 0x10
#define NMCFG_NMBASE1 0x14
#define NMCFG_NMBASE3 0x18 // >= MYST
#define NMCFG_SUBSYSIDR 0x2c // >= MYST
#define NMCFG_ROMBASE 0x30
#define NMCFG_CAP_PTR 0x34 // >= MIL2
#define NMCFG_INTCTRL 0x3c
#define NMCFG_OPTION 0x40
#define NMCFG_NM_INDEX 0x44
#define NMCFG_NM_DATA 0x48
#define NMCFG_SUBSYSIDW 0x4c // >= MYST
#define NMCFG_OPTION2 0x50 // >= G100
#define NMCFG_OPTION3 0x54 // >= G400
#define NMCFG_OPTION4 0x58 // >= G450
#define NMCFG_PM_IDENT 0xdc // >= G100
#define NMCFG_PM_CSR 0xe0 // >= G100
#define NMCFG_AGP_IDENT 0xf0 // >= MIL2
#define NMCFG_AGP_STS 0xf4 // >= MIL2
#define NMCFG_AGP_CMD 0xf8 // >= MIL2
//new:
/* neomagic ISA direct registers */
/* VGA standard registers: */
#define NMISA8_ATTRINDW 0x03c0
#define NMISA8_ATTRINDR 0x03c1
#define NMISA8_ATTRDATW 0x03c0
#define NMISA8_ATTRDATR 0x03c1
#define NMISA8_SEQIND 0x03c4
#define NMISA8_SEQDAT 0x03c5
#define NMISA16_SEQIND 0x03c4
#define NMISA8_CRTCIND 0x03d4
#define NMISA8_CRTCDAT 0x03d5
#define NMISA16_CRTCIND 0x03d4
#define NMISA8_GRPHIND 0x03ce
#define NMISA8_GRPHDAT 0x03cf
#define NMISA16_GRPHIND 0x03ce
/* neomagic ISA GENERAL direct registers */
/* VGA standard registers: */
#define NMISA8_MISCW 0x03c2
#define NMISA8_MISCR 0x03cc
#define NMISA8_INSTAT1 0x03da
/* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */
/* VGA standard registers: */
#define NMISA8_PALMASK 0x03c6
#define NMISA8_PALINDR 0x03c7
#define NMISA8_PALINDW 0x03c8
#define NMISA8_PALDATA 0x03c9
/* neomagic ISA CRTC indexed registers */
/* VGA standard registers: */
#define NMCRTCX_HTOTAL 0x00
#define NMCRTCX_HDISPE 0x01
#define NMCRTCX_HBLANKS 0x02
#define NMCRTCX_HBLANKE 0x03
#define NMCRTCX_HSYNCS 0x04
#define NMCRTCX_HSYNCE 0x05
#define NMCRTCX_VTOTAL 0x06
#define NMCRTCX_OVERFLOW 0x07
#define NMCRTCX_PRROWSCN 0x08
#define NMCRTCX_MAXSCLIN 0x09
#define NMCRTCX_VGACURCTRL 0x0a
#define NMCRTCX_FBSTADDH 0x0c
#define NMCRTCX_FBSTADDL 0x0d
#define NMCRTCX_VSYNCS 0x10
#define NMCRTCX_VSYNCE 0x11
#define NMCRTCX_VDISPE 0x12
#define NMCRTCX_PITCHL 0x13
#define NMCRTCX_VBLANKS 0x15
#define NMCRTCX_VBLANKE 0x16
#define NMCRTCX_MODECTL 0x17
#define NMCRTCX_LINECOMP 0x18
/* NeoMagic specific registers: */
#define NMCRTCX_VEXT 0x70 /* >= NM2200 */
/* neomagic ISA SEQUENCER indexed registers */
/* VGA standard registers: */
#define NMSEQX_RESET 0x00
#define NMSEQX_CLKMODE 0x01
#define NMSEQX_MEMMODE 0x04
/* neomagic ISA ATTRIBUTE indexed registers */
/* VGA standard registers: */
#define NMATBX_MODECTL 0x10
#define NMATBX_OSCANCOLOR 0x11
#define NMATBX_COLPLANE_EN 0x12
#define NMATBX_HORPIXPAN 0x13
#define NMATBX_COLSEL 0x14
/* neomagic ISA GRAPHICS indexed registers */
/* VGA standard registers: */
#define NMGRPHX_ENSETRESET 0x01
#define NMGRPHX_DATAROTATE 0x03
#define NMGRPHX_READMAPSEL 0x04
#define NMGRPHX_MODE 0x05
#define NMGRPHX_MISC 0x06
#define NMGRPHX_BITMASK 0x08
/* NeoMagic specific registers: */
#define NMGRPHX_GRPHXLOCK 0x09
#define NMGRPHX_GENLOCK 0x0a
#define NMGRPHX_FBSTADDE 0x0e
#define NMGRPHX_CRTC_PITCHE 0x0f
#define NMGRPHX_IFACECTRL 0x11
#define NMGRPHX_PANELCTRL1 0x20
#define NMGRPHX_PANELTYPE 0x21
#define NMGRPHX_PANELCTRL2 0x25
#define NMGRPHX_PANELVCENT1 0x28
#define NMGRPHX_PANELVCENT2 0x29
#define NMGRPHX_PANELVCENT3 0x2a
#define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */
#define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */
#define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */
#define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */
#define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */
#define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */
#define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */
#define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */
#define NMGRPHX_CURCTRL 0x82
#define NMGRPHX_COLDEPTH 0x90
/* (NeoMagic pixelPLL set C registers) */
#define NMGRPHX_PLLC_NL 0x9b
#define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */
#define NMGRPHX_PLLC_M 0x9f
/* NeoMagic specific PCI cursor registers < NM2200 */
#define NMCR1_CURCTRL 0x0100
#define NMCR1_CURX 0x0104
#define NMCR1_CURY 0x0108
#define NMCR1_CURBGCOLOR 0x010c
#define NMCR1_CURFGCOLOR 0x0110
#define NMCR1_CURADDRESS 0x0114
/* NeoMagic specific PCI cursor registers >= NM2200 */
#define NMCR1_22CURCTRL 0x1000
#define NMCR1_22CURX 0x1004
#define NMCR1_22CURY 0x1008
#define NMCR1_22CURBGCOLOR 0x100c
#define NMCR1_22CURFGCOLOR 0x1010
#define NMCR1_22CURADDRESS 0x1014
//end new.
/* NM ACCeleration registers */
#define NMACC_DWGCTL 0x1C00
#define NMACC_MACCESS 0x1C04
#define NMACC_MCTLWTST 0x1C08
#define NMACC_ZORG 0x1C0C
#define NMACC_PLNWT 0x1C1C
#define NMACC_BCOL 0x1C20
#define NMACC_FCOL 0x1C24
#define NMACC_XYSTRT 0x1C40
#define NMACC_XYEND 0x1C44
#define NMACC_SGN 0x1C58
#define NMACC_LEN 0x1C5C
#define NMACC_AR0 0x1C60
#define NMACC_AR3 0x1C6C
#define NMACC_AR5 0x1C74
#define NMACC_CXBNDRY 0x1C80
#define NMACC_FXBNDRY 0x1C84
#define NMACC_YDSTLEN 0x1C88
#define NMACC_PITCH 0x1C8C
#define NMACC_YDST 0x1C90
#define NMACC_YDSTORG 0x1C94
#define NMACC_YTOP 0x1C98
#define NMACC_YBOT 0x1C9C
#define NMACC_CXLEFT 0x1CA0
#define NMACC_CXRIGHT 0x1CA4
#define NMACC_FXLEFT 0x1CA8
#define NMACC_FXRIGHT 0x1CAC
#define NMACC_STATUS 0x1E14
#define NMACC_ICLEAR 0x1E18 /* required for interrupt stuff */
#define NMACC_IEN 0x1E1C /* required for interrupt stuff */
#define NMACC_RST 0x1E40
#define NMACC_MEMRDBK 0x1E44
#define NMACC_OPMODE 0x1E54
#define NMACC_PRIMADDRESS 0x1E58
#define NMACC_PRIMEND 0x1E5C
#define NMACC_TEXORG 0x2C24 // >= G100
#define NMACC_DWGSYNC 0x2C4C // >= G200
#define NMACC_TEXORG1 0x2CA4 // >= G200
#define NMACC_TEXORG2 0x2CA8 // >= G200
#define NMACC_TEXORG3 0x2CAC // >= G200
#define NMACC_TEXORG4 0x2CB0 // >= G200
#define NMACC_SRCORG 0x2CB4 // >= G200
#define NMACC_DSTORG 0x2CB8 // >= G200
/*NM BES (Back End Scaler) registers (>= G200) */
#define NMBES_A1ORG 0x3D00
#define NMBES_A2ORG 0x3D04
#define NMBES_B1ORG 0x3D08
#define NMBES_B2ORG 0x3D0C
#define NMBES_A1CORG 0x3D10
#define NMBES_A2CORG 0x3D14
#define NMBES_B1CORG 0x3D18
#define NMBES_B2CORG 0x3D1C
#define NMBES_CTL 0x3D20
#define NMBES_PITCH 0x3D24
#define NMBES_HCOORD 0x3D28
#define NMBES_VCOORD 0x3D2C
#define NMBES_HISCAL 0x3D30
#define NMBES_VISCAL 0x3D34
#define NMBES_HSRCST 0x3D38
#define NMBES_HSRCEND 0x3D3C
#define NMBES_LUMACTL 0x3D40
#define NMBES_V1WGHT 0x3D48
#define NMBES_V2WGHT 0x3D4C
#define NMBES_HSRCLST 0x3D50
#define NMBES_V1SRCLST 0x3D54
#define NMBES_V2SRCLST 0x3D58
#define NMBES_A1C3ORG 0x3D60
#define NMBES_A2C3ORG 0x3D64
#define NMBES_B1C3ORG 0x3D68
#define NMBES_B2C3ORG 0x3D6C
#define NMBES_GLOBCTL 0x3DC0
#define NMBES_STATUS 0x3DC4
/* Macros for convenient accesses to the NM chips */
#define NM_REG8(r_) ((vuint8 *)regs)[(r_)]
#define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
/* read and write to PCI config space */
#define CFGR(A) (mn_pci_access.offset=NMCFG_##A, ioctl(fd,MN_GET_PCI, &mn_pci_access,sizeof(mn_pci_access)), mn_pci_access.value)
#define CFGW(A,B) (mn_pci_access.offset=NMCFG_##A, mn_pci_access.value = B, ioctl(fd,MN_SET_PCI,&mn_pci_access,sizeof(mn_pci_access)))
/* read and write from the powergraphics registers */
#define ACCR(A) (NM_REG32(NMACC_##A))
#define ACCW(A,B) (NM_REG32(NMACC_##A)=B)
#define ACCGO(A,B) (NM_REG32(NMACC_##A + 0x0100)=B)
/* read and write from the backend scaler registers */
#define BESR(A) (NM_REG32(NMBES_##A))
#define BESW(A,B) (NM_REG32(NMBES_##A)=B)
//new:
/* read and write from first CRTC (mapped) */
#define CR1R(A) (NM_REG32(NMCR1_##A))
#define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B))
/* read and write from ISA I/O space */
#define ISAWB(A,B)(mn_isa_access.adress=NMISA8_##A, mn_isa_access.data = (uint8)B, mn_isa_access.size = 1, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access)))
#define ISAWW(A,B)(mn_isa_access.adress=NMISA16_##A, mn_isa_access.data = B, mn_isa_access.size = 2, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access)))
#define ISARB(A) (mn_isa_access.adress=NMISA8_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), (uint8)mn_isa_access.data)
#define ISARW(A) (mn_isa_access.adress=NMISA16_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), mn_isa_access.data)
/* read and write from ISA CRTC indexed registers */
#define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8))))
#define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT))
/* read and write from ISA GRAPHICS indexed registers */
#define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8))))
#define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT))
/* read and write from ISA SEQUENCER indexed registers */
#define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8))))
#define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT))
/* read and write from ISA ATTRIBUTE indexed registers */
/* define DUMMY to prevent compiler warnings */
#define static uint8 DUMMY;
#define ISAATBW(A,B)(DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B)))
#define ISAATBR(A) (DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR))