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arm64: Use DEVICE_GRE memory when mapping MTR_WC.

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* This is the closest thing ARM has the semantics of write-combining
  MTR on x86.

Change-Id: I12a1582e0af871e2ab729262e90695ffe928c85b
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8223
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Owen Anderson
2024-09-04 17:15:24 +00:00
committed by waddlesplash
parent 4e4d316738
commit 0caf23319c
3 changed files with 9 additions and 2 deletions
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headers/private/kernel/arch/arm64/arm_registers.h
+2
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@@ -501,6 +501,8 @@
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00 #define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_DEVICE_nGnRE 0x04 #define MAIR_DEVICE_nGnRE 0x04
#define MAIR_DEVICE_nGRE 0x08
#define MAIR_DEVICE_GRE 0x0C
#define MAIR_NORMAL_NC 0x44 #define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0xbb #define MAIR_NORMAL_WT 0xbb
#define MAIR_NORMAL_WB 0xff #define MAIR_NORMAL_WB 0xff
src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp
+1 -1
View File
@@ -464,7 +464,7 @@ VMSAv8TranslationMap::GetMemoryAttr(uint32 attributes, uint32 memoryType, bool i
type = MAIR_DEVICE_nGnRnE; type = MAIR_DEVICE_nGnRnE;
break; break;
case B_MTR_WC: case B_MTR_WC:
type = MAIR_NORMAL_NC; type = MAIR_DEVICE_GRE;
break; break;
case B_MTR_WT: case B_MTR_WT:
type = MAIR_NORMAL_WT; type = MAIR_NORMAL_WT;
src/system/kernel/arch/arm64/arch_vm_translation_map.cpp
+6 -1
View File
@@ -72,7 +72,6 @@ arch_vm_translation_map_init(kernel_args* args, VMPhysicalPageMapper** _physical
uint32_t tg1 = (tcr >> 30) & 0x3; uint32_t tg1 = (tcr >> 30) & 0x3;
uint64_t ttbr0 = READ_SPECIALREG(TTBR0_EL1); uint64_t ttbr0 = READ_SPECIALREG(TTBR0_EL1);
uint64_t ttbr1 = READ_SPECIALREG(TTBR1_EL1); uint64_t ttbr1 = READ_SPECIALREG(TTBR1_EL1);
uint64_t mair = READ_SPECIALREG(MAIR_EL1);
uint64_t mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1); uint64_t mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
uint64_t mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1); uint64_t mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1);
uint64_t sctlr = READ_SPECIALREG(SCTLR_EL1); uint64_t sctlr = READ_SPECIALREG(SCTLR_EL1);
@@ -93,7 +92,13 @@ arch_vm_translation_map_init(kernel_args* args, VMPhysicalPageMapper** _physical
VMSAv8TranslationMap::fHwFeature |= VMSAv8TranslationMap::HW_COMMON_NOT_PRIVATE; VMSAv8TranslationMap::fHwFeature |= VMSAv8TranslationMap::HW_COMMON_NOT_PRIVATE;
} }
uint64_t mair =
(MAIR_DEVICE_nGnRnE) | // Uncached
(MAIR_DEVICE_GRE << 8) | // Write-combining
(MAIR_NORMAL_WT << 16) | // Write-through
(MAIR_NORMAL_WB << 24); // Write-back
VMSAv8TranslationMap::fMair = mair; VMSAv8TranslationMap::fMair = mair;
WRITE_SPECIALREG(MAIR_EL1, mair);
WRITE_SPECIALREG(TCR_EL1, tcr); WRITE_SPECIALREG(TCR_EL1, tcr);