i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Pointer style cleanup; Variable consolidation

Browse Source
This commit is contained in:
Alexander von Gluck IV
2011-12-09 21:26:41 -06:00
parent 61cf713381
commit 0cd5024dbb
16 changed files with 129 additions and 130 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/accelerants/radeon_hd/accelerant.cpp
+15 -15
View File
@@ -38,10 +38,10 @@
#endif
struct accelerant_info *gInfo;
display_info *gDisplay[MAX_DISPLAY];
connector_info *gConnector[ATOM_MAX_SUPPORTED_DEVICE];
gpio_info *gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE];
struct accelerant_info* gInfo;
display_info* gDisplay[MAX_DISPLAY];
connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE];
gpio_info* gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE];
class AreaCloner {
@@ -49,7 +49,7 @@ public:
AreaCloner();
~AreaCloner();
area_id Clone(const char *name, void **_address,
area_id Clone(const char* name, void** _address,
uint32 spec, uint32 protection,
area_id sourceArea);
status_t InitCheck()
@@ -76,7 +76,7 @@ AreaCloner::~AreaCloner()
area_id
AreaCloner::Clone(const char *name, void **_address, uint32 spec,
AreaCloner::Clone(const char* name, void** _address, uint32 spec,
uint32 protection, area_id sourceArea)
{
fArea = clone_area(name, _address, spec, protection, sourceArea);
@@ -102,7 +102,7 @@ init_common(int device, bool isClone)
{
// initialize global accelerant info structure
gInfo = (accelerant_info *)malloc(sizeof(accelerant_info));
gInfo = (accelerant_info*)malloc(sizeof(accelerant_info));
if (gInfo == NULL)
return B_NO_MEMORY;
@@ -111,12 +111,12 @@ init_common(int device, bool isClone)
// malloc memory for active display information
for (uint32 id = 0; id < MAX_DISPLAY; id++) {
gDisplay[id] = (display_info *)malloc(sizeof(display_info));
gDisplay[id] = (display_info*)malloc(sizeof(display_info));
if (gDisplay[id] == NULL)
return B_NO_MEMORY;
memset(gDisplay[id], 0, sizeof(display_info));
gDisplay[id]->regs = (register_info *)malloc(sizeof(register_info));
gDisplay[id]->regs = (register_info*)malloc(sizeof(register_info));
if (gDisplay[id]->regs == NULL)
return B_NO_MEMORY;
memset(gDisplay[id]->regs, 0, sizeof(register_info));
@@ -124,7 +124,7 @@ init_common(int device, bool isClone)
// malloc for possible physical card connectors
for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) {
gConnector[id] = (connector_info *)malloc(sizeof(connector_info));
gConnector[id] = (connector_info*)malloc(sizeof(connector_info));
if (gConnector[id] == NULL)
return B_NO_MEMORY;
@@ -133,7 +133,7 @@ init_common(int device, bool isClone)
// malloc for card gpio pin information
for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) {
gGPIOInfo[id] = (gpio_info *)malloc(sizeof(gpio_info));
gGPIOInfo[id] = (gpio_info*)malloc(sizeof(gpio_info));
if (gGPIOInfo[id] == NULL)
return B_NO_MEMORY;
@@ -159,7 +159,7 @@ init_common(int device, bool isClone)
AreaCloner sharedCloner;
gInfo->shared_info_area = sharedCloner.Clone("radeon hd shared info",
(void **)&gInfo->shared_info, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void**)&gInfo->shared_info, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
data.shared_info_area);
status_t status = sharedCloner.InitCheck();
if (status < B_OK) {
@@ -170,7 +170,7 @@ init_common(int device, bool isClone)
AreaCloner regsCloner;
gInfo->regs_area = regsCloner.Clone("radeon hd regs",
(void **)&gInfo->regs, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void**)&gInfo->regs, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
gInfo->shared_info->registers_area);
status = regsCloner.InitCheck();
if (status < B_OK) {
@@ -180,7 +180,7 @@ init_common(int device, bool isClone)
}
gInfo->rom_area = clone_area("radeon hd AtomBIOS",
(void **)&gInfo->rom, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void**)&gInfo->rom, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,
gInfo->shared_info->rom_area);
if (gInfo->rom_area < 0) {
@@ -312,7 +312,7 @@ radeon_uninit_accelerant(void)
status_t
radeon_get_accelerant_device_info(accelerant_device_info *di)
radeon_get_accelerant_device_info(accelerant_device_info* di)
{
radeon_shared_info &info = *gInfo->shared_info;
src/add-ons/accelerants/radeon_hd/accelerant.h
+10 -10
View File
@@ -48,13 +48,13 @@ struct fb_info {
struct accelerant_info {
vuint8 *regs;
vuint8* regs;
area_id regs_area;
radeon_shared_info *shared_info;
radeon_shared_info* shared_info;
area_id shared_info_area;
display_mode *mode_list; // cloned list of standard display modes
display_mode* mode_list; // cloned list of standard display modes
area_id mode_list_area;
uint8* rom;
@@ -154,7 +154,7 @@ typedef struct {
typedef struct {
bool active;
uint32 connectorIndex; // matches connector id in connector_info
register_info *regs;
register_info* regs;
bool found_ranges;
uint32 vfreq_max;
uint32 vfreq_min;
@@ -172,11 +172,11 @@ typedef struct {
#define MC 0x5 // Memory controller calls
extern accelerant_info *gInfo;
extern atom_context *gAtomContext;
extern display_info *gDisplay[MAX_DISPLAY];
extern connector_info *gConnector[ATOM_MAX_SUPPORTED_DEVICE];
extern gpio_info *gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE];
extern accelerant_info* gInfo;
extern atom_context* gAtomContext;
extern display_info* gDisplay[MAX_DISPLAY];
extern connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE];
extern gpio_info* gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE];
// register access
@@ -184,7 +184,7 @@ extern gpio_info *gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE];
inline uint32
_read32(uint32 offset)
{
return *(volatile uint32 *)(gInfo->regs + offset);
return *(volatile uint32*)(gInfo->regs + offset);
}
src/add-ons/accelerants/radeon_hd/accelerant_protos.h
+10 -10
View File
@@ -25,24 +25,24 @@ void spin(bigtime_t delay);
// general
status_t radeon_init_accelerant(int fd);
void radeon_uninit_accelerant(void);
status_t radeon_get_accelerant_device_info(accelerant_device_info *di);
status_t radeon_get_accelerant_device_info(accelerant_device_info* di);
// modes & constraints
uint32 radeon_accelerant_mode_count(void);
status_t radeon_get_mode_list(display_mode *dm);
status_t radeon_set_display_mode(display_mode *mode);
status_t radeon_get_display_mode(display_mode *currentMode);
status_t radeon_get_frame_buffer_config(frame_buffer_config *config);
status_t radeon_get_pixel_clock_limits(display_mode *mode,
uint32 *low, uint32 *high);
status_t radeon_get_mode_list(display_mode* dm);
status_t radeon_set_display_mode(display_mode* mode);
status_t radeon_get_display_mode(display_mode* currentMode);
status_t radeon_get_frame_buffer_config(frame_buffer_config* config);
status_t radeon_get_pixel_clock_limits(display_mode* mode,
uint32* low, uint32* high);
status_t radeon_get_edid_info(void* info, size_t size, uint32* edid_version);
// accelerant engine
uint32 radeon_accelerant_engine_count(void);
status_t radeon_acquire_engine(uint32 capabilities, uint32 maxWait,
sync_token *syncToken, engine_token **_engineToken);
status_t radeon_release_engine(engine_token *engineToken,
sync_token *syncToken);
sync_token* syncToken, engine_token** _engineToken);
status_t radeon_release_engine(engine_token* engineToken,
sync_token* syncToken);
#ifdef __cplusplus
src/add-ons/accelerants/radeon_hd/bios.cpp
+2 -2
View File
@@ -25,7 +25,7 @@
#endif
atom_context *gAtomContext;
atom_context* gAtomContext;
void
@@ -133,7 +133,7 @@ radeon_init_bios(uint8* bios)
radeon_dump_bios();
#endif
struct card_info *atom_card_info
struct card_info* atom_card_info
= (card_info*)malloc(sizeof(card_info));
if (!atom_card_info)
src/add-ons/accelerants/radeon_hd/connector.cpp
+46 -47
View File
@@ -38,8 +38,8 @@ union aux_channel_transaction {
static int
dp_aux_speak(uint32 hwLine, uint8 *send, int sendBytes,
uint8 *recv, int recvBytes, uint8 delay, uint8 *ack)
dp_aux_speak(uint32 hwLine, uint8* send, int sendBytes,
uint8* recv, int recvBytes, uint8 delay, uint8* ack)
{
if (hwLine == 0) {
ERROR("%s: cannot speak on invalid GPIO pin!\n", __func__);
@@ -51,7 +51,7 @@ dp_aux_speak(uint32 hwLine, uint8 *send, int sendBytes,
memset(&args, 0, sizeof(args));
unsigned char *base = (unsigned char *)gAtomContext->scratch;
unsigned char* base = (unsigned char*)gAtomContext->scratch;
memcpy(base, send, sendBytes);
args.v1.lpAuxRequest = 0;
@@ -92,7 +92,7 @@ dp_aux_speak(uint32 hwLine, uint8 *send, int sendBytes,
int
dp_aux_write(uint32 hwLine, uint16 address,
uint8 *send, uint8 sendBytes, uint8 delay)
uint8* send, uint8 sendBytes, uint8 delay)
{
uint8 auxMessage[20];
int auxMessageBytes = sendBytes + 4;
@@ -131,7 +131,7 @@ dp_aux_write(uint32 hwLine, uint16 address,
int
dp_aux_read(uint32 hwLine, uint16 address,
uint8 *recv, int recvBytes, uint8 delay)
uint8* recv, int recvBytes, uint8 delay)
{
uint8 auxMessage[4];
int auxMessageBytes = 4;
@@ -310,15 +310,14 @@ dp_aux_set_i2c_byte(uint32 hwLine, uint16 address, uint8* data, bool end)
static void
gpio_lock_i2c(void* cookie, bool lock)
{
gpio_info *info = (gpio_info*)cookie;
radeon_shared_info &sinfo = *gInfo->shared_info;
gpio_info* info = (gpio_info*)cookie;
uint32 buffer = 0;
if (lock == true) {
// hw_capable and > DCE3
if (info->hw_capable == true
&& sinfo.dceMajor >= 3) {
&& gInfo->shared_info->dceMajor >= 3) {
// Switch GPIO pads to ddc mode
buffer = Read32(OUT, info->mask_scl_reg);
buffer &= ~(1 << 16);
@@ -362,15 +361,15 @@ gpio_lock_i2c(void* cookie, bool lock)
static status_t
gpio_get_i2c_bit(void* cookie, int* _clock, int* _data)
{
gpio_info *info = (gpio_info*)cookie;
gpio_info* info = (gpio_info*)cookie;
uint32 scl = Read32(OUT, info->y_scl_reg)
& info->y_scl_mask;
uint32 sda = Read32(OUT, info->y_sda_reg)
& info->y_sda_mask;
*_clock = (scl != 0);
*_data = (sda != 0);
*_clock = scl != 0;
*_data = sda != 0;
return B_OK;
}
@@ -398,7 +397,7 @@ gpio_set_i2c_bit(void* cookie, int clock, int data)
bool
connector_read_edid(uint32 connectorIndex, edid1_info *edid)
connector_read_edid(uint32 connectorIndex, edid1_info* edid)
{
// ensure things are sane
uint32 gpioID = gConnector[connectorIndex]->gpioID;
@@ -436,7 +435,7 @@ connector_read_edid(uint32 connectorIndex, edid1_info *edid)
#if 0
bool
connector_read_edid_lvds(uint32 connectorIndex, edid1_info *edid)
connector_read_edid_lvds(uint32 connectorIndex, edid1_info* edid)
{
uint8 dceMajor;
uint8 dceMinor;
@@ -445,7 +444,7 @@ connector_read_edid_lvds(uint32 connectorIndex, edid1_info *edid)
if (atom_parse_data_header(gAtomContexg, index, NULL,
&dceMajor, &dceMinor, &offset) == B_OK) {
lvdsInfo = (union lvds_info *)(gAtomContext->bios + offset);
lvdsInfo = (union lvds_info*)(gAtomContext->bios + offset);
display_timing timing;
// Pixel Clock
@@ -539,8 +538,8 @@ gpio_probe()
return B_ERROR;
}
struct _ATOM_GPIO_I2C_INFO *i2c_info
= (struct _ATOM_GPIO_I2C_INFO *)(gAtomContext->bios + tableOffset);
struct _ATOM_GPIO_I2C_INFO* i2c_info
= (struct _ATOM_GPIO_I2C_INFO*)(gAtomContext->bios + tableOffset);
uint32 numIndices = (tableSize - sizeof(ATOM_COMMON_TABLE_HEADER))
/ sizeof(ATOM_GPIO_I2C_ASSIGMENT);
@@ -553,7 +552,7 @@ gpio_probe()
}
for (uint32 i = 0; i < numIndices; i++) {
ATOM_GPIO_I2C_ASSIGMENT *gpio = &i2c_info->asGPIO_Info[i];
ATOM_GPIO_I2C_ASSIGMENT* gpio = &i2c_info->asGPIO_Info[i];
if (info.dceMajor >= 3) {
if (i == 4 && B_LENDIAN_TO_HOST_INT16(gpio->usClkMaskRegisterIndex)
@@ -657,8 +656,8 @@ connector_probe_legacy()
return B_ERROR;
}
union atom_supported_devices *supportedDevices;
supportedDevices = (union atom_supported_devices *)
union atom_supported_devices* supportedDevices;
supportedDevices = (union atom_supported_devices*)
(gAtomContext->bios + tableOffset);
uint16 deviceSupport
@@ -767,23 +766,23 @@ connector_probe()
return B_ERROR;
}
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
ATOM_ENCODER_OBJECT_TABLE *enc_obj;
ATOM_OBJECT_TABLE *router_obj;
ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
ATOM_OBJECT_HEADER *obj_header;
ATOM_CONNECTOR_OBJECT_TABLE* con_obj;
ATOM_ENCODER_OBJECT_TABLE* enc_obj;
ATOM_OBJECT_TABLE* router_obj;
ATOM_DISPLAY_OBJECT_PATH_TABLE* path_obj;
ATOM_OBJECT_HEADER* obj_header;
obj_header = (ATOM_OBJECT_HEADER *)(gAtomContext->bios + tableOffset);
path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
obj_header = (ATOM_OBJECT_HEADER*)(gAtomContext->bios + tableOffset);
path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE*)
(gAtomContext->bios + tableOffset
+ B_LENDIAN_TO_HOST_INT16(obj_header->usDisplayPathTableOffset));
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE*)
(gAtomContext->bios + tableOffset
+ B_LENDIAN_TO_HOST_INT16(obj_header->usConnectorObjectTableOffset));
enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
enc_obj = (ATOM_ENCODER_OBJECT_TABLE*)
(gAtomContext->bios + tableOffset
+ B_LENDIAN_TO_HOST_INT16(obj_header->usEncoderObjectTableOffset));
router_obj = (ATOM_OBJECT_TABLE *)
router_obj = (ATOM_OBJECT_TABLE*)
(gAtomContext->bios + tableOffset
+ B_LENDIAN_TO_HOST_INT16(obj_header->usRouterObjectTableOffset));
int deviceSupport = B_LENDIAN_TO_HOST_INT16(obj_header->usDeviceSupport);
@@ -800,10 +799,10 @@ connector_probe()
if (connectorIndex >= ATOM_MAX_SUPPORTED_DEVICE)
continue;
uint8 *addr = (uint8*)path_obj->asDispPath;
ATOM_DISPLAY_OBJECT_PATH *path;
uint8* addr = (uint8*)path_obj->asDispPath;
ATOM_DISPLAY_OBJECT_PATH* path;
addr += pathSize;
path = (ATOM_DISPLAY_OBJECT_PATH *)addr;
path = (ATOM_DISPLAY_OBJECT_PATH*)addr;
pathSize += B_LENDIAN_TO_HOST_INT16(path->usSize);
uint32 connectorType;
@@ -865,12 +864,12 @@ connector_probe()
enc_obj->asObjects[k].usObjectID);
if (B_LENDIAN_TO_HOST_INT16(path->usGraphicObjIds[j])
== encoder_obj) {
ATOM_COMMON_RECORD_HEADER *record
= (ATOM_COMMON_RECORD_HEADER *)
((uint16 *)gAtomContext->bios + tableOffset
ATOM_COMMON_RECORD_HEADER* record
= (ATOM_COMMON_RECORD_HEADER*)
((uint16*)gAtomContext->bios + tableOffset
+ B_LENDIAN_TO_HOST_INT16(
enc_obj->asObjects[k].usRecordOffset));
ATOM_ENCODER_CAP_RECORD *cap_record;
ATOM_ENCODER_CAP_RECORD* cap_record;
uint16 caps = 0;
while (record->ucRecordSize > 0
&& record->ucRecordType > 0
@@ -878,14 +877,14 @@ connector_probe()
<= ATOM_MAX_OBJECT_RECORD_NUMBER) {
switch (record->ucRecordType) {
case ATOM_ENCODER_CAP_RECORD_TYPE:
cap_record = (ATOM_ENCODER_CAP_RECORD *)
cap_record = (ATOM_ENCODER_CAP_RECORD*)
record;
caps = B_LENDIAN_TO_HOST_INT16(
cap_record->usEncoderCap);
break;
}
record = (ATOM_COMMON_RECORD_HEADER *)
((char *)record + record->ucRecordSize);
record = (ATOM_COMMON_RECORD_HEADER*)
((char*)record + record->ucRecordSize);
}
uint32 encoderID = (encoder_obj & OBJECT_ID_MASK)
@@ -936,7 +935,7 @@ connector_probe()
if (B_LENDIAN_TO_HOST_INT16(path->usConnObjectId)
== B_LENDIAN_TO_HOST_INT16(
con_obj->asObjects[j].usObjectID)) {
ATOM_COMMON_RECORD_HEADER *record
ATOM_COMMON_RECORD_HEADER* record
= (ATOM_COMMON_RECORD_HEADER*)(gAtomContext->bios
+ tableOffset + B_LENDIAN_TO_HOST_INT16(
con_obj->asObjects[j].usRecordOffset));
@@ -944,16 +943,16 @@ connector_probe()
&& record->ucRecordType > 0
&& record->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER) {
ATOM_I2C_RECORD *i2c_record;
ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
//ATOM_HPD_INT_RECORD *hpd_record;
ATOM_I2C_RECORD* i2c_record;
ATOM_I2C_ID_CONFIG_ACCESS* i2c_config;
//ATOM_HPD_INT_RECORD* hpd_record;
switch (record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
i2c_record
= (ATOM_I2C_RECORD *)record;
= (ATOM_I2C_RECORD*)record;
i2c_config
= (ATOM_I2C_ID_CONFIG_ACCESS *)
= (ATOM_I2C_ID_CONFIG_ACCESS*)
&i2c_record->sucI2cId;
// attach i2c gpio information for connector
connector_attach_gpio(connectorIndex,
@@ -965,8 +964,8 @@ connector_probe()
}
// move to next record
record = (ATOM_COMMON_RECORD_HEADER *)
((char *)record + record->ucRecordSize);
record = (ATOM_COMMON_RECORD_HEADER*)
((char*)record + record->ucRecordSize);
}
}
}
src/add-ons/accelerants/radeon_hd/connector.h
+3 -3
View File
@@ -80,9 +80,9 @@ const int connector_convert[] = {
};
int dp_aux_write(uint32 hwLine, uint16 address, uint8 *send,
int dp_aux_write(uint32 hwLine, uint16 address, uint8* send,
uint8 sendBytes, uint8 delay);
int dp_aux_read(uint32 hwLine, uint16 address, uint8 *recv,
int dp_aux_read(uint32 hwLine, uint16 address, uint8* recv,
int recvBytes, uint8 delay);
status_t dp_aux_set_i2c_byte(uint32 hwLine, uint16 address,
uint8* data, bool end);
@@ -92,7 +92,7 @@ status_t dp_aux_get_i2c_byte(uint32 hwLine, uint16 address,
status_t gpio_probe();
status_t connector_attach_gpio(uint32 id, uint8 hw_line);
bool connector_read_edid(uint32 connector, edid1_info *edid);
bool connector_read_edid(uint32 connector, edid1_info* edid);
status_t connector_probe();
status_t connector_probe_legacy();
void debug_connectors();
src/add-ons/accelerants/radeon_hd/display.cpp
+8 -8
View File
@@ -26,7 +26,7 @@
#define TRACE_DISPLAY
#ifdef TRACE_DISPLAY
extern "C" void _sPrintf(const char *format, ...);
extern "C" void _sPrintf(const char* format, ...);
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
@@ -217,12 +217,12 @@ init_registers(register_info* regs, uint8 crtcID)
status_t
detect_crt_ranges(uint32 crtid)
{
edid1_info *edid = &gDisplay[crtid]->edid_info;
edid1_info* edid = &gDisplay[crtid]->edid_info;
// Scan each display EDID description for monitor ranges
for (uint32 index = 0; index < EDID1_NUM_DETAILED_MONITOR_DESC; index++) {
edid1_detailed_monitor *monitor
edid1_detailed_monitor* monitor
= &edid->detailed_monitor[index];
if (monitor->monitor_desc_type
@@ -411,7 +411,7 @@ display_crtc_blank(uint8 crtcID, int command)
void
display_crtc_scale(uint8 crtcID, display_mode *mode)
display_crtc_scale(uint8 crtcID, display_mode* mode)
{
TRACE("%s\n", __func__);
ENABLE_SCALER_PS_ALLOCATION args;
@@ -427,7 +427,7 @@ display_crtc_scale(uint8 crtcID, display_mode *mode)
void
display_crtc_fb_set(uint8 crtcID, display_mode *mode)
display_crtc_fb_set(uint8 crtcID, display_mode* mode)
{
radeon_shared_info &info = *gInfo->shared_info;
register_info* regs = gDisplay[crtcID]->regs;
@@ -583,7 +583,7 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode)
void
display_crtc_set(uint8 crtcID, display_mode *mode)
display_crtc_set(uint8 crtcID, display_mode* mode)
{
display_timing& displayTiming = mode->timing;
@@ -621,12 +621,12 @@ display_crtc_set(uint8 crtcID, display_mode *mode)
args.susModeMiscInfo.usAccess = B_HOST_TO_LENDIAN_INT16(misc);
args.ucCRTC = crtcID;
atom_execute_table(gAtomContext, index, (uint32 *)&args);
atom_execute_table(gAtomContext, index, (uint32*)&args);
}
void
display_crtc_set_dtd(uint8 crtcID, display_mode *mode)
display_crtc_set_dtd(uint8 crtcID, display_mode* mode)
{
display_timing& displayTiming = mode->timing;
src/add-ons/accelerants/radeon_hd/display.h
+4 -4
View File
@@ -22,10 +22,10 @@ void debug_displays();
uint32 display_get_encoder_mode(uint32 connectorIndex);
void display_crtc_lock(uint8 crtcID, int command);
void display_crtc_blank(uint8 crtcID, int command);
void display_crtc_scale(uint8 crtcID, display_mode *mode);
void display_crtc_fb_set(uint8 crtcID, display_mode *mode);
void display_crtc_set(uint8 crtcID, display_mode *mode);
void display_crtc_set_dtd(uint8 crtcID, display_mode *mode);
void display_crtc_scale(uint8 crtcID, display_mode* mode);
void display_crtc_fb_set(uint8 crtcID, display_mode* mode);
void display_crtc_set(uint8 crtcID, display_mode* mode);
void display_crtc_set_dtd(uint8 crtcID, display_mode* mode);
void display_crtc_power(uint8 crtcID, int command);
void display_crtc_memreq(uint8 crtcID, int command);
src/add-ons/accelerants/radeon_hd/encoder.cpp
+2 -2
View File
@@ -23,7 +23,7 @@
#define TRACE_ENCODER
#ifdef TRACE_ENCODER
extern "C" void _sPrintf(const char *format, ...);
extern "C" void _sPrintf(const char* format, ...);
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
@@ -1115,7 +1115,7 @@ encoder_output_lock(bool lock)
}
static const char *encoder_name_matrix[36] = {
static const char* encoder_name_matrix[36] = {
"NONE",
"Internal Radeon LVDS",
"Internal Radeon TMDS1",
src/add-ons/accelerants/radeon_hd/engine.cpp
+2 -2
View File
@@ -40,7 +40,7 @@ radeon_accelerant_engine_count(void)
status_t
radeon_acquire_engine(uint32 capabilities, uint32 maxWait,
sync_token *syncToken, engine_token **_engineToken)
sync_token* syncToken, engine_token** _engineToken)
{
TRACE("%s\n", __func__);
*_engineToken = &sEngineToken;
@@ -53,7 +53,7 @@ radeon_acquire_engine(uint32 capabilities, uint32 maxWait,
status_t
radeon_release_engine(engine_token *engineToken, sync_token *syncToken)
radeon_release_engine(engine_token* engineToken, sync_token* syncToken)
{
TRACE("%s\n", __func__);
if (syncToken != NULL)
src/add-ons/accelerants/radeon_hd/gpu.cpp
+2 -2
View File
@@ -164,7 +164,7 @@ radeon_gpu_reset()
void
radeon_gpu_mc_halt(gpu_state *gpuState)
radeon_gpu_mc_halt(gpu_state* gpuState)
{
// Backup current memory controller state
gpuState->d1vgaControl = Read32(OUT, D1VGA_CONTROL);
@@ -189,7 +189,7 @@ radeon_gpu_mc_halt(gpu_state *gpuState)
void
radeon_gpu_mc_resume(gpu_state *gpuState)
radeon_gpu_mc_resume(gpu_state* gpuState)
{
Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
src/add-ons/accelerants/radeon_hd/hooks.cpp
+2 -2
View File
@@ -12,8 +12,8 @@
#include "accelerant_protos.h"
extern "C" void *
get_accelerant_hook(uint32 feature, void *data)
extern "C" void*
get_accelerant_hook(uint32 feature, void* data)
{
switch (feature) {
/* general */
src/add-ons/accelerants/radeon_hd/mode.cpp
+9 -9
View File
@@ -29,7 +29,7 @@
#define TRACE_MODE
#ifdef TRACE_MODE
extern "C" void _sPrintf(const char *format, ...);
extern "C" void _sPrintf(const char* format, ...);
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
@@ -71,7 +71,7 @@ radeon_accelerant_mode_count(void)
status_t
radeon_get_mode_list(display_mode *modeList)
radeon_get_mode_list(display_mode* modeList)
{
TRACE("%s\n", __func__);
memcpy(modeList, gInfo->mode_list,
@@ -159,7 +159,7 @@ radeon_dpms_set(int mode)
status_t
radeon_set_display_mode(display_mode *mode)
radeon_set_display_mode(display_mode* mode)
{
radeon_shared_info &info = *gInfo->shared_info;
@@ -232,7 +232,7 @@ radeon_set_display_mode(display_mode *mode)
status_t
radeon_get_display_mode(display_mode *_currentMode)
radeon_get_display_mode(display_mode* _currentMode)
{
TRACE("%s\n", __func__);
@@ -242,7 +242,7 @@ radeon_get_display_mode(display_mode *_currentMode)
status_t
radeon_get_frame_buffer_config(frame_buffer_config *config)
radeon_get_frame_buffer_config(frame_buffer_config* config)
{
TRACE("%s\n", __func__);
@@ -256,14 +256,14 @@ radeon_get_frame_buffer_config(frame_buffer_config *config)
status_t
radeon_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high)
radeon_get_pixel_clock_limits(display_mode* mode, uint32* _low, uint32* _high)
{
TRACE("%s\n", __func__);
if (_low != NULL) {
// lower limit of about 48Hz vertical refresh
uint32 totalClocks = (uint32)mode->timing.h_total
*(uint32)mode->timing.v_total;
* (uint32)mode->timing.v_total;
uint32 low = (totalClocks * 48L) / 1000L;
if (low < PLL_MIN_DEFAULT)
@@ -284,7 +284,7 @@ radeon_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high)
bool
is_mode_supported(display_mode *mode)
is_mode_supported(display_mode* mode)
{
bool sane = true;
@@ -333,7 +333,7 @@ is_mode_supported(display_mode *mode)
* A quick sanity check of the provided display_mode
*/
status_t
is_mode_sane(display_mode *mode)
is_mode_sane(display_mode* mode)
{
// horizontal timing
// validate h_sync_start is less then h_sync_end
src/add-ons/accelerants/radeon_hd/mode.h
+1 -1
View File
@@ -29,7 +29,7 @@
status_t create_mode_list(void);
bool is_mode_supported(display_mode* mode);
status_t is_mode_sane(display_mode *mode);
status_t is_mode_sane(display_mode* mode);
uint32 radeon_dpms_capabilities(void);
uint32 radeon_dpms_mode(void);
void radeon_dpms_set(int mode);
src/add-ons/accelerants/radeon_hd/pll.cpp
+9 -9
View File
@@ -23,7 +23,7 @@
#define TRACE_PLL
#ifdef TRACE_PLL
extern "C" void _sPrintf(const char *format, ...);
extern "C" void _sPrintf(const char* format, ...);
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
@@ -43,7 +43,7 @@ union firmware_info {
status_t
pll_limit_probe(pll_info *pll)
pll_limit_probe(pll_info* pll)
{
int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
uint8 tableMajor;
@@ -56,8 +56,8 @@ pll_limit_probe(pll_info *pll)
return B_ERROR;
}
union firmware_info *firmwareInfo
= (union firmware_info *)(gAtomContext->bios + tableOffset);
union firmware_info* firmwareInfo
= (union firmware_info*)(gAtomContext->bios + tableOffset);
/* pixel clock limits */
pll->referenceFreq
@@ -124,7 +124,7 @@ pll_limit_probe(pll_info *pll)
void
pll_compute_post_divider(pll_info *pll)
pll_compute_post_divider(pll_info* pll)
{
if ((pll->flags & PLL_USE_POST_DIV) != 0) {
TRACE("%s: using AtomBIOS post divider\n", __func__);
@@ -168,7 +168,7 @@ pll_compute_post_divider(pll_info *pll)
status_t
pll_compute(pll_info *pll)
pll_compute(pll_info* pll)
{
pll_compute_post_divider(pll);
@@ -291,7 +291,7 @@ union adjust_pixel_clock {
void
pll_setup_flags(pll_info *pll, uint8 crtcID)
pll_setup_flags(pll_info* pll, uint8 crtcID)
{
radeon_shared_info &info = *gInfo->shared_info;
uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
@@ -328,7 +328,7 @@ pll_setup_flags(pll_info *pll, uint8 crtcID)
status_t
pll_adjust(pll_info *pll, uint8 crtcID)
pll_adjust(pll_info* pll, uint8 crtcID)
{
// TODO: PLL flags
radeon_shared_info &info = *gInfo->shared_info;
@@ -485,7 +485,7 @@ status_t
pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
{
uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
pll_info *pll = &gConnector[connectorIndex]->encoder.pll;
pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
pll->pixelClock = pixelClock;
pll->id = pllID;
src/add-ons/accelerants/radeon_hd/pll.h
+4 -4
View File
@@ -84,10 +84,10 @@ struct pll_info {
};
status_t pll_adjust(pll_info *pll, uint8 crtcID);
status_t pll_compute(pll_info *pll);
void pll_setup_flags(pll_info *pll, uint8 crtcID);
status_t pll_limit_probe(pll_info *pll);
status_t pll_adjust(pll_info* pll, uint8 crtcID);
status_t pll_compute(pll_info* pll);
void pll_setup_flags(pll_info* pll, uint8 crtcID);
status_t pll_limit_probe(pll_info* pll);
status_t pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID);