headers for nvidia_gpgpu driver
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25874 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
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/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002-9/2007.
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*/
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#ifndef DRIVERINTERFACE_H
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#define DRIVERINTERFACE_H
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#include <Accelerant.h>
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#include "video_overlay.h"
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#include <Drivers.h>
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#include <PCI.h>
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#include <OS.h>
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#define DRIVER_PREFIX "nvidia_gpgpu"
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#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x"
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/*
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Internal driver state (also for sharing info between driver and accelerant)
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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typedef struct {
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sem_id sem;
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int32 ben;
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} benaphore;
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#define INIT_BEN(x) x.sem = create_sem(0, "NV_GPGPU "#x" benaphore"); x.ben = 0;
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#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
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/* dualhead extensions to flags */
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#define DUALHEAD_OFF (0<<6)
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#define DUALHEAD_CLONE (1<<6)
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#define DUALHEAD_ON (2<<6)
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#define DUALHEAD_SWITCH (3<<6)
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#define DUALHEAD_BITS (3<<6)
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#define DUALHEAD_CAPABLE (1<<8)
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#define TV_BITS (3<<9)
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#define TV_MON (0<<9
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#define TV_PAL (1<<9)
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#define TV_NTSC (2<<9)
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#define TV_CAPABLE (1<<11)
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#define TV_VIDEO (1<<12)
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#define TV_PRIMARY (1<<13)
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#define SKD_MOVE_CURSOR 0x00000001
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#define SKD_PROGRAM_CLUT 0x00000002
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#define SKD_SET_START_ADDR 0x00000004
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#define SKD_SET_CURSOR 0x00000008
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#define SKD_HANDLER_INSTALLED 0x80000000
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enum {
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NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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NV_GET_PCI,
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NV_SET_PCI,
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NV_DEVICE_NAME,
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NV_RUN_INTERRUPTS,
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NV_ISA_OUT,
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NV_ISA_IN
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};
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/* card_type in order of date of NV chip design */
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enum {
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NV04 = 0,
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NV05,
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NV05M64,
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NV06,
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NV10,
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NV11,
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NV11M,
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NV15,
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NV17,
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NV17M,
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NV18,
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NV18M,
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NV20,
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NV25,
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NV28,
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NV30,
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NV31,
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NV34,
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NV35,
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NV36,
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NV38,
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NV40,
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NV41,
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NV43,
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NV44,
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NV45,
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G70,
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G71,
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G72,
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G73,
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G80,
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G84,
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G86
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};
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/* card_arch in order of date of NV chip design */
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enum {
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NV04A = 0,
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NV10A,
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NV20A,
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NV30A,
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NV40A,
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NV50A
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};
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // tv_encoder_type in order of capability (more or less)
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NONE = 0,
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CH7003,
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CH7004,
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CH7005,
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CH7006,
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CH7007,
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CH7008,
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SAA7102,
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SAA7103,
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SAA7104,
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SAA7105,
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BT868,
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BT869,
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CX25870,
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CX25871,
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NVIDIA
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};
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/* handles to pre-defined engine commands */
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#define NV_ROP5_SOLID 0x00000000 /* 2D */
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#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */
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#define NV_IMAGE_PATTERN 0x00000002 /* 2D */
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#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */
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#define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007
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#define NV4_SURFACE 0x00000010 /* 2D */
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#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */
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#define NV_IMAGE_BLIT 0x00000011 /* 2D */
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#define NV12_IMAGE_BLIT 0x00000011 /* 2D */
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/* fixme:
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* never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration:
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* There's a hardware fault in the input->output colorspace conversion here.
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* Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed
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* by testing.
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*/
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//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
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#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
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#define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */
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#define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */
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#define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */
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#define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */
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#define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */
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#define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */
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#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */
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/* max. number of overlay buffers */
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#define MAXBUFFERS 3
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//-----------------------------------------------------------------------------------
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/* safety byte-offset from end of cardRAM for preventing acceleration engine crashes
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* caused by the existance of DMA engine command buffers in cardRAM and/or fifo
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* channel engine command re-assigning on-the-fly */
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/* pre-NV40 notes:
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* - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug'
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* (confirmed on a TNT1);
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* - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
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#define PRE_NV40_OFFSET 80 * 1024
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/* NV40 and higher notes:
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* - we need at least 416kB distance from the DMA command buffer:
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* If you get too close to the DMA command buffer on NV40 and NV43 at least (both
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* confirmed), the source DMA instance will mess-up for at least engine command
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* NV_IMAGE_BLIT and NV12_IMAGE_BLIT;
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* - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug'
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* (fixme: unknown yet because fifo assignment switching isn't used here atm);
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* - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
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#define NV40_PLUS_OFFSET 512 * 1024
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/* fifo re-assigning bug definition:
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* if the fifo assignment is changed while at the same time card memory in the
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* dangerous region is being accessed by some application, the engine will crash.
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* This bug applies for both PIO and DMA mode acceleration! */
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/* source-DMA instance bug definition:
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* if card memory in the dangerous region is being accessed by some application while
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* a DMA command buffer exists in the same memory (though in a different place),
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* the engine will crash. */
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//-----------------------------------------------------------------------------------
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/* internal used info on overlay buffers */
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typedef struct {
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uint16 slopspace;
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uint32 size;
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} int_buf_info;
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typedef struct { // apsed, see comments in nv.settings
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// for driver
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char accelerant[B_FILE_NAME_LENGTH];
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char primary[B_FILE_NAME_LENGTH];
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bool dumprom;
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// for accelerant
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uint32 logmask;
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uint32 memory;
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uint32 tv_output;
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bool usebios;
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bool hardcursor;
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bool switchhead;
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bool pgm_panel;
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bool dma_acc;
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bool vga_on_tv;
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bool force_sync;
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bool force_ws;
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uint32 gpu_clk;
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uint32 ram_clk;
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} nv_settings;
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/* shared info */
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typedef struct {
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/* a few ID things */
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uint16 vendor_id; /* PCI vendor ID, from pci_info */
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uint16 device_id; /* PCI device ID, from pci_info */
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uint8 revision; /* PCI device revsion, from pci_info */
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uint8 bus; /* PCI bus number, from pci_info */
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uint8 device; /* PCI device number on bus, from pci_info */
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uint8 function; /* PCI function number in device, from pci_info */
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/* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */
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bool accelerant_in_use;
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/* bug workaround for 4.5.0 */
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uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
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uint32 * clone_bugfix_regs;
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/*memory mappings*/
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area_id regs_area; /* Kernel's area_id for the memory mapped registers.
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It will be cloned into the accelerant's address
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space. */
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area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
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area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an
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aligned area using MTRR-WC. */
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area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */
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void *framebuffer; /* As viewed from virtual memory */
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void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
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void *dma_buffer; /* As viewed from virtual memory */
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void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */
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/*screenmode list*/
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area_id mode_area; /* Contains the list of display modes the driver supports */
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uint32 mode_count; /* Number of display modes in the list */
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/*flags - used by driver*/
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uint32 flags;
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/*vblank semaphore*/
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sem_id vblank; /* The vertical blank semaphore. Ownership will be
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transfered to the team opening the device first */
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/*cursor information*/
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struct {
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uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
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uint16 hot_y; /* is 0,0 */
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uint16 x; /* The location of the cursor hot spot on the */
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uint16 y; /* desktop */
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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bool dh_right; /* Is cursor on right side of stretched screen? */
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} cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration: head1 */
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uint32 dpms_flags; /* current DPMS mode */
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bool acc_mode; /* signals (non)accelerated mode */
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bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
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bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
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accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acc engine */
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struct {
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uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */
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uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */
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} fifo;
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struct {
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uint32 put; /* last 32-bit-word adress given to engine to exec. to */
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uint32 current; /* first free 32-bit-word adress in buffer */
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uint32 free; /* nr. of useable free 32-bit words remaining in buffer */
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uint32 max; /* command buffer's useable size in 32-bit words */
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} dma;
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struct {
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uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */
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uint32 reload; /* reload state and surfaces (one bit per clone) */
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uint32 newmode; /* re-allocate all buffers (one bit per clone) */
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//fixme: memory stuff needs to be expanded (shared texture allocation?)
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uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */
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uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */
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bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */
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} threeD;
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} engine;
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struct
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{
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/* specialised registers for card initialisation read from NV BIOS (pins) */
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/* general card information */
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uint32 card_type; /* see card_type enum above */
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uint32 card_arch; /* see card_arch enum above */
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bool laptop; /* mobile chipset or not ('internal' flatpanel!) */
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bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */
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bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */
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bool master_tmds1; /* on die TMDS encoder active on CRTC1 */
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bool master_tmds2; /* on die TMDS encoder active on CRTC2 */
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bool tmds1_active; /* found panel on CRTC1 that is active */
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bool tmds2_active; /* found panel on CRTC2 that is active */
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display_timing p1_timing; /* 'modeline' fetched for panel 1 */
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display_timing p2_timing; /* 'modeline' fetched for panel 2 */
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float panel1_aspect; /* panel's aspect ratio */
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float panel2_aspect; /* panel's aspect ratio */
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bool crtc2_prim; /* using CRTC2 as primary CRTC */
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bool i2c_bus0; /* we have a wired I2C bus 0 on board */
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bool i2c_bus1; /* we have a wired I2C bus 1 on board */
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bool i2c_bus2; /* we have a wired I2C bus 2 on board */
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bool i2c_bus3; /* we have a wired I2C bus 3 on board */
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struct
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{
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uint32 type; /* see tvchip_type enum above */
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uint8 version; /* chip silicon version */
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uint8 bus; /* I2C bus on which TVout chip resides */
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uint8 adress; /* I2C adress on which TVout chip resides */
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} tv_encoder;
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uint8 monitors; /* output devices connection matrix */
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bool int_assigned; /* card has a useable INT assigned to it */
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status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
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/* PINS */
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float f_ref; /* PLL reference-oscillator frequency (Mhz) */
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bool ext_pll; /* the extended PLL contains more dividers */
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uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
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uint32 min_system_vco;
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uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
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uint32 min_pixel_vco;
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uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */
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uint32 min_video_vco;
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uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
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uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */
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uint32 max_dac1_clock; /* dac1 limits (Mhz) */
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uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac1_clock_16;
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uint32 max_dac1_clock_24;
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uint32 max_dac1_clock_32;
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uint32 max_dac1_clock_32dh;
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uint32 max_dac2_clock; /* dac2 limits (Mhz) */
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uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac2_clock_16;
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uint32 max_dac2_clock_24;
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uint32 max_dac2_clock_32;
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uint32 max_dac2_clock_32dh;
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bool secondary_head; /* presence of functions */
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bool tvout;
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bool primary_dvi;
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bool secondary_dvi;
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uint32 memory_size; /* memory (in bytes) */
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} ps;
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/* mirror of the ROM (copied in driver, because may not be mapped permanently) */
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uint8 rom_mirror[65536];
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/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
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nv_settings settings;
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struct
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{
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||||
overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
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int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
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||||
overlay_token myToken; /* scaler is free/in use */
|
||||
benaphore lock; /* for creating buffers and aquiring overlay unit routines */
|
||||
bool crtc; /* location of overlay unit */
|
||||
/* variables needed for virtualscreens (move_overlay()): */
|
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bool active; /* true is overlay currently in use */
|
||||
overlay_window ow; /* current position of overlay output window */
|
||||
overlay_buffer ob; /* current inputbuffer in use */
|
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overlay_view my_ov; /* current corrected view in inputbuffer */
|
||||
uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */
|
||||
uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */
|
||||
} overlay;
|
||||
|
||||
} shared_info;
|
||||
|
||||
/* Read or write a value in PCI configuration space */
|
||||
typedef struct {
|
||||
uint32 magic; /* magic number to make sure the caller groks us */
|
||||
uint32 offset; /* Offset to read/write */
|
||||
uint32 size; /* Number of bytes to transfer */
|
||||
uint32 value; /* The value read or written */
|
||||
} nv_get_set_pci;
|
||||
|
||||
/* Enable or Disable CRTC (1,2) interrupts */
|
||||
typedef struct {
|
||||
uint32 magic; /* magic number to make sure the caller groks us */
|
||||
bool crtc; /* adressed CRTC */
|
||||
bool do_it; /* state to set */
|
||||
} nv_set_vblank_int;
|
||||
|
||||
/* Retrieve the area_id of the kernel/accelerant shared info */
|
||||
typedef struct {
|
||||
uint32 magic; /* magic number to make sure the caller groks us */
|
||||
area_id shared_info_area; /* area_id containing the shared information */
|
||||
} nv_get_private_data;
|
||||
|
||||
/* Retrieve the device name. Usefull for when we have a file handle, but want
|
||||
to know the device name (like when we are cloning the accelerant) */
|
||||
typedef struct {
|
||||
uint32 magic; /* magic number to make sure the caller groks us */
|
||||
char *name; /* The name of the device, less the /dev root */
|
||||
} nv_device_name;
|
||||
|
||||
/* Read or write a value in ISA I/O space */
|
||||
typedef struct {
|
||||
uint32 magic; /* magic number to make sure the caller groks us */
|
||||
uint16 adress; /* Offset to read/write */
|
||||
uint8 size; /* Number of bytes to transfer */
|
||||
uint16 data; /* The value read or written */
|
||||
} nv_in_out_isa;
|
||||
|
||||
enum {
|
||||
|
||||
_WAIT_FOR_VBLANK = (1 << 0)
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,311 @@
|
||||
/*
|
||||
definitions for used nVidia acceleration engine commands.
|
||||
|
||||
Written by Rudolf Cornelissen 12/2004-12/2005
|
||||
*/
|
||||
|
||||
#ifndef NV_ACC_H
|
||||
#define NV_ACC_H
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 SetRop5; /* b0-7 is ROP5 */
|
||||
} cmd_nv_rop5_solid;
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 TopLeft; /* b0-15 is left, b16-31 is top */
|
||||
uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
|
||||
} cmd_nv_image_black_rectangle;
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 SetColorFormat; /* colorspace */
|
||||
uint32 reserved03[0x0001];
|
||||
uint32 SetShape; /* b0-1: %00 = 8X_8Y; %01 = 64X_1Y; %10 = 1X_64Y */
|
||||
uint32 reserved04[0x0001];
|
||||
uint32 SetColor0; /* b0-31 is color */
|
||||
uint32 SetColor1; /* b0-31 is color */
|
||||
uint32 SetPattern[0x0002]; /* b0-31 is bitmap */
|
||||
} cmd_nv_image_pattern;
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 SourceOrg; /* b0-15 is X, b16-31 is Y */
|
||||
uint32 DestOrg; /* b0-15 is X, b16-31 is Y */
|
||||
uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
|
||||
} cmd_nv_image_blit;
|
||||
|
||||
//fixme: using nv4_gdi_rectangle_text for DMA acc. Differs slightly from this one!
|
||||
//WARNING: nv4_gdi_rectangle_text can only do 32 unclipped rects at once!
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 SetColorFormat; /* colorspace */
|
||||
uint32 reserved03[0x003e];
|
||||
uint32 Color1A; /* b0-31 is color */
|
||||
struct {
|
||||
uint32 LeftTop; /* b0-15 is top, b16-31 is left */
|
||||
uint32 WidthHeight; /* b0-15 is height, b16-31 is width */
|
||||
} UnclippedRectangle[0x40]; /* command can handle upto 64 unclipped rects */
|
||||
/* fixme: XFree also defines the registers below:
|
||||
* (used for the 2D 'ScanlineCPUToScreenColorExpandFill' and 'ColorExpandScanline'
|
||||
* functions.)
|
||||
* We don't use this currently. */
|
||||
/*
|
||||
U032 reserved04[(0x080)-3];
|
||||
struct
|
||||
{
|
||||
U032 TopLeft;
|
||||
U032 BottomRight;
|
||||
} ClipB;
|
||||
U032 Color1B;
|
||||
struct
|
||||
{
|
||||
U032 TopLeft;
|
||||
U032 BottomRight;
|
||||
} ClippedRectangle[64];
|
||||
U032 reserved05[(0x080)-5];
|
||||
struct
|
||||
{
|
||||
U032 TopLeft;
|
||||
U032 BottomRight;
|
||||
} ClipC;
|
||||
U032 Color1C;
|
||||
U032 WidthHeightC;
|
||||
U032 PointC;
|
||||
U032 MonochromeData1C;
|
||||
U032 reserved06[(0x080)+121];
|
||||
struct
|
||||
{
|
||||
U032 TopLeft;
|
||||
U032 BottomRight;
|
||||
} ClipD;
|
||||
U032 Color1D;
|
||||
U032 WidthHeightInD;
|
||||
U032 WidthHeightOutD;
|
||||
U032 PointD;
|
||||
U032 MonochromeData1D;
|
||||
U032 reserved07[(0x080)+120];
|
||||
struct
|
||||
{
|
||||
U032 TopLeft;
|
||||
U032 BottomRight;
|
||||
} ClipE;
|
||||
U032 Color0E;
|
||||
U032 Color1E;
|
||||
U032 WidthHeightInE;
|
||||
U032 WidthHeightOutE;
|
||||
U032 PointE;
|
||||
U032 MonochromeData01E;
|
||||
*/
|
||||
} cmd_nv3_gdi_rectangle_text;
|
||||
|
||||
/* This command could (at least) potentially speed-up our fill_span command... :-) */
|
||||
//fixme: test this 2D command!
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00af];
|
||||
uint32 Color; /* b0-31 is color */
|
||||
uint32 reserved03[0x003e];
|
||||
struct {
|
||||
uint32 Point0; /* b0-15 is X, b16-31 is Y: starting coordinate */
|
||||
uint32 Point1; /* b0-15 is X, b16-31 is Y: ending coordinate */
|
||||
} Line[0x10]; /* command can handle upto 16 lines */
|
||||
struct {
|
||||
uint32 Point0X; /* b0-31 is X: starting coordinate */
|
||||
uint32 Point0Y; /* b0-31 is Y: starting coordinate */
|
||||
uint32 Point1X; /* b0-31 is X: ending coordinate */
|
||||
uint32 Point1Y; /* b0-31 is Y: ending coordinate */
|
||||
} Line32[0x08]; /* cmd can handle upto 8 lines with 32-bit coordinates */
|
||||
struct {
|
||||
uint32 Point; /* b0-15 is X, b16-31 is Y */
|
||||
} Polyline[0x20]; /* cmd can handle upto 32 points polylines */
|
||||
struct {
|
||||
uint32 PointX; /* b0-31 is X */
|
||||
uint32 PointY; /* b0-31 is Y */
|
||||
} Polyline32[0x10]; /* cmd can handle upto 16 point polylines with 32-bit coord's */
|
||||
struct {
|
||||
uint32 Color; /* b0-31 is color */
|
||||
uint32 Point; /* b0-15 is X, b16-31 is Y */
|
||||
} ColorPolyline[0x10]; /* cmd can handle upto 16 point polylines with individually
|
||||
* colored sections */
|
||||
} cmd_nv1_render_solid_lin;
|
||||
|
||||
/* Someone defined this in XFree once (as 'RivaRectangle') but never used it:
|
||||
* a handle should also be defined in the engine's init code, which was never done AFAIK.
|
||||
* The command could be very interesting for us, as it could potentially speed-up our
|
||||
* rectangle_fills :-) */
|
||||
//fixme: test this 2D command!
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00af];
|
||||
uint32 Color; /* b0-31 is color */
|
||||
uint32 reserved03[0x003e];
|
||||
struct {
|
||||
uint32 TopLeft; /* b0-15 is left, b16-31 is top */
|
||||
uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
|
||||
} Rectangle[0x10]; /* command can handle upto 16 rectangles */
|
||||
} cmd_nv_render_solid_rectangle;/* nv1_render_solid_rectangle is identical */
|
||||
|
||||
//fixme: (setup in progress for DMA) complete or remove (this cmd is not used currently)
|
||||
typedef struct {
|
||||
} cmd_nv1_image_from_cpu; /* 'pixmap': used in XFree 4.2.0, but not beyond.
|
||||
* (Used for the 2D 'ImageWriteScanline' and
|
||||
* 'ScanlineImageWriteRect' functions.)
|
||||
* Is this command actually usefull? */
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 Format; /* buffer colorspace */
|
||||
uint32 Pitch; /* b0-15 is source pitch, b16-31 is dest pitch */
|
||||
uint32 OffsetSource; /* b0-31 is source bufferadress offset */
|
||||
uint32 OffsetDest; /* b0-31 is dest bufferadress offset */
|
||||
} cmd_nv4_surface; /* nv10_context_surfaces_2d is identical as far as used */
|
||||
|
||||
/************************
|
||||
* 3D specific commands *
|
||||
************************/
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00ae];
|
||||
uint32 Colorkey; /* texture colorkey */
|
||||
uint32 Offset; /* texture offset */
|
||||
uint32 Format; /* texture colorspace, size, and a lot more */
|
||||
uint32 Filter; /* texture filtering modes (used for scaling) */
|
||||
uint32 Blend; /* triangle blend: shade, perspective, specular.. */
|
||||
uint32 Control; /* triangle control: Z-enable, culling, dither.. */
|
||||
uint32 FogColor; /* fog colorvalue */
|
||||
uint32 reserved03[0x0039];
|
||||
struct {
|
||||
float ScreenX; /* X */
|
||||
float ScreenY; /* Y */
|
||||
float ScreenZ; /* depth */
|
||||
float RWH; /* eyeM */
|
||||
uint32 Color; /* b24-31 Alpha, b16-23 Red, b8-15 Green, b0-7 Blue */
|
||||
uint32 Specular; /* b24-31 Fog, b16-23 Red, b8-15 Green, b0-7 Blue */
|
||||
float TU; /* texture S */
|
||||
float TV; /* texture T */
|
||||
} TLVertex[0x10]; /* command can handle upto 16 textured, lit(?) vertexes */
|
||||
uint32 TLVDrawPrim[0x40]; /* b20-31 is I5, b16-19 is I4, b12-15 is I3,
|
||||
* b8-11 is I2, 4-7 is I1, b0-3 is I0:
|
||||
* Ix is a TLVertex[Ix].
|
||||
* So: define your (single) texture, define your
|
||||
* vertexes, and then program TLVDrawPrim with the
|
||||
* order to draw them.
|
||||
* You can draw primitives consisting of sets of upto
|
||||
* 6 out of 16 defined vertexes this way; and you can
|
||||
* draw 64 sets maximum. */
|
||||
} cmd_nv4_dx5_texture_triangle; /* nv10_dx5_texture_triangle is identical */
|
||||
|
||||
typedef struct {
|
||||
uint32 reserved00[0x0004];
|
||||
uint16 FifoFree; /* little endian (FIFO internal register) */
|
||||
uint16 Nop; /* little endian (FIFO internal register) */
|
||||
uint32 reserved01[0x000b];
|
||||
uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
|
||||
uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
|
||||
uint32 reserved02[0x00b0]; /* fixme? there's more here that's not used apparantly */
|
||||
uint32 Pitch; /* b16-31 is Z-buffer, b0-15 is colorbuffer pitch */
|
||||
uint32 SetOffsetColor; /* b0-31 is colorbuffer (renderbuffer) offset */
|
||||
uint32 SetOffsetZeta; /* b0-31 is Z-buffer (zeta buffer) offset */
|
||||
} cmd_nv4_context_surfaces_argb_zs; /* nv10_context_surfaces_argb_zs is identical */
|
||||
|
||||
//fixme: fill this out...
|
||||
typedef struct {
|
||||
} cmd_nv4_dx6_multi_texture_triangle;/* nv10_dx6_multi_texture_triangle is identical? */
|
||||
|
||||
|
||||
/************ DMA command defines ***********/
|
||||
|
||||
/* FIFO channels */
|
||||
#define NV_GENERAL_FIFO_CH0 0x0000
|
||||
#define NV_GENERAL_FIFO_CH1 0x2000
|
||||
#define NV_GENERAL_FIFO_CH2 0x4000
|
||||
#define NV_GENERAL_FIFO_CH3 0x6000
|
||||
#define NV_GENERAL_FIFO_CH4 0x8000
|
||||
#define NV_GENERAL_FIFO_CH5 0xa000
|
||||
#define NV_GENERAL_FIFO_CH6 0xc000
|
||||
#define NV_GENERAL_FIFO_CH7 0xe000
|
||||
|
||||
/* sub-command offsets within FIFO channels */
|
||||
#define NV_GENERAL_DMAPUT 0x0040
|
||||
#define NV_GENERAL_DMAGET 0x0044
|
||||
#define NV_ROP5_SOLID_SETROP5 0x0300
|
||||
#define NV_IMAGE_BLACK_RECTANGLE_TOPLEFT 0x0300
|
||||
#define NV_IMAGE_PATTERN_SETCOLORFORMAT 0x0300
|
||||
#define NV_IMAGE_PATTERN_SETSHAPE 0x0308
|
||||
#define NV_IMAGE_PATTERN_SETCOLOR0 0x0310
|
||||
#define NV_IMAGE_BLIT_SOURCEORG 0x0300
|
||||
//fixme note: non-DMA acc is still using NV3_GDI_RECTANGLE_TEXT...
|
||||
//which is just as fast as NV4_GDI_RECTANGLE_TEXT, but has a hardware fault for DMA!
|
||||
#define NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT 0x0300
|
||||
#define NV4_GDI_RECTANGLE_TEXT_COLOR1A 0x03fc
|
||||
#define NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP 0x0400
|
||||
#define NV4_SURFACE_FORMAT 0x0300
|
||||
#define NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT 0x0300
|
||||
#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCEORG 0x0308
|
||||
#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCESIZE 0x0400
|
||||
|
||||
|
||||
/************************
|
||||
* 3D specific commands *
|
||||
************************/
|
||||
|
||||
#define NV4_DX5_TEXTURE_TRIANGLE_COLORKEY 0x0300
|
||||
#define NV4_DX5_TEXTURE_TRIANGLE_TLVERTEX(i) 0x0400 + (i << 5)
|
||||
#define NV4_DX5_TEXTURE_TRIANGLE_TLVDRAWPRIM(i) 0x0600 + (i << 2)
|
||||
#define NV4_CONTEXT_SURFACES_ARGB_ZS_PITCH 0x0308
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,912 @@
|
||||
/* NV registers definitions and macros for access to them */
|
||||
|
||||
/* PCI_config_space */
|
||||
#define NVCFG_DEVID 0x00
|
||||
#define NVCFG_DEVCTRL 0x04
|
||||
#define NVCFG_CLASS 0x08
|
||||
#define NVCFG_HEADER 0x0c
|
||||
#define NVCFG_BASE1REGS 0x10
|
||||
#define NVCFG_BASE2FB 0x14
|
||||
#define NVCFG_BASE3 0x18
|
||||
#define NVCFG_BASE4 0x1c //unknown if used
|
||||
#define NVCFG_BASE5 0x20 //unknown if used
|
||||
#define NVCFG_BASE6 0x24 //unknown if used
|
||||
#define NVCFG_BASE7 0x28 //unknown if used
|
||||
#define NVCFG_SUBSYSID1 0x2c
|
||||
#define NVCFG_ROMBASE 0x30
|
||||
#define NVCFG_CAPPTR 0x34
|
||||
#define NVCFG_CFG_1 0x38 //unknown if used
|
||||
#define NVCFG_INTERRUPT 0x3c
|
||||
#define NVCFG_SUBSYSID2 0x40
|
||||
#define NVCFG_AGPREF 0x44
|
||||
#define NVCFG_AGPSTAT 0x48
|
||||
#define NVCFG_AGPCMD 0x4c
|
||||
#define NVCFG_ROMSHADOW 0x50
|
||||
#define NVCFG_VGA 0x54
|
||||
#define NVCFG_SCHRATCH 0x58
|
||||
#define NVCFG_CFG_10 0x5c
|
||||
#define NVCFG_CFG_11 0x60
|
||||
#define NVCFG_CFG_12 0x64
|
||||
#define NVCFG_CFG_13 0x68 //unknown if used
|
||||
#define NVCFG_CFG_14 0x6c //unknown if used
|
||||
#define NVCFG_CFG_15 0x70 //unknown if used
|
||||
#define NVCFG_CFG_16 0x74 //unknown if used
|
||||
#define NVCFG_PCIEREF 0x78
|
||||
#define NVCFG_PCIEDCAP 0x7c
|
||||
#define NVCFG_PCIEDCTST 0x80
|
||||
#define NVCFG_PCIELCAP 0x84
|
||||
#define NVCFG_PCIELCTST 0x88
|
||||
#define NVCFG_CFG_22 0x8c //unknown if used
|
||||
#define NVCFG_CFG_23 0x90 //unknown if used
|
||||
#define NVCFG_CFG_24 0x94 //unknown if used
|
||||
#define NVCFG_CFG_25 0x98 //unknown if used
|
||||
#define NVCFG_CFG_26 0x9c //unknown if used
|
||||
#define NVCFG_CFG_27 0xa0 //unknown if used
|
||||
#define NVCFG_CFG_28 0xa4 //unknown if used
|
||||
#define NVCFG_CFG_29 0xa8 //unknown if used
|
||||
#define NVCFG_CFG_30 0xac //unknown if used
|
||||
#define NVCFG_CFG_31 0xb0 //unknown if used
|
||||
#define NVCFG_CFG_32 0xb4 //unknown if used
|
||||
#define NVCFG_CFG_33 0xb8 //unknown if used
|
||||
#define NVCFG_CFG_34 0xbc //unknown if used
|
||||
#define NVCFG_CFG_35 0xc0 //unknown if used
|
||||
#define NVCFG_CFG_36 0xc4 //unknown if used
|
||||
#define NVCFG_CFG_37 0xc8 //unknown if used
|
||||
#define NVCFG_CFG_38 0xcc //unknown if used
|
||||
#define NVCFG_CFG_39 0xd0 //unknown if used
|
||||
#define NVCFG_CFG_40 0xd4 //unknown if used
|
||||
#define NVCFG_CFG_41 0xd8 //unknown if used
|
||||
#define NVCFG_CFG_42 0xdc //unknown if used
|
||||
#define NVCFG_CFG_43 0xe0 //unknown if used
|
||||
#define NVCFG_CFG_44 0xe4 //unknown if used
|
||||
#define NVCFG_CFG_45 0xe8 //unknown if used
|
||||
#define NVCFG_CFG_46 0xec //unknown if used
|
||||
#define NVCFG_CFG_47 0xf0 //unknown if used
|
||||
#define NVCFG_CFG_48 0xf4 //unknown if used
|
||||
#define NVCFG_CFG_49 0xf8 //unknown if used
|
||||
#define NVCFG_CFG_50 0xfc //unknown if used
|
||||
|
||||
/* used NV INT registers for vblank */
|
||||
#define NV32_MAIN_INTE 0x00000140
|
||||
#define NV32_CRTC_INTS 0x00600100
|
||||
#define NV32_CRTC_INTE 0x00600140
|
||||
#define NV32_CRTC2_INTS 0x00602100
|
||||
#define NV32_CRTC2_INTE 0x00602140
|
||||
|
||||
/* NV ACCeleration registers */
|
||||
/* engine initialisation registers */
|
||||
#define NVACC_ABS_UCLP_XMIN 0x0040053c
|
||||
#define NVACC_ABS_UCLP_YMIN 0x00400540
|
||||
#define NVACC_ABS_UCLP_XMAX 0x00400544
|
||||
#define NVACC_ABS_UCLP_YMAX 0x00400548
|
||||
#define NVACC_BETA_AND_VAL 0x00400608
|
||||
#define NVACC_FORMATS 0x00400618
|
||||
#define NVACC_OFFSET0 0x00400640
|
||||
#define NVACC_OFFSET1 0x00400644
|
||||
#define NVACC_OFFSET2 0x00400648
|
||||
#define NVACC_OFFSET3 0x0040064c
|
||||
#define NVACC_OFFSET4 0x00400650
|
||||
#define NVACC_OFFSET5 0x00400654
|
||||
#define NVACC_BBASE0 0x00400658
|
||||
#define NVACC_BBASE1 0x0040065c
|
||||
#define NVACC_BBASE2 0x00400660
|
||||
#define NVACC_BBASE3 0x00400664
|
||||
#define NVACC_NV10_BBASE4 0x00400668
|
||||
#define NVACC_NV10_BBASE5 0x0040066c
|
||||
#define NVACC_PITCH0 0x00400670
|
||||
#define NVACC_PITCH1 0x00400674
|
||||
#define NVACC_PITCH2 0x00400678
|
||||
#define NVACC_PITCH3 0x0040067c
|
||||
#define NVACC_PITCH4 0x00400680
|
||||
#define NVACC_BLIMIT0 0x00400684
|
||||
#define NVACC_BLIMIT1 0x00400688
|
||||
#define NVACC_BLIMIT2 0x0040068c
|
||||
#define NVACC_BLIMIT3 0x00400690
|
||||
#define NVACC_NV10_BLIMIT4 0x00400694
|
||||
#define NVACC_NV10_BLIMIT5 0x00400698
|
||||
#define NVACC_BPIXEL 0x00400724
|
||||
#define NVACC_NV20_OFFSET0 0x00400820
|
||||
#define NVACC_NV20_OFFSET1 0x00400824
|
||||
#define NVACC_NV20_OFFSET2 0x00400828
|
||||
#define NVACC_NV20_OFFSET3 0x0040082c
|
||||
#define NVACC_STRD_FMT 0x00400830
|
||||
#define NVACC_NV20_PITCH0 0x00400850
|
||||
#define NVACC_NV20_PITCH1 0x00400854
|
||||
#define NVACC_NV20_PITCH2 0x00400858
|
||||
#define NVACC_NV20_PITCH3 0x0040085c
|
||||
#define NVACC_NV20_BLIMIT6 0x00400864
|
||||
#define NVACC_NV20_BLIMIT7 0x00400868
|
||||
#define NVACC_NV20_BLIMIT8 0x0040086c
|
||||
#define NVACC_NV20_BLIMIT9 0x00400870
|
||||
#define NVACC_NV25_WHAT1 0x00400890
|
||||
|
||||
/* specials */
|
||||
#define NVACC_DEBUG0 0x00400080
|
||||
#define NVACC_DEBUG1 0x00400084
|
||||
#define NVACC_DEBUG2 0x00400088
|
||||
#define NVACC_DEBUG3 0x0040008c
|
||||
#define NVACC_NV10_DEBUG4 0x00400090
|
||||
#define NVACC_NV10_DEBUG5 0x00400094
|
||||
#define NVACC_NV20_WHAT5 0x00400098
|
||||
#define NVACC_NV20_WHAT1 0x0040009c
|
||||
#define NVACC_ACC_INTS 0x00400100
|
||||
#define NVACC_ACC_INTE 0x00400140
|
||||
#define NVACC_NV10_CTX_CTRL 0x00400144
|
||||
#define NVACC_NV4X_DMA_SRC 0x00400220
|
||||
#define NVACC_NV4X_WHAT1 0x0040032c
|
||||
#define NVACC_NV4X_WHAT2 0x00405000
|
||||
#define NVACC_NV25_WHAT0 0x00400610
|
||||
#define NVACC_STATUS 0x00400700
|
||||
#define NVACC_NV04_SURF_TYP 0x0040070c
|
||||
#define NVACC_NV10_SURF_TYP 0x00400710
|
||||
#define NVACC_NV04_ACC_STAT 0x00400710
|
||||
#define NVACC_NV10_ACC_STAT 0x00400714
|
||||
#define NVACC_FIFO_EN 0x00400720
|
||||
#define NVACC_RDI_INDEX 0x00400750
|
||||
#define NVACC_RDI_DATA 0x00400754
|
||||
#define NVACC_PAT_SHP 0x00400810
|
||||
#define NVACC_NV40P_WHAT0 0x00400820
|
||||
#define NVACC_NV40P_WHAT1 0x00400824
|
||||
#define NVACC_NV40P_WHAT2 0x00400828
|
||||
#define NVACC_NV40P_WHAT3 0x0040082c
|
||||
#define NVACC_NV40P_OFFSET0 0x00400840
|
||||
#define NVACC_NV40P_OFFSET1 0x00400844
|
||||
#define NVACC_NV44_WHAT2 0x00400860
|
||||
#define NVACC_NV44_WHAT3 0x00400864
|
||||
//fixme? (guessed)
|
||||
#define NVACC_NV40P_PITCH0 0x00400870
|
||||
#define NVACC_NV40P_PITCH1 0x00400874
|
||||
#define NVACC_NV20_WHAT2 0x00400880
|
||||
//end fixme.
|
||||
#define NVACC_NV40P_BLIMIT6 0x004008a0
|
||||
#define NVACC_NV40P_BLIMIT7 0x004008a4
|
||||
#define NVACC_NV20_WHAT0 0x00400900
|
||||
#define NVACC_NV41_WHAT0 0x00400d00
|
||||
#define NVACC_NV20_2_WHAT0 0x00406900
|
||||
#define NVACC_NV40_WHAT0 0x004009b0
|
||||
#define NVACC_NV40_WHAT1 0x004009b4
|
||||
#define NVACC_NV40_WHAT2 0x004009b8
|
||||
#define NVACC_NV40_WHAT3 0x004009bc
|
||||
#define NVACC_NV20_WHAT3 0x00400b80
|
||||
#define NVACC_NV20_WHAT4 0x00400b84
|
||||
#define NVACC_NV25_WHAT2 0x00400b88
|
||||
#define NVACC_WINCLIP_H_0 0x00400f00
|
||||
#define NVACC_WINCLIP_H_1 0x00400f04
|
||||
#define NVACC_WINCLIP_H_2 0x00400f08
|
||||
#define NVACC_WINCLIP_H_3 0x00400f0c
|
||||
#define NVACC_WINCLIP_H_4 0x00400f10
|
||||
#define NVACC_WINCLIP_H_5 0x00400f14
|
||||
#define NVACC_WINCLIP_H_6 0x00400f18
|
||||
#define NVACC_WINCLIP_H_7 0x00400f1c
|
||||
#define NVACC_WINCLIP_V_0 0x00400f20
|
||||
#define NVACC_WINCLIP_V_1 0x00400f24
|
||||
#define NVACC_WINCLIP_V_2 0x00400f28
|
||||
#define NVACC_WINCLIP_V_3 0x00400f2c
|
||||
#define NVACC_WINCLIP_V_4 0x00400f30
|
||||
#define NVACC_WINCLIP_V_5 0x00400f34
|
||||
#define NVACC_WINCLIP_V_6 0x00400f38
|
||||
#define NVACC_WINCLIP_V_7 0x00400f3c
|
||||
#define NVACC_NV10_XFMOD0 0x00400f40
|
||||
#define NVACC_NV10_XFMOD1 0x00400f44
|
||||
#define NVACC_GLOB_STAT_0 0x00400f48
|
||||
#define NVACC_GLOB_STAT_1 0x00400f4c
|
||||
#define NVACC_NV10_PIPEADR 0x00400f50
|
||||
#define NVACC_NV10_PIPEDAT 0x00400f54
|
||||
/* PGRAPH unknown registers */
|
||||
#define NVACC_PGWHAT_00 0x00400e00
|
||||
#define NVACC_PGWHAT_01 0x00400e04
|
||||
#define NVACC_PGWHAT_02 0x00400e08
|
||||
#define NVACC_PGWHAT_03 0x00400e0c
|
||||
#define NVACC_PGWHAT_04 0x00400e10
|
||||
#define NVACC_PGWHAT_05 0x00400e14
|
||||
#define NVACC_PGWHAT_06 0x00400e18
|
||||
#define NVACC_PGWHAT_07 0x00400e1c
|
||||
#define NVACC_PGWHAT_08 0x00400e20
|
||||
#define NVACC_PGWHAT_09 0x00400e24
|
||||
#define NVACC_PGWHAT_0A 0x00400e28
|
||||
#define NVACC_PGWHAT_0B 0x00400e2c
|
||||
#define NVACC_PGWHAT_0C 0x00400e30
|
||||
#define NVACC_PGWHAT_0D 0x00400e34
|
||||
#define NVACC_PGWHAT_0E 0x00400e38
|
||||
#define NVACC_PGWHAT_0F 0x00400e3c
|
||||
#define NVACC_PGWHAT_10 0x00400e40
|
||||
#define NVACC_PGWHAT_11 0x00400e44
|
||||
#define NVACC_PGWHAT_12 0x00400e48
|
||||
#define NVACC_PGWHAT_13 0x00400e4c
|
||||
#define NVACC_PGWHAT_14 0x00400e50
|
||||
#define NVACC_PGWHAT_15 0x00400e54
|
||||
#define NVACC_PGWHAT_16 0x00400e58
|
||||
#define NVACC_PGWHAT_17 0x00400e5c
|
||||
#define NVACC_PGWHAT_18 0x00400e60
|
||||
#define NVACC_PGWHAT_19 0x00400e64
|
||||
#define NVACC_PGWHAT_1A 0x00400e68
|
||||
#define NVACC_PGWHAT_1B 0x00400e6c
|
||||
#define NVACC_PGWHAT_1C 0x00400e70
|
||||
#define NVACC_PGWHAT_1D 0x00400e74
|
||||
#define NVACC_PGWHAT_1E 0x00400e78
|
||||
#define NVACC_PGWHAT_1F 0x00400e7c
|
||||
#define NVACC_PGWHAT_20 0x00400e80
|
||||
#define NVACC_PGWHAT_21 0x00400e84
|
||||
#define NVACC_PGWHAT_22 0x00400e88
|
||||
#define NVACC_PGWHAT_23 0x00400e8c
|
||||
#define NVACC_PGWHAT_24 0x00400e90
|
||||
#define NVACC_PGWHAT_25 0x00400e94
|
||||
#define NVACC_PGWHAT_26 0x00400e98
|
||||
#define NVACC_PGWHAT_27 0x00400e9c
|
||||
#define NVACC_PGWHAT_28 0x00400ea0
|
||||
#define NVACC_PGWHAT_29 0x00400ea4
|
||||
#define NVACC_PGWHAT_2A 0x00400ea8
|
||||
/* PGRAPH cache registers */
|
||||
#define NVACC_CACHE1_1 0x00400160
|
||||
#define NVACC_CACHE1_2 0x00400180
|
||||
#define NVACC_CACHE1_3 0x004001a0
|
||||
#define NVACC_CACHE1_4 0x004001c0
|
||||
#define NVACC_CACHE1_5 0x004001e0
|
||||
#define NVACC_CACHE2_1 0x00400164
|
||||
#define NVACC_CACHE2_2 0x00400184
|
||||
#define NVACC_CACHE2_3 0x004001a4
|
||||
#define NVACC_CACHE2_4 0x004001c4
|
||||
#define NVACC_CACHE2_5 0x004001e4
|
||||
#define NVACC_CACHE3_1 0x00400168
|
||||
#define NVACC_CACHE3_2 0x00400188
|
||||
#define NVACC_CACHE3_3 0x004001a8
|
||||
#define NVACC_CACHE3_4 0x004001c8
|
||||
#define NVACC_CACHE3_5 0x004001e8
|
||||
#define NVACC_CACHE4_1 0x0040016c
|
||||
#define NVACC_CACHE4_2 0x0040018c
|
||||
#define NVACC_CACHE4_3 0x004001ac
|
||||
#define NVACC_CACHE4_4 0x004001cc
|
||||
#define NVACC_CACHE4_5 0x004001ec
|
||||
#define NVACC_NV10_CACHE5_1 0x00400170
|
||||
#define NVACC_NV04_CTX_CTRL 0x00400170
|
||||
#define NVACC_CACHE5_2 0x00400190
|
||||
#define NVACC_CACHE5_3 0x004001b0
|
||||
#define NVACC_CACHE5_4 0x004001d0
|
||||
#define NVACC_CACHE5_5 0x004001f0
|
||||
#define NVACC_NV10_CACHE6_1 0x00400174
|
||||
#define NVACC_CACHE6_2 0x00400194
|
||||
#define NVACC_CACHE6_3 0x004001b4
|
||||
#define NVACC_CACHE6_4 0x004001d4
|
||||
#define NVACC_CACHE6_5 0x004001f4
|
||||
#define NVACC_NV10_CACHE7_1 0x00400178
|
||||
#define NVACC_CACHE7_2 0x00400198
|
||||
#define NVACC_CACHE7_3 0x004001b8
|
||||
#define NVACC_CACHE7_4 0x004001d8
|
||||
#define NVACC_CACHE7_5 0x004001f8
|
||||
#define NVACC_NV10_CACHE8_1 0x0040017c
|
||||
#define NVACC_CACHE8_2 0x0040019c
|
||||
#define NVACC_CACHE8_3 0x004001bc
|
||||
#define NVACC_CACHE8_4 0x004001dc
|
||||
#define NVACC_CACHE8_5 0x004001fc
|
||||
#define NVACC_NV10_CTX_SW1 0x0040014c
|
||||
#define NVACC_NV10_CTX_SW2 0x00400150
|
||||
#define NVACC_NV10_CTX_SW3 0x00400154
|
||||
#define NVACC_NV10_CTX_SW4 0x00400158
|
||||
#define NVACC_NV10_CTX_SW5 0x0040015c
|
||||
/* engine tile registers src */
|
||||
#define NVACC_NV10_FBTIL0AD 0x00100240
|
||||
#define NVACC_NV10_FBTIL0ED 0x00100244
|
||||
#define NVACC_NV10_FBTIL0PT 0x00100248
|
||||
#define NVACC_NV10_FBTIL0ST 0x0010024c
|
||||
#define NVACC_NV10_FBTIL1AD 0x00100250
|
||||
#define NVACC_NV10_FBTIL1ED 0x00100254
|
||||
#define NVACC_NV10_FBTIL1PT 0x00100258
|
||||
#define NVACC_NV10_FBTIL1ST 0x0010025c
|
||||
#define NVACC_NV10_FBTIL2AD 0x00100260
|
||||
#define NVACC_NV10_FBTIL2ED 0x00100264
|
||||
#define NVACC_NV10_FBTIL2PT 0x00100268
|
||||
#define NVACC_NV10_FBTIL2ST 0x0010026c
|
||||
#define NVACC_NV10_FBTIL3AD 0x00100270
|
||||
#define NVACC_NV10_FBTIL3ED 0x00100274
|
||||
#define NVACC_NV10_FBTIL3PT 0x00100278
|
||||
#define NVACC_NV10_FBTIL3ST 0x0010027c
|
||||
#define NVACC_NV10_FBTIL4AD 0x00100280
|
||||
#define NVACC_NV10_FBTIL4ED 0x00100284
|
||||
#define NVACC_NV10_FBTIL4PT 0x00100288
|
||||
#define NVACC_NV10_FBTIL4ST 0x0010028c
|
||||
#define NVACC_NV10_FBTIL5AD 0x00100290
|
||||
#define NVACC_NV10_FBTIL5ED 0x00100294
|
||||
#define NVACC_NV10_FBTIL5PT 0x00100298
|
||||
#define NVACC_NV10_FBTIL5ST 0x0010029c
|
||||
#define NVACC_NV10_FBTIL6AD 0x001002a0
|
||||
#define NVACC_NV10_FBTIL6ED 0x001002a4
|
||||
#define NVACC_NV10_FBTIL6PT 0x001002a8
|
||||
#define NVACC_NV10_FBTIL6ST 0x001002ac
|
||||
#define NVACC_NV10_FBTIL7AD 0x001002b0
|
||||
#define NVACC_NV10_FBTIL7ED 0x001002b4
|
||||
#define NVACC_NV10_FBTIL7PT 0x001002b8
|
||||
#define NVACC_NV10_FBTIL7ST 0x001002bc
|
||||
#define NVACC_NV41_FBTIL0AD 0x00100600
|
||||
#define NVACC_NV41_FBTIL0ED 0x00100604
|
||||
#define NVACC_NV41_FBTIL0PT 0x00100608
|
||||
#define NVACC_NV41_FBTIL0ST 0x0010060c
|
||||
#define NVACC_NV41_FBTIL1AD 0x00100610
|
||||
#define NVACC_NV41_FBTIL1ED 0x00100614
|
||||
#define NVACC_NV41_FBTIL1PT 0x00100618
|
||||
#define NVACC_NV41_FBTIL1ST 0x0010061c
|
||||
#define NVACC_NV41_FBTIL2AD 0x00100620
|
||||
#define NVACC_NV41_FBTIL2ED 0x00100624
|
||||
#define NVACC_NV41_FBTIL2PT 0x00100628
|
||||
#define NVACC_NV41_FBTIL2ST 0x0010062c
|
||||
#define NVACC_NV41_FBTIL3AD 0x00100630
|
||||
#define NVACC_NV41_FBTIL3ED 0x00100634
|
||||
#define NVACC_NV41_FBTIL3PT 0x00100638
|
||||
#define NVACC_NV41_FBTIL3ST 0x0010063c
|
||||
#define NVACC_NV41_FBTIL4AD 0x00100640
|
||||
#define NVACC_NV41_FBTIL4ED 0x00100644
|
||||
#define NVACC_NV41_FBTIL4PT 0x00100648
|
||||
#define NVACC_NV41_FBTIL4ST 0x0010064c
|
||||
#define NVACC_NV41_FBTIL5AD 0x00100650
|
||||
#define NVACC_NV41_FBTIL5ED 0x00100654
|
||||
#define NVACC_NV41_FBTIL5PT 0x00100658
|
||||
#define NVACC_NV41_FBTIL5ST 0x0010065c
|
||||
#define NVACC_NV41_FBTIL6AD 0x00100660
|
||||
#define NVACC_NV41_FBTIL6ED 0x00100664
|
||||
#define NVACC_NV41_FBTIL6PT 0x00100668
|
||||
#define NVACC_NV41_FBTIL6ST 0x0010066c
|
||||
#define NVACC_NV41_FBTIL7AD 0x00100670
|
||||
#define NVACC_NV41_FBTIL7ED 0x00100674
|
||||
#define NVACC_NV41_FBTIL7PT 0x00100678
|
||||
#define NVACC_NV41_FBTIL7ST 0x0010067c
|
||||
#define NVACC_NV41_FBTIL8AD 0x00100680
|
||||
#define NVACC_NV41_FBTIL8ED 0x00100684
|
||||
#define NVACC_NV41_FBTIL8PT 0x00100688
|
||||
#define NVACC_NV41_FBTIL8ST 0x0010068c
|
||||
#define NVACC_NV41_FBTIL9AD 0x00100690
|
||||
#define NVACC_NV41_FBTIL9ED 0x00100694
|
||||
#define NVACC_NV41_FBTIL9PT 0x00100698
|
||||
#define NVACC_NV41_FBTIL9ST 0x0010069c
|
||||
#define NVACC_NV41_FBTILAAD 0x001006a0
|
||||
#define NVACC_NV41_FBTILAED 0x001006a4
|
||||
#define NVACC_NV41_FBTILAPT 0x001006a8
|
||||
#define NVACC_NV41_FBTILAST 0x001006ac
|
||||
#define NVACC_NV41_FBTILBAD 0x001006b0
|
||||
#define NVACC_NV41_FBTILBED 0x001006b4
|
||||
#define NVACC_NV41_FBTILBPT 0x001006b8
|
||||
#define NVACC_NV41_FBTILBST 0x001006bc
|
||||
#define NVACC_G70_FBTILCAD 0x001006c0
|
||||
#define NVACC_G70_FBTILCED 0x001006c4
|
||||
#define NVACC_G70_FBTILCPT 0x001006c8
|
||||
#define NVACC_G70_FBTILCST 0x001006cc
|
||||
#define NVACC_G70_FBTILDAD 0x001006d0
|
||||
#define NVACC_G70_FBTILDED 0x001006d4
|
||||
#define NVACC_G70_FBTILDPT 0x001006d8
|
||||
#define NVACC_G70_FBTILDST 0x001006dc
|
||||
#define NVACC_G70_FBTILEAD 0x001006e0
|
||||
#define NVACC_G70_FBTILEED 0x001006e4
|
||||
#define NVACC_G70_FBTILEPT 0x001006e8
|
||||
#define NVACC_G70_FBTILEST 0x001006ec
|
||||
/* engine tile registers dst */
|
||||
#define NVACC_NV20_WHAT_T0 0x004009a4
|
||||
#define NVACC_NV20_WHAT_T1 0x004009a8
|
||||
#define NVACC_NV40_WHAT_T2 0x004069a4
|
||||
#define NVACC_NV40_WHAT_T3 0x004069a8
|
||||
#define NVACC_NV40P_WHAT_T0 0x004009f0
|
||||
#define NVACC_NV40P_WHAT_T1 0x004009f4
|
||||
#define NVACC_G70_WHAT_T0 0x00400df0
|
||||
#define NVACC_G70_WHAT_T1 0x00400df4
|
||||
#define NVACC_NV40P_WHAT_T2 0x004069f0
|
||||
#define NVACC_NV40P_WHAT_T3 0x004069f4
|
||||
#define NVACC_NV10_TIL0AD 0x00400b00
|
||||
#define NVACC_NV10_TIL0ED 0x00400b04
|
||||
#define NVACC_NV10_TIL0PT 0x00400b08
|
||||
#define NVACC_NV10_TIL0ST 0x00400b0c
|
||||
#define NVACC_NV10_TIL1AD 0x00400b10
|
||||
#define NVACC_NV10_TIL1ED 0x00400b14
|
||||
#define NVACC_NV10_TIL1PT 0x00400b18
|
||||
#define NVACC_NV10_TIL1ST 0x00400b1c
|
||||
#define NVACC_NV10_TIL2AD 0x00400b20
|
||||
#define NVACC_NV10_TIL2ED 0x00400b24
|
||||
#define NVACC_NV10_TIL2PT 0x00400b28
|
||||
#define NVACC_NV10_TIL2ST 0x00400b2c
|
||||
#define NVACC_NV10_TIL3AD 0x00400b30
|
||||
#define NVACC_NV10_TIL3ED 0x00400b34
|
||||
#define NVACC_NV10_TIL3PT 0x00400b38
|
||||
#define NVACC_NV10_TIL3ST 0x00400b3c
|
||||
#define NVACC_NV10_TIL4AD 0x00400b40
|
||||
#define NVACC_NV10_TIL4ED 0x00400b44
|
||||
#define NVACC_NV10_TIL4PT 0x00400b48
|
||||
#define NVACC_NV10_TIL4ST 0x00400b4c
|
||||
#define NVACC_NV10_TIL5AD 0x00400b50
|
||||
#define NVACC_NV10_TIL5ED 0x00400b54
|
||||
#define NVACC_NV10_TIL5PT 0x00400b58
|
||||
#define NVACC_NV10_TIL5ST 0x00400b5c
|
||||
#define NVACC_NV10_TIL6AD 0x00400b60
|
||||
#define NVACC_NV10_TIL6ED 0x00400b64
|
||||
#define NVACC_NV10_TIL6PT 0x00400b68
|
||||
#define NVACC_NV10_TIL6ST 0x00400b6c
|
||||
#define NVACC_NV10_TIL7AD 0x00400b70
|
||||
#define NVACC_NV10_TIL7ED 0x00400b74
|
||||
#define NVACC_NV10_TIL7PT 0x00400b78
|
||||
#define NVACC_NV10_TIL7ST 0x00400b7c
|
||||
/* cache setup registers */
|
||||
#define NVACC_PF_INTSTAT 0x00002100
|
||||
#define NVACC_PF_INTEN 0x00002140
|
||||
#define NVACC_PF_RAMHT 0x00002210
|
||||
#define NVACC_PF_RAMFC 0x00002214
|
||||
#define NVACC_PF_RAMRO 0x00002218
|
||||
#define NVACC_PF_CACHES 0x00002500
|
||||
#define NVACC_PF_MODE 0x00002504
|
||||
#define NVACC_PF_SIZE 0x0000250c
|
||||
#define NVACC_PF_CACH0_PSH0 0x00003000
|
||||
#define NVACC_PF_CACH0_PUL0 0x00003050
|
||||
#define NVACC_PF_CACH0_PUL1 0x00003054
|
||||
#define NVACC_PF_CACH1_PSH0 0x00003200
|
||||
#define NVACC_PF_CACH1_PSH1 0x00003204
|
||||
#define NVACC_PF_CACH1_DMAS 0x00003220
|
||||
#define NVACC_PF_CACH1_DMAF 0x00003224
|
||||
#define NVACC_PF_CACH1_DMAI 0x0000322c
|
||||
#define NVACC_PF_CACH1_DMAC 0x00003230
|
||||
#define NVACC_PF_CACH1_DMAP 0x00003240
|
||||
#define NVACC_PF_CACH1_DMAG 0x00003244
|
||||
#define NVACC_PF_CACH1_PUL0 0x00003250
|
||||
#define NVACC_PF_CACH1_PUL1 0x00003254
|
||||
#define NVACC_PF_CACH1_HASH 0x00003258
|
||||
#define NVACC_PF_CACH1_ENG 0x00003280
|
||||
/* Ptimer registers */
|
||||
#define NVACC_PT_INTSTAT 0x00009100
|
||||
#define NVACC_PT_INTEN 0x00009140
|
||||
#define NVACC_PT_NUMERATOR 0x00009200
|
||||
#define NVACC_PT_DENOMINATR 0x00009210
|
||||
/* used PRAMIN registers */
|
||||
#define NVACC_PR_CTX0_R 0x00711400
|
||||
#define NVACC_PR_CTX1_R 0x00711404
|
||||
#define NVACC_PR_CTX2_R 0x00711408
|
||||
#define NVACC_PR_CTX3_R 0x0071140c
|
||||
#define NVACC_PR_CTX0_0 0x00711420
|
||||
#define NVACC_PR_CTX1_0 0x00711424
|
||||
#define NVACC_PR_CTX2_0 0x00711428
|
||||
#define NVACC_PR_CTX3_0 0x0071142c
|
||||
#define NVACC_PR_CTX0_1 0x00711430
|
||||
#define NVACC_PR_CTX1_1 0x00711434
|
||||
#define NVACC_PR_CTX2_1 0x00711438
|
||||
#define NVACC_PR_CTX3_1 0x0071143c
|
||||
#define NVACC_PR_CTX0_2 0x00711440
|
||||
#define NVACC_PR_CTX1_2 0x00711444
|
||||
#define NVACC_PR_CTX2_2 0x00711448
|
||||
#define NVACC_PR_CTX3_2 0x0071144c
|
||||
#define NVACC_PR_CTX0_3 0x00711450
|
||||
#define NVACC_PR_CTX1_3 0x00711454
|
||||
#define NVACC_PR_CTX2_3 0x00711458
|
||||
#define NVACC_PR_CTX3_3 0x0071145c
|
||||
#define NVACC_PR_CTX0_4 0x00711460
|
||||
#define NVACC_PR_CTX1_4 0x00711464
|
||||
#define NVACC_PR_CTX2_4 0x00711468
|
||||
#define NVACC_PR_CTX3_4 0x0071146c
|
||||
#define NVACC_PR_CTX0_5 0x00711470
|
||||
#define NVACC_PR_CTX1_5 0x00711474
|
||||
#define NVACC_PR_CTX2_5 0x00711478
|
||||
#define NVACC_PR_CTX3_5 0x0071147c
|
||||
#define NVACC_PR_CTX0_6 0x00711480
|
||||
#define NVACC_PR_CTX1_6 0x00711484
|
||||
#define NVACC_PR_CTX2_6 0x00711488
|
||||
#define NVACC_PR_CTX3_6 0x0071148c
|
||||
#define NVACC_PR_CTX0_7 0x00711490
|
||||
#define NVACC_PR_CTX1_7 0x00711494
|
||||
#define NVACC_PR_CTX2_7 0x00711498
|
||||
#define NVACC_PR_CTX3_7 0x0071149c
|
||||
#define NVACC_PR_CTX0_8 0x007114a0
|
||||
#define NVACC_PR_CTX1_8 0x007114a4
|
||||
#define NVACC_PR_CTX2_8 0x007114a8
|
||||
#define NVACC_PR_CTX3_8 0x007114ac
|
||||
#define NVACC_PR_CTX0_9 0x007114b0
|
||||
#define NVACC_PR_CTX1_9 0x007114b4
|
||||
#define NVACC_PR_CTX2_9 0x007114b8
|
||||
#define NVACC_PR_CTX3_9 0x007114bc
|
||||
#define NVACC_PR_CTX0_A 0x007114c0
|
||||
#define NVACC_PR_CTX1_A 0x007114c4 /* not used */
|
||||
#define NVACC_PR_CTX2_A 0x007114c8
|
||||
#define NVACC_PR_CTX3_A 0x007114cc
|
||||
#define NVACC_PR_CTX0_B 0x007114d0
|
||||
#define NVACC_PR_CTX1_B 0x007114d4
|
||||
#define NVACC_PR_CTX2_B 0x007114d8
|
||||
#define NVACC_PR_CTX3_B 0x007114dc
|
||||
#define NVACC_PR_CTX0_C 0x007114e0
|
||||
#define NVACC_PR_CTX1_C 0x007114e4
|
||||
#define NVACC_PR_CTX2_C 0x007114e8
|
||||
#define NVACC_PR_CTX3_C 0x007114ec
|
||||
#define NVACC_PR_CTX0_D 0x007114f0
|
||||
#define NVACC_PR_CTX1_D 0x007114f4
|
||||
#define NVACC_PR_CTX2_D 0x007114f8
|
||||
#define NVACC_PR_CTX3_D 0x007114fc
|
||||
#define NVACC_PR_CTX0_E 0x00711500
|
||||
#define NVACC_PR_CTX1_E 0x00711504
|
||||
#define NVACC_PR_CTX2_E 0x00711508
|
||||
#define NVACC_PR_CTX3_E 0x0071150c
|
||||
#define NVACC_PR_CTX0_F 0x00711510
|
||||
#define NVACC_PR_CTX1_F 0x00711514
|
||||
#define NVACC_PR_CTX2_F 0x00711518
|
||||
#define NVACC_PR_CTX3_F 0x0071151c
|
||||
#define NVACC_PR_CTX0_10 0x00711520
|
||||
#define NVACC_PR_CTX1_10 0x00711524
|
||||
#define NVACC_PR_CTX2_10 0x00711528
|
||||
#define NVACC_PR_CTX3_10 0x0071152c
|
||||
/* used RAMHT registers (hash-table) */
|
||||
#define NVACC_HT_HANDL_00 0x00710000
|
||||
#define NVACC_HT_VALUE_00 0x00710004
|
||||
#define NVACC_HT_HANDL_01 0x00710008
|
||||
#define NVACC_HT_VALUE_01 0x0071000c
|
||||
#define NVACC_HT_HANDL_02 0x00710010
|
||||
#define NVACC_HT_VALUE_02 0x00710014
|
||||
#define NVACC_HT_HANDL_03 0x00710018
|
||||
#define NVACC_HT_VALUE_03 0x0071001c
|
||||
#define NVACC_HT_HANDL_04 0x00710020
|
||||
#define NVACC_HT_VALUE_04 0x00710024
|
||||
#define NVACC_HT_HANDL_05 0x00710028
|
||||
#define NVACC_HT_VALUE_05 0x0071002c
|
||||
#define NVACC_HT_HANDL_06 0x00710030
|
||||
#define NVACC_HT_VALUE_06 0x00710034
|
||||
#define NVACC_HT_HANDL_10 0x00710080
|
||||
#define NVACC_HT_VALUE_10 0x00710084
|
||||
#define NVACC_HT_HANDL_11 0x00710088
|
||||
#define NVACC_HT_VALUE_11 0x0071008c
|
||||
#define NVACC_HT_HANDL_12 0x00710090
|
||||
#define NVACC_HT_VALUE_12 0x00710094
|
||||
#define NVACC_HT_HANDL_13 0x00710098
|
||||
#define NVACC_HT_VALUE_13 0x0071009c
|
||||
#define NVACC_HT_HANDL_14 0x007100a0
|
||||
#define NVACC_HT_VALUE_14 0x007100a4
|
||||
#define NVACC_HT_HANDL_15 0x007100a8
|
||||
#define NVACC_HT_VALUE_15 0x007100ac
|
||||
#define NVACC_HT_HANDL_16 0x007100b0
|
||||
#define NVACC_HT_VALUE_16 0x007100b4
|
||||
#define NVACC_HT_HANDL_17 0x007100b8
|
||||
#define NVACC_HT_VALUE_17 0x007100bc
|
||||
|
||||
/* acc engine fifo setup registers (for function_register 'mappings') */
|
||||
#define NVACC_FIFO 0x00800000
|
||||
#define NVACC_FIFO_CH0 0x00800000
|
||||
#define NVACC_FIFO_CH1 0x00802000
|
||||
#define NVACC_FIFO_CH2 0x00804000
|
||||
#define NVACC_FIFO_CH3 0x00806000
|
||||
#define NVACC_FIFO_CH4 0x00808000
|
||||
#define NVACC_FIFO_CH5 0x0080a000
|
||||
#define NVACC_FIFO_CH6 0x0080c000
|
||||
#define NVACC_FIFO_CH7 0x0080e000
|
||||
|
||||
/* Nvidia PCI direct registers */
|
||||
#define NV32_PWRUPCTRL 0x00000200
|
||||
#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!!
|
||||
#define NV8_MISCW 0x000c03c2
|
||||
#define NV8_MISCR 0x000c03cc
|
||||
#define NV8_VSE2 0x000c03c3
|
||||
#define NV8_SEQIND 0x000c03c4
|
||||
#define NV16_SEQIND 0x000c03c4
|
||||
#define NV8_SEQDAT 0x000c03c5
|
||||
#define NV8_GRPHIND 0x000c03ce
|
||||
#define NV16_GRPHIND 0x000c03ce
|
||||
#define NV8_GRPHDAT 0x000c03cf
|
||||
|
||||
/* bootstrap info registers */
|
||||
#define NV32_NV4STRAPINFO 0x00100000
|
||||
#define NV32_PFB_CONFIG_0 0x00100200
|
||||
#define NV32_PFB_CONFIG_1 0x00100204
|
||||
#define NV32_NV10STRAPINFO 0x0010020c
|
||||
#define NV32_FB_MRS1 0x001002c0
|
||||
#define NV32_FB_MRS2 0x001002c8
|
||||
#define NV32_PFB_CLS_PAGE2 0x0010033c
|
||||
#define NV32_NVSTRAPINFO2 0x00101000
|
||||
|
||||
/* registers needed for 'coldstart' */
|
||||
#define NV32_PFB_DEBUG_0 0x00100080
|
||||
#define NV32_PFB_REFCTRL 0x00100210
|
||||
#define NV32_COREPLL 0x00680500
|
||||
#define NV32_MEMPLL 0x00680504
|
||||
#define NV32_PLL_CTRL 0x00680510
|
||||
#define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */
|
||||
#define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */
|
||||
#define NV32_CONFIG 0x00600804
|
||||
|
||||
/* primary head */
|
||||
#define NV8_ATTRINDW 0x006013c0
|
||||
#define NV8_ATTRDATW 0x006013c0
|
||||
#define NV8_ATTRDATR 0x006013c1
|
||||
#define NV8_CRTCIND 0x006013d4
|
||||
#define NV16_CRTCIND 0x006013d4
|
||||
#define NV8_CRTCDAT 0x006013d5
|
||||
#define NV8_INSTAT1 0x006013da
|
||||
#define NV32_NV10FBSTADD32 0x00600800
|
||||
#define NV32_RASTER 0x00600808
|
||||
#define NV32_NV10CURADD32 0x0060080c
|
||||
#define NV32_CURCONF 0x00600810
|
||||
#define NV32_PANEL_PWR 0x0060081c
|
||||
#define NV32_FUNCSEL 0x00600860
|
||||
|
||||
/* secondary head */
|
||||
#define NV8_ATTR2INDW 0x006033c0
|
||||
#define NV8_ATTR2DATW 0x006033c0
|
||||
#define NV8_ATTR2DATR 0x006033c1
|
||||
#define NV8_CRTC2IND 0x006033d4
|
||||
#define NV16_CRTC2IND 0x006033d4
|
||||
#define NV8_CRTC2DAT 0x006033d5
|
||||
#define NV8_2INSTAT1 0x006033da//verify!!!
|
||||
#define NV32_NV10FB2STADD32 0x00602800
|
||||
#define NV32_RASTER2 0x00602808
|
||||
#define NV32_NV10CUR2ADD32 0x0060280c
|
||||
#define NV32_2CURCONF 0x00602810
|
||||
#define NV32_2PANEL_PWR 0x0060281c//verify!!!
|
||||
#define NV32_2FUNCSEL 0x00602860
|
||||
|
||||
/* both heads */
|
||||
#define NVACC_NV11_CRTC_LO 0x00600830
|
||||
#define NVACC_NV11_CRTC_HI 0x00600834
|
||||
|
||||
/* Nvidia DAC direct registers (standard VGA palette RAM registers) */
|
||||
/* primary head */
|
||||
#define NV8_PALMASK 0x006813c6
|
||||
#define NV8_PALINDR 0x006813c7
|
||||
#define NV8_PALINDW 0x006813c8
|
||||
#define NV8_PALDATA 0x006813c9
|
||||
/* secondary head */
|
||||
#define NV8_PAL2MASK 0x006833c6
|
||||
#define NV8_PAL2INDR 0x006833c7
|
||||
#define NV8_PAL2INDW 0x006833c8
|
||||
#define NV8_PAL2DATA 0x006833c9
|
||||
|
||||
/* Nvidia PCI direct DAC registers (32bit) */
|
||||
/* primary head */
|
||||
#define NVDAC_CURPOS 0x00680300
|
||||
#define NVDAC_NV10_CURSYNC 0x00680404
|
||||
#define NVDAC_PIXPLLC 0x00680508
|
||||
#define NVDAC_PLLSEL 0x0068050c
|
||||
#define NVDAC_OUTPUT 0x0068052c
|
||||
#define NVDAC_PIXPLLC2 0x00680578
|
||||
#define NVDAC_GENCTRL 0x00680600
|
||||
#define NVDAC_TSTCTRL 0x00680608
|
||||
#define NVDAC_TSTDATA 0x00680610
|
||||
#define NVDAC_TV_SETUP 0x00680700
|
||||
/* (flatpanel registers: confirmed for TNT2 and up) */
|
||||
#define NVDAC_FP_VDISPEND 0x00680800
|
||||
#define NVDAC_FP_VTOTAL 0x00680804
|
||||
#define NVDAC_FP_VCRTC 0x00680808
|
||||
#define NVDAC_FP_VSYNC_S 0x0068080c
|
||||
#define NVDAC_FP_VSYNC_E 0x00680810
|
||||
#define NVDAC_FP_VVALID_S 0x00680814
|
||||
#define NVDAC_FP_VVALID_E 0x00680818
|
||||
#define NVDAC_FP_HDISPEND 0x00680820
|
||||
#define NVDAC_FP_HTOTAL 0x00680824
|
||||
#define NVDAC_FP_HCRTC 0x00680828
|
||||
#define NVDAC_FP_HSYNC_S 0x0068082c
|
||||
#define NVDAC_FP_HSYNC_E 0x00680830
|
||||
#define NVDAC_FP_HVALID_S 0x00680834
|
||||
#define NVDAC_FP_HVALID_E 0x00680838
|
||||
#define NVDAC_FP_CHKSUM 0x00680840
|
||||
#define NVDAC_FP_TST_CTRL 0x00680844
|
||||
#define NVDAC_FP_TG_CTRL 0x00680848
|
||||
#define NVDAC_FP_DEBUG0 0x00680880
|
||||
#define NVDAC_FP_DEBUG1 0x00680884
|
||||
#define NVDAC_FP_DEBUG2 0x00680888
|
||||
#define NVDAC_FP_DEBUG3 0x0068088c
|
||||
#define NVDAC_FP_TMDS_CTRL 0x006808b0
|
||||
#define NVDAC_FP_TMDS_DATA 0x006808b4
|
||||
/* secondary head */
|
||||
#define NVDAC2_CURPOS 0x00682300
|
||||
#define NVDAC2_NV10_CURSYNC 0x00682404
|
||||
#define NVDAC2_PIXPLLC 0x00680520
|
||||
#define NVDAC2_OUTPUT 0x0068252c
|
||||
#define NVDAC2_PIXPLLC2 0x0068057c
|
||||
#define NVDAC2_GENCTRL 0x00682600
|
||||
#define NVDAC2_TSTCTRL 0x00682608
|
||||
#define NVDAC2_TV_SETUP 0x00682700
|
||||
/* (flatpanel registers) */
|
||||
#define NVDAC2_FP_VDISPEND 0x00682800
|
||||
#define NVDAC2_FP_VTOTAL 0x00682804
|
||||
#define NVDAC2_FP_VCRTC 0x00682808
|
||||
#define NVDAC2_FP_VSYNC_S 0x0068280c
|
||||
#define NVDAC2_FP_VSYNC_E 0x00682810
|
||||
#define NVDAC2_FP_VVALID_S 0x00682814
|
||||
#define NVDAC2_FP_VVALID_E 0x00682818
|
||||
#define NVDAC2_FP_HDISPEND 0x00682820
|
||||
#define NVDAC2_FP_HTOTAL 0x00682824
|
||||
#define NVDAC2_FP_HCRTC 0x00682828
|
||||
#define NVDAC2_FP_HSYNC_S 0x0068282c
|
||||
#define NVDAC2_FP_HSYNC_E 0x00682830
|
||||
#define NVDAC2_FP_HVALID_S 0x00682834
|
||||
#define NVDAC2_FP_HVALID_E 0x00682838
|
||||
#define NVDAC2_FP_CHKSUM 0x00682840
|
||||
#define NVDAC2_FP_TST_CTRL 0x00682844
|
||||
#define NVDAC2_FP_TG_CTRL 0x00682848
|
||||
#define NVDAC2_FP_DEBUG0 0x00682880
|
||||
#define NVDAC2_FP_DEBUG1 0x00682884
|
||||
#define NVDAC2_FP_DEBUG2 0x00682888
|
||||
#define NVDAC2_FP_DEBUG3 0x0068288c
|
||||
#define NVDAC2_FP_TMDS_CTRL 0x006828b0//verify!!!
|
||||
#define NVDAC2_FP_TMDS_DATA 0x006828b4//verify!!!
|
||||
|
||||
/* Nvidia CRTC indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVCRTCX_HTOTAL 0x00
|
||||
#define NVCRTCX_HDISPE 0x01
|
||||
#define NVCRTCX_HBLANKS 0x02
|
||||
#define NVCRTCX_HBLANKE 0x03
|
||||
#define NVCRTCX_HSYNCS 0x04
|
||||
#define NVCRTCX_HSYNCE 0x05
|
||||
#define NVCRTCX_VTOTAL 0x06
|
||||
#define NVCRTCX_OVERFLOW 0x07
|
||||
#define NVCRTCX_PRROWSCN 0x08
|
||||
#define NVCRTCX_MAXSCLIN 0x09
|
||||
#define NVCRTCX_VGACURCTRL 0x0a
|
||||
#define NVCRTCX_FBSTADDH 0x0c
|
||||
#define NVCRTCX_FBSTADDL 0x0d
|
||||
#define NVCRTCX_VSYNCS 0x10
|
||||
#define NVCRTCX_VSYNCE 0x11
|
||||
#define NVCRTCX_VDISPE 0x12
|
||||
#define NVCRTCX_PITCHL 0x13
|
||||
#define NVCRTCX_VBLANKS 0x15
|
||||
#define NVCRTCX_VBLANKE 0x16
|
||||
#define NVCRTCX_MODECTL 0x17
|
||||
#define NVCRTCX_LINECOMP 0x18
|
||||
/* Nvidia specific registers: */
|
||||
#define NVCRTCX_REPAINT0 0x19
|
||||
#define NVCRTCX_REPAINT1 0x1a
|
||||
#define NVCRTCX_FIFO 0x1b
|
||||
#define NVCRTCX_LOCK 0x1f
|
||||
#define NVCRTCX_FIFO_LWM 0x20
|
||||
#define NVCRTCX_BUFFER 0x21
|
||||
#define NVCRTCX_LSR 0x25
|
||||
#define NVCRTCX_PIXEL 0x28
|
||||
#define NVCRTCX_HEB 0x2d
|
||||
#define NVCRTCX_CURCTL2 0x2f
|
||||
#define NVCRTCX_CURCTL1 0x30
|
||||
#define NVCRTCX_CURCTL0 0x31
|
||||
#define NVCRTCX_LCD 0x33
|
||||
#define NVCRTCX_RD_I2CBUS_1 0x36
|
||||
#define NVCRTCX_WR_I2CBUS_1 0x37
|
||||
#define NVCRTCX_RMA 0x38
|
||||
#define NVCRTCX_INTERLACE 0x39
|
||||
#define NVCRTCX_TREG 0x3d
|
||||
#define NVCRTCX_RD_I2CBUS_0 0x3e
|
||||
#define NVCRTCX_WR_I2CBUS_0 0x3f
|
||||
#define NVCRTCX_EXTRA 0x41
|
||||
#define NVCRTCX_OWNER 0x44
|
||||
#define NVCRTCX_FP_HTIMING 0x53
|
||||
#define NVCRTCX_FP_VTIMING 0x54
|
||||
#define NVCRTCX_0x59 0x59
|
||||
#define NVCRTCX_0x9f 0x9f
|
||||
|
||||
/* Nvidia ATTRIBUTE indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVATBX_MODECTL 0x10
|
||||
#define NVATBX_OSCANCOLOR 0x11
|
||||
#define NVATBX_COLPLANE_EN 0x12
|
||||
#define NVATBX_HORPIXPAN 0x13
|
||||
#define NVATBX_COLSEL 0x14
|
||||
|
||||
/* Nvidia SEQUENCER indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVSEQX_RESET 0x00
|
||||
#define NVSEQX_CLKMODE 0x01
|
||||
#define NVSEQX_MEMMODE 0x04
|
||||
|
||||
/* Nvidia GRAPHICS indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVGRPHX_ENSETRESET 0x01
|
||||
#define NVGRPHX_DATAROTATE 0x03
|
||||
#define NVGRPHX_READMAPSEL 0x04
|
||||
#define NVGRPHX_MODE 0x05
|
||||
#define NVGRPHX_MISC 0x06
|
||||
#define NVGRPHX_BITMASK 0x08
|
||||
|
||||
/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */
|
||||
#define NVBES_NV04_INTE 0x00680140
|
||||
#define NVBES_NV04_ISCALVH 0x00680200
|
||||
#define NVBES_NV04_CTRL_V 0x00680204
|
||||
#define NVBES_NV04_CTRL_H 0x00680208
|
||||
#define NVBES_NV04_OE_STATE 0x00680224
|
||||
#define NVBES_NV04_SU_STATE 0x00680228
|
||||
#define NVBES_NV04_RM_STATE 0x0068022c
|
||||
#define NVBES_NV04_DSTREF 0x00680230
|
||||
#define NVBES_NV04_DSTSIZE 0x00680234
|
||||
#define NVBES_NV04_FIFOTHRS 0x00680238
|
||||
#define NVBES_NV04_FIFOBURL 0x0068023c
|
||||
#define NVBES_NV04_COLKEY 0x00680240
|
||||
#define NVBES_NV04_GENCTRL 0x00680244
|
||||
#define NVBES_NV04_RED_AMP 0x00680280
|
||||
#define NVBES_NV04_GRN_AMP 0x00680284
|
||||
#define NVBES_NV04_BLU_AMP 0x00680288
|
||||
#define NVBES_NV04_SAT 0x0068028c
|
||||
/* buffer 0 */
|
||||
#define NVBES_NV04_0BUFADR 0x0068020c
|
||||
#define NVBES_NV04_0SRCPTCH 0x00680214
|
||||
#define NVBES_NV04_0OFFSET 0x0068021c
|
||||
/* buffer 1 */
|
||||
#define NVBES_NV04_1BUFADR 0x00680210
|
||||
#define NVBES_NV04_1SRCPTCH 0x00680218
|
||||
#define NVBES_NV04_1OFFSET 0x00680220
|
||||
|
||||
/* Nvidia BES (Back End Scaler) registers (>= NV10) */
|
||||
#define NVBES_NV10_INTE 0x00008140
|
||||
#define NVBES_NV10_BUFSEL 0x00008700
|
||||
#define NVBES_NV10_GENCTRL 0x00008704
|
||||
#define NVBES_NV10_COLKEY 0x00008b00
|
||||
/* buffer 0 */
|
||||
#define NVBES_NV10_0BUFADR 0x00008900
|
||||
#define NVBES_NV10_0MEMMASK 0x00008908
|
||||
#define NVBES_NV10_0BRICON 0x00008910
|
||||
#define NVBES_NV10_0SAT 0x00008918
|
||||
#define NVBES_NV10_0OFFSET 0x00008920
|
||||
#define NVBES_NV10_0SRCSIZE 0x00008928
|
||||
#define NVBES_NV10_0SRCREF 0x00008930
|
||||
#define NVBES_NV10_0ISCALH 0x00008938
|
||||
#define NVBES_NV10_0ISCALV 0x00008940
|
||||
#define NVBES_NV10_0DSTREF 0x00008948
|
||||
#define NVBES_NV10_0DSTSIZE 0x00008950
|
||||
#define NVBES_NV10_0SRCPTCH 0x00008958
|
||||
/* buffer 1 */
|
||||
#define NVBES_NV10_1BUFADR 0x00008904
|
||||
#define NVBES_NV10_1MEMMASK 0x0000890c
|
||||
#define NVBES_NV10_1BRICON 0x00008914
|
||||
#define NVBES_NV10_1SAT 0x0000891c
|
||||
#define NVBES_NV10_1OFFSET 0x00008924
|
||||
#define NVBES_NV10_1SRCSIZE 0x0000892c
|
||||
#define NVBES_NV10_1SRCREF 0x00008934
|
||||
#define NVBES_NV10_1ISCALH 0x0000893c
|
||||
#define NVBES_NV10_1ISCALV 0x00008944
|
||||
#define NVBES_NV10_1DSTREF 0x0000894c
|
||||
#define NVBES_NV10_1DSTSIZE 0x00008954
|
||||
#define NVBES_NV10_1SRCPTCH 0x0000895c
|
||||
/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
|
||||
#define NVBES_DEC_GENCTRL 0x00001588
|
||||
/* LVDS panel related registers */
|
||||
#define NV32_LVDS_PWR 0x0000130c
|
||||
/* unknown registers */
|
||||
#define NV32_NV4X_WHAT0 0x00001540
|
||||
#define NV32_NV44_WHAT10 0x00001700
|
||||
#define NV32_NV44_WHAT11 0x00001704
|
||||
#define NV32_NV44_WHAT12 0x00001708
|
||||
#define NV32_NV44_WHAT13 0x0000170c
|
||||
|
||||
/* Macros for convenient accesses to the NV chips */
|
||||
#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
|
||||
#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
|
||||
#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
|
||||
|
||||
/* read and write to PCI config space */
|
||||
#define CFGR(A) (*(nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), &nv_pci_access.value))
|
||||
#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access)))
|
||||
|
||||
/* read and write from ISA I/O space */
|
||||
#define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B, nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access)))
|
||||
#define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B, nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access)))
|
||||
#define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data)
|
||||
#define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data)
|
||||
|
||||
/* read and write from the dac registers */
|
||||
#define DACR(A) (NV_REG32(NVDAC_##A))
|
||||
#define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
|
||||
|
||||
/* read and write from the secondary dac registers */
|
||||
#define DAC2R(A) (NV_REG32(NVDAC2_##A))
|
||||
#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)
|
||||
|
||||
/* read and write from the backend scaler registers */
|
||||
#define BESR(A) (NV_REG32(NVBES_##A))
|
||||
#define BESW(A,B) (NV_REG32(NVBES_##A)=B)
|
||||
|
||||
/* read and write from CRTC indexed registers */
|
||||
#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8)))
|
||||
#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT))
|
||||
|
||||
/* read and write from second CRTC indexed registers */
|
||||
#define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8)))
|
||||
#define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT))
|
||||
|
||||
/* read and write from ATTRIBUTE indexed registers */
|
||||
#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B))
|
||||
#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR))
|
||||
|
||||
/* read and write from ATTRIBUTE indexed registers */
|
||||
#define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B))
|
||||
#define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR))
|
||||
|
||||
/* read and write from SEQUENCER indexed registers */
|
||||
#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8)))
|
||||
#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT))
|
||||
|
||||
/* read and write from PCI GRAPHICS indexed registers */
|
||||
#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8)))
|
||||
#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT))
|
||||
|
||||
/* read and write from the acceleration engine registers */
|
||||
#define ACCR(A) (NV_REG32(NVACC_##A))
|
||||
#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
|
||||
Reference in New Issue
Block a user