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The DMA_PUT register is write-only on some cards (confirmed NV11).

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10846 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-01-18 18:37:27 +00:00
parent d1a21786b1
commit 18b2b9dab7
1 changed files with 3 additions and 2 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+3 -2
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@@ -777,6 +777,8 @@ static void nv_start_dma(void)
/* note: /* note:
* the actual FIFO channel that gets activated does not really matter: * the actual FIFO channel that gets activated does not really matter:
* all FIFO fill-level info actually points at the same registers. */ * all FIFO fill-level info actually points at the same registers. */
/* note also:
* NV_GENERAL_DMAPUT is a write-only register on some cards (confirmed NV11). */
NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT + NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT +
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]) = si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]) =
(si->engine.dma.put << 2); (si->engine.dma.put << 2);
@@ -786,8 +788,7 @@ for (dummy = 0; dummy < 2; dummy++)
{ {
LOG(4,("ACC_DMA: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + LOG(4,("ACC_DMA: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET +
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]))); si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])));
LOG(4,("ACC_DMA: put $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT + LOG(4,("ACC_DMA: put $%08x\n", si->engine.dma.put));
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])));
} }
} }