i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Made it possible to disable PCI module debug output.

Browse Source 
This speeds up boottime with serial debug enabled.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12080 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2005-03-27 17:00:20 +00:00
parent 11356b94e3
commit 1e29ee2b74
4 changed files with 56 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/kernel/bus_managers/pci/pci.cpp
+6 -6
View File
@@ -72,7 +72,7 @@ PCI::GetNthPciInfo(PCIBus *bus, long *curindex, long wantindex, pci_info *outInf
void
PCI::DiscoverBus(PCIBus *bus)
{
dprintf("PCI: DiscoverBus, bus %u\n", bus->bus);
TRACE(("PCI: DiscoverBus, bus %u\n", bus->bus));
for (int dev = 0; dev < gMaxBusDevices; dev++) {
uint16 vendor_id = pci_read_config(bus->bus, dev, 0, PCI_vendor_id, 2);
@@ -90,7 +90,7 @@ PCI::DiscoverBus(PCIBus *bus)
void
PCI::DiscoverDevice(PCIBus *bus, uint8 dev, uint8 func)
{
dprintf("PCI: DiscoverDevice, bus %u, dev %u, func %u\n", bus->bus, dev, func);
TRACE(("PCI: DiscoverDevice, bus %u, dev %u, func %u\n", bus->bus, dev, func));
uint16 device_id = pci_read_config(bus->bus, dev, func, PCI_device_id, 2);
if (device_id == 0xffff)
@@ -126,7 +126,7 @@ PCI::CreateBus(PCIDev *parent, uint8 bus)
PCIDev *
PCI::CreateDevice(PCIBus *parent, uint8 dev, uint8 func)
{
dprintf("PCI: CreateDevice, bus %u, dev %u, func %u:\n", parent->bus, dev, func);
TRACE(("PCI: CreateDevice, bus %u, dev %u, func %u:\n", parent->bus, dev, func));
PCIDev *newdev = new PCIDev;
newdev->next = 0;
@@ -138,8 +138,8 @@ PCI::CreateDevice(PCIBus *parent, uint8 dev, uint8 func)
ReadPciBasicInfo(newdev);
dprintf("PCI: vendor 0x%04x, device 0x%04x, class_base 0x%02x, class_sub 0x%02x\n",
newdev->info.vendor_id, newdev->info.device_id, newdev->info.class_base, newdev->info.class_sub);
TRACE(("PCI: vendor 0x%04x, device 0x%04x, class_base 0x%02x, class_sub 0x%02x\n",
newdev->info.vendor_id, newdev->info.device_id, newdev->info.class_base, newdev->info.class_sub));
// append
if (parent->child == 0) {
@@ -302,7 +302,7 @@ PCI::ReadPciHeaderInfo(PCIDev *dev)
}
default:
dprintf("PCI: Header type unknown (%d)\n", dev->info.header_type);
TRACE(("PCI: Header type unknown (%d)\n", dev->info.header_type));
break;
}
}
src/add-ons/kernel/bus_managers/pci/pci.h
+7
View File
@@ -3,6 +3,13 @@
extern "C" {
#endif
#define TRACE_PCI
#ifndef TRACE_PCI
#define TRACE(x)
#else
#define TRACE(x) dprintf x
#endif
void pci_init(void);
void pci_uninit(void);
long pci_get_nth_pci_info(long index, pci_info *outInfo);
src/add-ons/kernel/bus_managers/pci/pci_info.cpp
+38 -38
View File
@@ -29,51 +29,51 @@ const char *get_class_info(uint8 class_base, uint8 class_sub, uint8 class_api);
void
print_bridge_info(pci_info *info, bool verbose)
{
dprintf("PCI: primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, secondary_latency %02x\n",
info->u.h1.primary_bus, info->u.h1.secondary_bus, info->u.h1.subordinate_bus, info->u.h1.secondary_latency);
dprintf("PCI: io_base %04x%02x, io_limit %04x%02x\n",
info->u.h1.io_base_upper16, info->u.h1.io_base, info->u.h1.io_limit_upper16, info->u.h1.io_limit);
dprintf("PCI: memory_base %04x, memory_limit %04x\n",
info->u.h1.memory_base, info->u.h1.memory_limit);
dprintf("PCI: prefetchable memory base %08lx%04x, limit %08lx%04x\n",
TRACE(("PCI: primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, secondary_latency %02x\n",
info->u.h1.primary_bus, info->u.h1.secondary_bus, info->u.h1.subordinate_bus, info->u.h1.secondary_latency));
TRACE(("PCI: io_base %04x%02x, io_limit %04x%02x\n",
info->u.h1.io_base_upper16, info->u.h1.io_base, info->u.h1.io_limit_upper16, info->u.h1.io_limit));
TRACE(("PCI: memory_base %04x, memory_limit %04x\n",
info->u.h1.memory_base, info->u.h1.memory_limit));
TRACE(("PCI: prefetchable memory base %08lx%04x, limit %08lx%04x\n",
info->u.h1.prefetchable_memory_base_upper32, info->u.h1.prefetchable_memory_base,
info->u.h1.prefetchable_memory_limit_upper32, info->u.h1.prefetchable_memory_limit);
dprintf("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h1.bridge_control, info->u.h1.secondary_status);
dprintf("PCI: interrupt_line %02x, interrupt_pin %02x\n",
info->u.h1.interrupt_line, info->u.h1.interrupt_pin);
dprintf("PCI: ROM base host %08lx, pci %08lx, size ??\n",
info->u.h1.rom_base, info->u.h1.rom_base_pci);
info->u.h1.prefetchable_memory_limit_upper32, info->u.h1.prefetchable_memory_limit));
TRACE(("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h1.bridge_control, info->u.h1.secondary_status));
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x\n",
info->u.h1.interrupt_line, info->u.h1.interrupt_pin));
TRACE(("PCI: ROM base host %08lx, pci %08lx, size ??\n",
info->u.h1.rom_base, info->u.h1.rom_base_pci));
for (int i = 0; i < 2; i++)
dprintf("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n",
TRACE(("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n",
i, info->u.h1.base_registers[i], info->u.h1.base_registers_pci[i],
info->u.h1.base_register_sizes[i], info->u.h1.base_register_flags[i]);
info->u.h1.base_register_sizes[i], info->u.h1.base_register_flags[i]));
}
void
print_generic_info(pci_info *info, bool verbose)
{
dprintf("PCI: ROM base host %08lx, pci %08lx, size %08lx\n",
info->u.h0.rom_base, info->u.h0.rom_base_pci, info->u.h0.rom_size);
dprintf("PCI: cardbus_CIS %08lx, subsystem_id %04x, subsystem_vendor_id %04x\n",
info->u.h0.cardbus_cis, info->u.h0.subsystem_id, info->u.h0.subsystem_vendor_id);
dprintf("PCI: interrupt_line %02x, interrupt_pin %02x, min_grant %02x, max_latency %02x\n",
info->u.h0.interrupt_line, info->u.h0.interrupt_pin, info->u.h0.min_grant, info->u.h0.max_latency);
TRACE(("PCI: ROM base host %08lx, pci %08lx, size %08lx\n",
info->u.h0.rom_base, info->u.h0.rom_base_pci, info->u.h0.rom_size));
TRACE(("PCI: cardbus_CIS %08lx, subsystem_id %04x, subsystem_vendor_id %04x\n",
info->u.h0.cardbus_cis, info->u.h0.subsystem_id, info->u.h0.subsystem_vendor_id));
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x, min_grant %02x, max_latency %02x\n",
info->u.h0.interrupt_line, info->u.h0.interrupt_pin, info->u.h0.min_grant, info->u.h0.max_latency));
for (int i = 0; i < 6; i++)
dprintf("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n",
TRACE(("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n",
i, info->u.h0.base_registers[i], info->u.h0.base_registers_pci[i],
info->u.h0.base_register_sizes[i], info->u.h0.base_register_flags[i]);
info->u.h0.base_register_sizes[i], info->u.h0.base_register_flags[i]));
}
void
print_info_basic(pci_info *info, bool verbose)
{
dprintf("PCI: bus %2d, device %2d, function %2d: vendor %04x, device %04x, revision %02x\n",
info->bus, info->device, info->function, info->vendor_id, info->device_id, info->revision);
dprintf("PCI: class_base %02x, class_function %02x, class_api %02x\n",
info->class_base, info->class_sub, info->class_api);
TRACE(("PCI: bus %2d, device %2d, function %2d: vendor %04x, device %04x, revision %02x\n",
info->bus, info->device, info->function, info->vendor_id, info->device_id, info->revision));
TRACE(("PCI: class_base %02x, class_function %02x, class_api %02x\n",
info->class_base, info->class_sub, info->class_api));
if (verbose) {
#if USE_PCI_HEADER
@@ -81,27 +81,27 @@ print_info_basic(pci_info *info, bool verbose)
const char *venFull;
get_vendor_info(info->vendor_id, &venShort, &venFull);
if (!venShort && !venFull) {
dprintf("PCI: vendor %04x: Unknown\n", info->vendor_id);
TRACE(("PCI: vendor %04x: Unknown\n", info->vendor_id));
} else if (venShort && venFull) {
dprintf("PCI: vendor %04x: %s - %s\n", info->vendor_id, venShort, venFull);
TRACE(("PCI: vendor %04x: %s - %s\n", info->vendor_id, venShort, venFull));
} else {
dprintf("PCI: vendor %04x: %s\n", info->vendor_id, venShort ? venShort : venFull);
TRACE(("PCI: vendor %04x: %s\n", info->vendor_id, venShort ? venShort : venFull));
}
const char *devShort;
const char *devFull;
get_device_info(info->vendor_id, info->device_id, &devShort, &devFull);
if (!devShort && !devFull) {
dprintf("PCI: device %04x: Unknown\n", info->device_id);
TRACE(("PCI: device %04x: Unknown\n", info->device_id));
} else if (devShort && devFull) {
dprintf("PCI: device %04x: %s - %s\n", info->device_id, devShort, devFull);
TRACE(("PCI: device %04x: %s - %s\n", info->device_id, devShort, devFull));
} else {
dprintf("PCI: device %04x: %s\n", info->device_id, devShort ? devShort : devFull);
TRACE(("PCI: device %04x: %s\n", info->device_id, devShort ? devShort : devFull));
}
#endif
dprintf("PCI: info: %s\n", get_class_info(info->class_base, info->class_sub, info->class_api));
TRACE(("PCI: info: %s\n", get_class_info(info->class_base, info->class_sub, info->class_api)));
}
dprintf("PCI: line_size %02x, latency %02x, header_type %02x, BIST %02x\n",
info->line_size, info->latency, info->header_type, info->bist);
TRACE(("PCI: line_size %02x, latency %02x, header_type %02x, BIST %02x\n",
info->line_size, info->latency, info->header_type, info->bist));
switch (info->header_type) {
case 0:
@@ -111,7 +111,7 @@ print_info_basic(pci_info *info, bool verbose)
print_bridge_info(info, verbose);
break;
default:
dprintf("PCI: unknown header type\n");
TRACE(("PCI: unknown header type\n"));
}
}
src/add-ons/kernel/bus_managers/pci/pci_module.c
+5 -5
View File
@@ -16,20 +16,20 @@ status_t pci_module_rescan(void);
status_t
pci_module_init(void)
{
dprintf("PCI: pci_module_init\n");
TRACE(("PCI: pci_module_init\n"));
if (B_OK != pci_io_init()) {
dprintf("PCI: pci_io_init failed\n");
TRACE(("PCI: pci_io_init failed\n"));
return B_ERROR;
}
if (B_OK != pci_config_init()) {
dprintf("PCI: pci_config_init failed\n");
TRACE(("PCI: pci_config_init failed\n"));
return B_ERROR;
}
if (B_OK != pci_irq_init()) {
dprintf("PCI: IRQ router not available\n");
TRACE(("PCI: IRQ router not available\n"));
} else {
gIrqRouterAvailable = true;
}
@@ -44,7 +44,7 @@ pci_module_init(void)
status_t
pci_module_uninit(void)
{
dprintf("PCI: pci_module_uninit\n");
TRACE(("PCI: pci_module_uninit\n"));
pci_uninit();
return B_OK;
}