boot/bios_ia32: basic support la57 aka 5-level paging for x86_64 kernels
la57 kernel support is required. we simply add a 5th level and enable the cr4 feature. the safemode option "256tb_memory_limit" is named after the 4gb one, but the current support is limited to 512GB as before (this can be later extended). Change-Id: I922774473c4a6112a0e4ff74162285ad58aa53af Reviewed-on: https://review.haiku-os.org/c/haiku/+/3552 Reviewed-by: Adrien Destugues <[email protected]> Reviewed-by: Axel Dörfler <[email protected]>
This commit is contained in:
Jérôme Duval
@@ -18,6 +18,7 @@
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#define B_SAFEMODE_DISABLE_HYPER_THREADING "disable_hyperthreading"
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#define B_SAFEMODE_FAIL_SAFE_VIDEO_MODE "fail_safe_video_mode"
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#define B_SAFEMODE_4_GB_MEMORY_LIMIT "4gb_memory_limit"
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#define B_SAFEMODE_256_TB_MEMORY_LIMIT "256tb_memory_limit"
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#if DEBUG_SPINLOCK_LATENCIES
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# define B_SAFEMODE_DISABLE_LATENCY_CHECK "disable_latency_check"
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@@ -21,6 +21,7 @@
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#include <boot/stage2.h>
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#include <boot/stdio.h>
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#include <kernel.h>
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#include <safemode.h>
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#include "debug.h"
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#include "mmu.h"
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@@ -35,7 +36,8 @@ static const uint64 kPageMappingFlags = 0x103;
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extern "C" void long_enter_kernel(int currentCPU, uint64 stackTop);
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extern uint64 gLongGDT;
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extern uint32 gLongPhysicalPML4;
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extern uint32 gLongPhysicalPMLTop;
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extern bool gLongLA57;
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extern uint64 gLongKernelEntry;
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@@ -88,16 +90,11 @@ long_gdt_init()
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static void
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long_mmu_init()
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{
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uint64* pml4;
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uint64* pdpt;
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uint64* pageDir;
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uint64* pageTable;
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addr_t physicalAddress;
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// Allocate the top level PML4.
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pml4 = (uint64*)mmu_allocate_page(&gKernelArgs.arch_args.phys_pgdir);
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memset(pml4, 0, B_PAGE_SIZE);
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gKernelArgs.arch_args.vir_pgdir = fix_address((uint64)(addr_t)pml4);
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uint64* pmlTop;
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// Allocate the top level PMLTop.
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pmlTop = (uint64*)mmu_allocate_page(&gKernelArgs.arch_args.phys_pgdir);
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memset(pmlTop, 0, B_PAGE_SIZE);
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gKernelArgs.arch_args.vir_pgdir = fix_address((uint64)(addr_t)pmlTop);
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// Store the virtual memory usage information.
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gKernelArgs.virtual_allocated_range[0].start = KERNEL_LOAD_BASE_64_BIT;
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@@ -127,6 +124,29 @@ long_mmu_init()
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if (maxAddress / 0x40000000 > 512)
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panic("Can't currently support more than 512GB of RAM!");
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uint64* pml4 = pmlTop;
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addr_t physicalAddress;
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cpuid_info info;
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if (get_current_cpuid(&info, 7, 0) == B_OK
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&& (info.regs.ecx & IA32_FEATURE_LA57) != 0) {
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if (get_safemode_boolean(B_SAFEMODE_256_TB_MEMORY_LIMIT, false)) {
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// LA57 has been disabled!
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dprintf("la57 disabled per safemode setting\n");
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} else {
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dprintf("la57 enabled\n");
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gLongLA57 = true;
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pml4 = (uint64*)mmu_allocate_page(&physicalAddress);
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memset(pml4, 0, B_PAGE_SIZE);
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pmlTop[511] = physicalAddress | kTableMappingFlags;
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pmlTop[0] = physicalAddress | kTableMappingFlags;
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}
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}
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uint64* pdpt;
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uint64* pageDir;
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uint64* pageTable;
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// Create page tables for the physical map area. Also map this PDPT
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// temporarily at the bottom of the address space so that we are identity
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// mapped.
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@@ -151,7 +171,6 @@ long_mmu_init()
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mmu_free(pdpt, B_PAGE_SIZE);
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// Allocate tables for the kernel mappings.
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pdpt = (uint64*)mmu_allocate_page(&physicalAddress);
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memset(pdpt, 0, B_PAGE_SIZE);
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pml4[511] = physicalAddress | kTableMappingFlags;
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@@ -186,6 +205,8 @@ long_mmu_init()
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mmu_free(pageTable, B_PAGE_SIZE);
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mmu_free(pageDir, B_PAGE_SIZE);
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mmu_free(pdpt, B_PAGE_SIZE);
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if (pml4 != pmlTop)
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mmu_free(pml4, B_PAGE_SIZE);
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// Sort the address ranges.
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sort_address_ranges(gKernelArgs.physical_memory_range,
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@@ -216,7 +237,7 @@ long_mmu_init()
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gKernelArgs.virtual_allocated_range[i].size);
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}
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gLongPhysicalPML4 = gKernelArgs.arch_args.phys_pgdir;
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gLongPhysicalPMLTop = gKernelArgs.arch_args.phys_pgdir;
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}
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@@ -27,6 +27,9 @@ FUNCTION(long_enter_kernel):
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movl 8(%esp), %edi
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movl 12(%esp), %esi
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movl gLongLA57, %ecx
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shl $12, %ecx
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// Currently running with 32-bit paging tables at an identity mapped
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// address. To switch to 64-bit paging we must first disable 32-bit paging,
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// otherwise loading the new CR3 will fault.
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@@ -34,13 +37,14 @@ FUNCTION(long_enter_kernel):
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andl $~(1 << 31), %eax
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movl %eax, %cr0
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// Enable PAE and PGE
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// Enable PAE and PGE, and optionally LA57
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movl %cr4, %eax
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orl $(1 << 5) | (1 << 7), %eax
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orl %ecx, %eax
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movl %eax, %cr4
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// Point CR3 to the kernel's PML4.
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movl gLongPhysicalPML4, %eax
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// Point CR3 to the kernel's PMLTop.
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movl gLongPhysicalPMLTop, %eax
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movl %eax, %cr3
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// Enable long mode by setting EFER.LME.
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@@ -97,7 +101,10 @@ long_gdtr:
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SYMBOL(gLongGDT):
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.long 0
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SYMBOL(gLongPhysicalPML4):
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SYMBOL(gLongPhysicalPMLTop):
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.long 0
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SYMBOL(gLongLA57):
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.long 0
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SYMBOL(gLongKernelEntry):
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@@ -589,16 +589,30 @@ smp_add_safemode_menus(Menu *menu)
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item->SetHelpText("Disables using X2APIC.");
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}
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if (get_current_cpuid(&info, 7, 0) == B_OK
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&& (info.regs.ebx & (IA32_FEATURE_SMEP
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| IA32_FEATURE_SMAP)) != 0) {
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menu->AddItem(item = new(nothrow) MenuItem(
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"Disable SMEP and SMAP"));
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item->SetType(MENU_ITEM_MARKABLE);
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item->SetData(B_SAFEMODE_DISABLE_SMEP_SMAP);
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item->SetHelpText("Disables using SMEP and SMAP.");
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}
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get_current_cpuid(&info, 0, 0);
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uint32 maxBasicLeaf = info.eax_0.max_eax;
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if (maxBasicLeaf >= 7) {
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if (get_current_cpuid(&info, 7, 0) == B_OK
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&& (info.regs.ebx & (IA32_FEATURE_SMEP
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| IA32_FEATURE_SMAP)) != 0) {
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menu->AddItem(item = new(nothrow) MenuItem(
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"Disable SMEP and SMAP"));
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item->SetType(MENU_ITEM_MARKABLE);
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item->SetData(B_SAFEMODE_DISABLE_SMEP_SMAP);
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item->SetHelpText("Disables using SMEP and SMAP.");
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}
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if (get_current_cpuid(&info, 7, 0) == B_OK
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&& (info.regs.ecx & IA32_FEATURE_LA57) != 0) {
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menu->AddItem(item = new(nothrow) MenuItem(
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"Ignore memory beyond 256 TiB"));
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item->SetType(MENU_ITEM_MARKABLE);
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item->SetData(B_SAFEMODE_256_TB_MEMORY_LIMIT);
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item->SetHelpText("Ignores all memory beyond the 256 TiB "
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"address limit, overriding the setting in the kernel "
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"settings file.");
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}
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}
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}
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if (gKernelArgs.num_cpus < 2)
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