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@@ -31,10 +31,12 @@ status_t nm_crtc_validate_timing(
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if (*hd_e < 640) *hd_e = 640;
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if (*hd_e > si->ps.max_crtc_width) *hd_e = si->ps.max_crtc_width;
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/* if hor. total does not leave room for a sensible sync pulse, increase it! */
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/* if hor. total does not leave room for a sensible sync pulse,*/
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/* increase it! */
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if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
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/* if hor. total does not adhere to max. blanking pulse width, decrease it! */
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/* if hor. total does not adhere to max. blanking pulse width,*/
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/* decrease it! */
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if (*ht > (*hd_e + 0x1f8)) *ht = (*hd_e + 0x1f8);
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/* make sure sync pulse is not during display */
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@@ -69,7 +71,8 @@ status_t nm_crtc_validate_timing(
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/*if vertical total does not leave room for a sync pulse, increase it!*/
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if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
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/* if vert. total does not adhere to max. blanking pulse width, decrease it! */
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/* if vert. total does not adhere to max. blanking pulse width,*/
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/* decrease it! */
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if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
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/* make sure sync pulse is not during display */
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@@ -114,15 +117,19 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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if (target.timing.h_display > si->ps.panel_width)
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{
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target.timing.h_display = si->ps.panel_width;
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LOG(4, ("CRTC: req. width > panel width: setting panning mode\n"));
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LOG(4,
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("CRTC: req. width > panel width: setting panning mode\n"));
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}
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if (target.timing.v_display > si->ps.panel_height)
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{
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target.timing.v_display = si->ps.panel_height;
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LOG(4, ("CRTC: req. height > panel height: setting scrolling mode\n"));
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LOG(4,
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("CRTC: req. height > panel height: setting scrolling "
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"mode\n"));
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}
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/* modify sync polarities (needed to maintain correct panel centering):
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/* modify sync polarities
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* (needed to maintain correct panel centering):
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* both polarities must be negative (confirmed NM2160) */
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target.timing.flags &= ~(B_POSITIVE_HSYNC | B_POSITIVE_VSYNC);
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}
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@@ -131,7 +138,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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htotal = ((target.timing.h_total >> 3) - 5);
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hdisp_e = ((target.timing.h_display >> 3) - 1);
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hblnk_s = hdisp_e;
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hblnk_e = (htotal + 0); /* this register differs from standard VGA! (says + 4) */
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hblnk_e = (htotal + 0); /* this register differs from standard VGA! */
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/* (says + 4) */
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hsync_s = (target.timing.h_sync_start >> 3);
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hsync_e = (target.timing.h_sync_end >> 3);
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@@ -142,7 +150,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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vsync_s = target.timing.v_sync_start;//-1;
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vsync_e = target.timing.v_sync_end;//-1;
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/* prevent memory adress counter from being reset (linecomp may not occur) */
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/* prevent memory adress counter from being reset */
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/* (linecomp may not occur) */
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linecomp = target.timing.v_display;
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if (crt_only)
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@@ -156,7 +165,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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/* actually program the card! */
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/* unlock CRTC registers at index 0-7 */
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temp = (ISACRTCR(VSYNCE) & 0x7f);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(VSYNCE, temp);
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/* horizontal standard VGA regs */
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@@ -178,10 +188,12 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))
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));
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ISACRTCW(PRROWSCN, 0x00); /* not used */
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ISACRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));
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ISACRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5))
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| ((linecomp & 0x200) >> (9 - 6))));
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ISACRTCW(VSYNCS, (vsync_s & 0xff));
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temp = (ISACRTCR(VSYNCE) & 0xf0);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(VSYNCE, (temp | (vsync_e & 0x0f)));
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ISACRTCW(VDISPE, (vdisp_e & 0xff));
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@@ -191,7 +203,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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// regp->CRTC[23] = 0xC3;
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ISACRTCW(LINECOMP, (linecomp & 0xff));
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/* horizontal - no extended regs available or needed on NeoMagic chips */
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/* horizontal - no extended regs available or needed on */
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/* NeoMagic chips */
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/* vertical - extended regs */
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//fixme: checkout if b2 or 3 should be switched! (linux contains error here)
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@@ -210,12 +223,14 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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}
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else
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{
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LOG(4,("CRTC: internal flatpanel active, setting display region only\n"));
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LOG(4,
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("CRTC: internal flatpanel active, setting display region only\n"));
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/* actually program the card! */
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/* unlock CRTC registers at index 0-7 */
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temp = (ISACRTCR(VSYNCE) & 0x7f);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(VSYNCE, temp);
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/* horizontal standard VGA regs */
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@@ -223,10 +238,11 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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/* vertical standard VGA regs */
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temp = (ISACRTCR(OVERFLOW) & ~0x52);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(OVERFLOW,
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(
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(
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temp |
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((vdisp_e & 0x100) >> (8 - 1)) |
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((vdisp_e & 0x200) >> (9 - 6)) |
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@@ -236,7 +252,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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ISACRTCW(PRROWSCN, 0x00); /* not used */
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temp = (ISACRTCR(MAXSCLIN) & ~0x40);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(MAXSCLIN, (temp | ((linecomp & 0x200) >> (9 - 6))));
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@@ -245,7 +262,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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// regp->CRTC[23] = 0xC3;
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ISACRTCW(LINECOMP, (linecomp & 0xff));
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/* horizontal - no extended regs available or needed on NeoMagic chips */
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/* horizontal - no extended regs available or needed on */
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/* NeoMagic chips */
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/* vertical - extended regs */
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//fixme: linecomp should have an extra bit... testable by setting linecomp
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@@ -254,7 +272,8 @@ status_t nm_crtc_set_timing(display_mode target, bool crt_only)
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if (si->ps.card_type >= NM2200)
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{
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temp = (ISACRTCR(VEXT) & ~0x02);
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/* we need to wait a bit or the card will mess-up it's register values.. */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. */
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snooze(10);
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ISACRTCW(VEXT,
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(
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@@ -374,7 +393,8 @@ status_t nm_crtc_depth(int mode)
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vid_delay |= (ISAGRPHR(COLDEPTH) & 0x70);
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break;
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}
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. (NM2160) */
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snooze(10);
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ISAGRPHW(COLDEPTH, vid_delay);
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@@ -387,6 +407,10 @@ status_t nm_crtc_depth(int mode)
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status_t nm_crtc_dpms(bool display, bool h, bool v)
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{
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char msg[100];
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const char* displayStatus;
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const char* horizontalSync;
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const char* verticalSync;
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uint8 temp, size_outputs;
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sprintf(msg, "CRTC: setting DPMS: ");
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@@ -396,7 +420,8 @@ status_t nm_crtc_dpms(bool display, bool h, bool v)
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/* turn screen off */
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temp = ISASEQR(CLKMODE);
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. (NM2160) */
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snooze(10);
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if (display)
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@@ -405,39 +430,43 @@ status_t nm_crtc_dpms(bool display, bool h, bool v)
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/* end synchronous reset if display should be enabled */
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ISASEQW(RESET, 0x03);
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sprintf(msg, "%sdisplay on, ", msg);
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displayStatus = "on";
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}
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else
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{
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ISASEQW(CLKMODE, (temp | 0x20));
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sprintf(msg, "%sdisplay off, ", msg);
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displayStatus = "off";
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}
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temp = 0x00;
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if (h)
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{
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sprintf(msg, "%shsync enabled, ", msg);
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horizontalSync = "enabled";
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}
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else
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{
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temp |= 0x10;
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sprintf(msg, "%shsync disabled, ", msg);
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horizontalSync = "disabled";
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}
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if (v)
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{
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sprintf(msg, "%svsync enabled\n", msg);
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verticalSync = "enabled";
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}
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else
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{
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temp |= 0x20;
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sprintf(msg, "%svsync disabled\n", msg);
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verticalSync = "disabled";
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}
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snprintf(msg, sizeof(msg),
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"CRTC: setting DPMS: display %s, hsync %s, vsync %s\n",
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displayStatus, horizontalSync, verticalSync);
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LOG(4, (msg));
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/* read panelsize and currently active outputs */
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size_outputs = nm_general_output_read();
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's register */
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/* values.. (NM2160) */
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snooze(10);
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if (si->ps.card_type < NM2200)
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@@ -445,7 +474,8 @@ status_t nm_crtc_dpms(bool display, bool h, bool v)
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/* no full DPMS support */
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if (temp)
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{
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/* Turn panel plus backlight and external monitor's sync signals off */
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/* Turn panel plus backlight and external monitor's */
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/* sync signals off */
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ISAGRPHW(PANELCTRL1, (size_outputs & 0xfc));
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}
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else
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@@ -473,19 +503,21 @@ status_t nm_crtc_dpms(bool display, bool h, bool v)
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/* we have full DPMS support for external monitors */
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//fixme: checkout if so...
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temp |= ((ISAGRPHR(ENSETRESET) & 0x0f) | 0x80);
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. (NM2160) */
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snooze(10);
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ISAGRPHW(ENSETRESET, temp);
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snooze(10);
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LOG(4,("CRTC: DPMS readback $%02x, programmed $%02x\n", ISAGRPHR(ENSETRESET), temp));
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LOG(4,("CRTC: DPMS readback $%02x, programmed $%02x\n",
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ISAGRPHR(ENSETRESET), temp));
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}
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}
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return B_OK;
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}
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status_t nm_crtc_set_display_pitch()
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status_t nm_crtc_set_display_pitch()
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{
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uint32 offset;
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@@ -495,7 +527,7 @@ status_t nm_crtc_set_display_pitch()
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offset = si->fbc.bytes_per_row / 8;
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LOG(2,("CRTC: offset register set to: $%04x\n", offset));
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/* program the card */
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ISACRTCW(PITCHL, (offset & 0xff));
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//fixme: test for max supported pitch if possible,
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@@ -507,7 +539,7 @@ status_t nm_crtc_set_display_pitch()
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return B_OK;
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}
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status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp)
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status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp)
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{
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uint8 val;
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uint32 timeout = 0;
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@@ -516,8 +548,9 @@ status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp)
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LOG(2,("CRTC: frameRAM: $%08x\n",si->framebuffer));
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LOG(2,("CRTC: framebuffer: $%08x\n",si->fbc.frame_buffer));
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/* make sure we _just_ left retrace, because otherwise distortions might occur
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* during our reprogramming (no double buffering) (verified on NM2160) */
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/* make sure we _just_ left retrace, because otherwise distortions */
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/* might occur during our reprogramming (no double buffering) */
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/* (verified on NM2160) */
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/* we might have no retraces during setmode! So:
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* wait 25mS max. for retrace to occur (refresh > 40Hz) */
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@@ -545,7 +578,8 @@ status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp)
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//this is testable via virtualscreen in 640x480x8 mode...
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//(b4 is >256Kb adresswrap bit, so that's already occupied)
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val = ISAGRPHR(FBSTADDE);
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's */
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/* register values.. (NM2160) */
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snooze(10);
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if (si->ps.card_type < NM2200)
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/* extended bits: (b18-20) */
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@@ -573,11 +607,13 @@ status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp)
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return B_OK;
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}
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/* setup centering mode for current internal or simultaneous flatpanel mode */
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/* setup centering mode for current internal or simultaneous */
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/* flatpanel mode */
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status_t nm_crtc_center(display_mode target, bool crt_only)
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{
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/* note:
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* NM2070 apparantly doesn't support horizontal centering this way... */
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* NM2070 apparantly doesn't support horizontal */
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/* centering this way... */
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uint8 vcent1, vcent2, vcent3, vcent4, vcent5;
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uint8 hcent1, hcent2, hcent3, hcent4, hcent5;
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@@ -637,8 +673,8 @@ status_t nm_crtc_center(display_mode target, bool crt_only)
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vcent5 = voffset;
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break;
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case 1280:
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/* this mode equals the largest possible panel on the newest chip:
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* so no centering needed here. */
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/* this mode equals the largest possible panel on the *
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* newest chip: so no centering needed here. */
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break;
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default:
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//fixme?: block non-standard modes? for now: not centered.
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@@ -669,15 +705,18 @@ status_t nm_crtc_center(display_mode target, bool crt_only)
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/* program panel control register 2: don't touch bit 3-5 */
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ctrl2 |= (ISAGRPHR(PANELCTRL2) & 0x38);
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's register */
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/* values.. (NM2160) */
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snooze(10);
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ISAGRPHW(PANELCTRL2, ctrl2);
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if (si->ps.card_type > NM2070)
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{
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/* program panel control register 3: don't touch bit 7-5 and bit 3-0 */
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/* program panel control register 3: don't touch bit 7-5 */
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/* and bit 3-0 */
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|
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ctrl3 |= (ISAGRPHR(PANELCTRL3) & 0xef);
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|
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/* we need to wait a bit or the card will mess-up it's register values.. (NM2160) */
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/* we need to wait a bit or the card will mess-up it's */
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|
|
/* register values.. (NM2160) */
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|
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snooze(10);
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|
|
ISAGRPHW(PANELCTRL3, ctrl3);
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|
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}
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|
@@ -690,7 +729,8 @@ status_t nm_crtc_prg_panel()
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|
|
{
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|
|
status_t stat = B_ERROR;
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|
|
/* only NM2070 requires this apparantly (because it's BIOS doesn't do it OK) */
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|
|
/* only NM2070 requires this apparantly */
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|
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/* (because it's BIOS doesn't do it OK) */
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|
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|
|
if (si->ps.card_type > NM2070) return B_OK;
|
|
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|
|
switch(si->ps.panel_width)
|
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|
|
@@ -910,7 +950,8 @@ status_t nm_crtc_cursor_init()
|
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|
|
|
|
|
|
|
|
/* we must set a valid colordepth to get full RAM access on Neomagic cards:
|
|
|
|
|
* in old pre 8-bit color VGA modes some planemask is in effect apparantly,
|
|
|
|
|
* allowing access only to every 7th and 8th RAM byte across the entire RAM. */
|
|
|
|
|
* allowing access only to every 7th and 8th RAM byte across the
|
|
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|
|
* entire RAM. */
|
|
|
|
|
nm_crtc_depth(BPP8);
|
|
|
|
|
|
|
|
|
|
/* clear cursor: so we need full RAM access! */
|
|
|
|
@@ -941,7 +982,8 @@ status_t nm_crtc_cursor_show()
|
|
|
|
|
|
|
|
|
|
status_t nm_crtc_cursor_hide()
|
|
|
|
|
{
|
|
|
|
|
//linux fixme: using this kills PCI(?) access sometimes, so use ISA access as below...
|
|
|
|
|
//linux fixme: using this kills PCI(?) access sometimes,
|
|
|
|
|
//so use ISA access as below...
|
|
|
|
|
/*
|
|
|
|
|
if (si->ps.card_type < NM2200)
|
|
|
|
|
{
|
|
|
|
|