* Renaming macros
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22624 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Salvatore Benedetto
@@ -19,58 +19,58 @@
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// --------------------------------
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#define OHCI_REVISION 0x00
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#define OHCI_REV_LO(rev) ((rev) & 0x0f)
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#define OHCI_REV_HI(rev) (((rev) >> 4) & 0x03)
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#define OHCI_REV_LEGACY(rev) ((rev) & 0x10)
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#define OHCI_REVISION_LOW(rev) ((rev) & 0x0f)
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#define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03)
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#define OHCI_REVISION_LEGACY(rev) ((rev) & 0x10)
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// --------------------------------
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// Control register (section 7.1.2)
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// --------------------------------
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#define OHCI_CONTROL 0x04
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#define OHCI_CBSR_MASK 0x00000003 // Control-Bulk Service Ratio
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#define OHCI_RATIO_1_1 0x00000000
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#define OHCI_RATIO_1_2 0x00000001
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#define OHCI_RATIO_1_3 0x00000002
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#define OHCI_RATIO_1_4 0x00000003
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#define OHCI_PLE 0x00000004 // Periodic List Enable
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#define OHCI_IE 0x00000008 // Isochronous Enable
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#define OHCI_CLE 0x00000010 // Control List Enable
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#define OHCI_BLE 0x00000020 // Bulk List Enable
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#define OHCI_HCFS_MASK 0x000000c0 // HostControllerFunctionalState
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#define OHCI_HCFS_RESET 0x00000000
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#define OHCI_HCFS_RESUME 0x00000040
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#define OHCI_HCFS_OPERATIONAL 0x00000080
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#define OHCI_HCFS_SUSPEND 0x000000c0
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#define OHCI_IR 0x00000100 // Interrupt Routing
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#define OHCI_RWC 0x00000200 // Remote Wakeup Connected
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#define OHCI_RWE 0x00000400 // Remote Wakeup Enabled
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#define OHCI_CONTROL 0x04
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#define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK 0x00000003
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#define OHCI_CONTROL_BULK_RATIO_1_1 0x00000000
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#define OHCI_CONTROL_BULK_RATIO_1_2 0x00000001
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#define OHCI_CONTROL_BULK_RATIO_1_3 0x00000002
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#define OHCI_CONTROL_BULK_RATIO_1_4 0x00000003
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#define OHCI_PERIODIC_LIST_ENABLE 0x00000004
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#define OHCI_ISOCHRONOUS_ENABLE 0x00000008
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#define OHCI_CONTROL_LIST_ENABLE 0x00000010
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#define OHCI_BULK_LIST_ENABLE 0x00000020
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#define OHCI_HC_FUNCTIONAL_STATE_MASK 0x000000c0
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#define OHCI_HC_FUNCTIONAL_STATE_RESET 0x00000000
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#define OHCI_HC_FUNCTIONAL_STATE_RESUME 0x00000040
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#define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL 0x00000080
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#define OHCI_HC_FUNCTIONAL_STATE_SUSPEND 0x000000c0
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#define OHCI_INTERRUPT_ROUTING 0x00000100
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#define OHCI_REMOTE_WAKEUP_CONNECTED 0x00000200
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#define OHCI_REMORE_WAKEUP_ENABLED 0x00000400
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// --------------------------------
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// Command status register (section 7.1.3)
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// --------------------------------
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#define OHCI_COMMAND_STATUS 0x08
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#define OHCI_HCR 0x00000001 // Host Controller Reset
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#define OHCI_CLF 0x00000002 // Control List Filled
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#define OHCI_BLF 0x00000004 // Bulk List Filled
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#define OHCI_OCR 0x00000008 // Ownership Change Request
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#define OHCI_SOC_MASK 0x00030000 // Scheduling Overrun Count
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#define OHCI_COMMAND_STATUS 0x08
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#define OHCI_HOST_CONTROLLER_RESET 0x00000001
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#define OHCI_CONTROL_LIST_FILLED 0x00000002
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#define OHCI_BULK_LIST_FILLED 0x00000004
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#define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008
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#define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000
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// --------------------------------
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// Interrupt status register (section 7.1.4)
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// --------------------------------
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#define OHCI_INTERRUPT_STATUS 0x0c
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#define OHCI_SO 0x00000001 // Scheduling Overrun
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#define OHCI_WDH 0x00000002 // Writeback Done Head
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#define OHCI_SF 0x00000004 // Start of Frame
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#define OHCI_RD 0x00000008 // Resume Detected
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#define OHCI_UE 0x00000010 // Unrecoverable Error
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#define OHCI_FNO 0x00000020 // Frame Number Overflow
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#define OHCI_RHSC 0x00000040 // Root Hub Status Change
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#define OHCI_OC 0x40000000 // Ownership Change
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#define OHCI_MIE 0x80000000 // Master Interrupt Enable
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#define OHCI_INTERRUPT_STATUS 0x0c
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#define OHCI_SCHEDULING_OVERRUN 0x00000001
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#define OHCI_WRITEBACK_DONE_HEAD 0x00000002
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#define OHCI_START_OF_FRAME 0x00000004
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#define OHCI_RESUME_DETECTED 0x00000008
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#define OHCI_UNRECOVERABLE_ERROR 0x00000010
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#define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020
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#define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040
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#define OHCI_OWNERSHIP_CHANGE 0x40000000
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#define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000
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// --------------------------------
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// Interupt enable register (section 7.1.5)
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@@ -138,34 +138,34 @@
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// Frame interval register (section 7.3.1)
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// --------------------------------
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#define OHCI_FM_INTERVAL 0x34
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#define OHCI_GET_IVAL(s) ((s) & 0x3fff)
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#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff)
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#define OHCI_FIT 0x80000000
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#define OHCI_FRAME_INTERVAL 0x34
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#define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff)
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#define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff)
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#define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000
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// --------------------------------
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// Frame remaining register (section 7.3.2)
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// --------------------------------
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#define OHCI_FM_REMAINING 0x38
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#define OHCI_FRAME_REMAINING 0x38
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// --------------------------------
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// Frame number register (section 7.3.3)
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// --------------------------------
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#define OHCI_FM_NUMBER 0x3c
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#define OHCI_FRAME_NUMBER 0x3c
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// --------------------------------
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// Periodic start register (section 7.3.4)
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// --------------------------------
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#define OHCI_PERIODIC_START 0x40
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#define OHCI_PERIODIC_START 0x40
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// --------------------------------
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// LS treshold register (section 7.3.5)
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// Low Speed (LS) treshold register (section 7.3.5)
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// --------------------------------
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#define OHCI_LS_THRESHOLD 0x44
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#define OHCI_LOW_SPEED_THRESHOLD 0x44
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// --------------------------------
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// Root Hub Partition (section 7.4)
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@@ -175,14 +175,14 @@
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// Root Hub Descriptor A register (section 7.4.1)
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// --------------------------------
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#define OHCI_RH_DESCRIPTOR_A 0x48
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#define OHCI_GET_PORT_COUNT(s) ((s) & 0xff)
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#define OHCI_PSM 0x0100 // Power Switching Mode
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#define OHCI_NPS 0x0200 // No Power Switching
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#define OHCI_DT 0x0400 // Device Type
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#define OHCI_OCPM 0x0800 // Overcurrent Protection Mode
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#define OHCI_NOCP 0x1000 // No Overcurrent Protection
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#define OHCI_GET_POTPGT(s) ((s) >> 24)
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#define OHCI_RH_DESCRIPTOR_A 0x48
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#define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff)
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#define OHCI_RH_POWER_SWITCHING_MODE 0x0100
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#define OHCI_RH_NO_POWER_SWITCHING 0x0200
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#define OHCI_RH_DEVICE_TYPE 0x0400
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#define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800
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#define OHCI_RH_NO_OVER_CURRENT_PROTECTION_MODE 0x1000
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#define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24)
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// --------------------------------
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// Root Hub Descriptor B register (section 7.4.2)
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@@ -194,61 +194,61 @@
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// Root Hub status register (section 7.4.3)
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// --------------------------------
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#define OHCI_RH_STATUS 0x50
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#define OHCI_LPS 0x00000001 // Local Power Status
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#define OHCI_OCI 0x00000002 // OverCurrent Indicator
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#define OHCI_DRWE 0x00008000 // Device Remote Wakeup Enable
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#define OHCI_LPSC 0x00010000 // Local Power Status Change
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#define OHCI_CCIC 0x00020000 // OverCurrent Indicator Change
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#define OHCI_CRWE 0x80000000 // Clear Remote Wakeup Enable
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#define OHCI_RH_STATUS 0x50
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#define OHCI_RH_LOCAL_POWER_STATUS 0x00000001
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#define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002
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#define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000
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#define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000
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#define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000
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#define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000
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// --------------------------------
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// Root Hub port status (n) register (section 7.4.4)
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// --------------------------------
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#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) // 1 based indexing
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#define OHCI_PORTSTATUS_CCS 0x00000001 // Current Connection Status
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#define OHCI_PORTSTATUS_PES 0x00000002 // Port Enable Status
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#define OHCI_PORTSTATUS_PSS 0x00000004 // Port Suspend Status
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#define OHCI_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator
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#define OHCI_PORTSTATUS_PRS 0x00000010 // Port Reset Status
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#define OHCI_PORTSTATUS_PPS 0x00000100 // Port Power Status
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#define OHCI_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached
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#define OHCI_PORTSTATUS_CSC 0x00010000 // Connection Status Change
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#define OHCI_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change
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#define OHCI_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change
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#define OHCI_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change
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#define OHCI_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change
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#define OHCI_RH_PORT_STATUS(n) (0x50 + (n) * 4) // 1 based indexing
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#define OHCI_RH_PORTSTATUS_CCS 0x00000001 // Current Connection Status
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#define OHCI_RH_PORTSTATUS_PES 0x00000002 // Port Enable Status
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#define OHCI_RH_PORTSTATUS_PSS 0x00000004 // Port Suspend Status
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#define OHCI_RH_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator
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#define OHCI_RH_PORTSTATUS_PRS 0x00000010 // Port Reset Status
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#define OHCI_RH_PORTSTATUS_PPS 0x00000100 // Port Power Status
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#define OHCI_RH_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached
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#define OHCI_RH_PORTSTATUS_CSC 0x00010000 // Connection Status Change
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#define OHCI_RH_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change
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#define OHCI_RH_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change
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#define OHCI_RH_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change
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#define OHCI_RH_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change
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// --------------------------------
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// ????
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// --------------------------------
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#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
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#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
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// --------------------------------
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// All interupts
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// --------------------------------
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#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | OHCI_FNO | OHCI_RHSC | OHCI_OC)
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#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | OHCI_FNO | OHCI_RHSC | OHCI_OC)
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// --------------------------------
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// All normal interupts
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// --------------------------------
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#define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
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#define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
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// --------------------------------
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// FSMPS
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// --------------------------------
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#define OHCI_FSMPS(i) (((i-210)*6/7) << 16)
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#define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16)
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// --------------------------------
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// Periodic
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// --------------------------------
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#define OHCI_PERIODIC(i) ((i)*9/10)
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#define OHCI_PERIODIC(i) ((i) * 9 / 10)
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// --------------------------------
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// OHCI physical address
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@@ -264,9 +264,9 @@ typedef uint32 ohci_physaddr_t;
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typedef struct ohci_hcca
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{
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addr_t hcca_interrupt_table[OHCI_NUMBER_OF_INTERRUPTS];
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uint32 hcca_frame_number;
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addr_t hcca_done_head;
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uint32 hcca_interrupt_table[OHCI_NUMBER_OF_INTERRUPTS];
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uint16 hcca_frame_number;
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uint32 hcca_done_head;
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uint8 hcca_reserved_for_hc[116];
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};
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@@ -322,22 +322,22 @@ typedef struct ohci_general_transfer_descriptor
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uint32 last_byte_address; // Physical buffer end
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};
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#define OHCI_BUFFER_ROUNDING 0x00040000 // Buffer Rounding
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#define OHCI_TD_DIRECTION_PID_MASK 0x00180000 // Direction / PID
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#define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
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#define OHCI_TD_DIRECTION_PID_OUT 0x00080000
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#define OHCI_TD_DIRECTION_PID_IN 0x00100000
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#define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) // Delay Interrupt
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#define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
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#define OHCI_TD_NO_INTERRUPT 0x00e00000
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#define OHCI_TD_INTERRUPT_MASK 0x00e00000
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#define OHCI_TD_TOGGLE_CARRY 0x00000000
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#define OHCI_TD_TOGGLE_0 0x02000000
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#define OHCI_TD_TOGGLE_1 0x03000000
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#define OHCI_TD_TOGGLE_MASK 0x03000000
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#define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3) // Error Count
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#define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28) // Condition Code
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#define OHCI_TD_NO_CONDITION_CODE 0xf0000000
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#define OHCI_BUFFER_ROUNDING 0x00040000
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#define OHCI_TD_DIRECTION_PID_MASK 0x00180000
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#define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
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#define OHCI_TD_DIRECTION_PID_OUT 0x00080000
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#define OHCI_TD_DIRECTION_PID_IN 0x00100000
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#define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
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#define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
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#define OHCI_TD_NO_INTERRUPT 0x00e00000
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#define OHCI_TD_INTERRUPT_MASK 0x00e00000
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#define OHCI_TD_TOGGLE_CARRY 0x00000000
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#define OHCI_TD_TOGGLE_0 0x02000000
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#define OHCI_TD_TOGGLE_1 0x03000000
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#define OHCI_TD_TOGGLE_MASK 0x03000000
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#define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3)
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#define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28)
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#define OHCI_TD_NO_CONDITION_CODE 0xf0000000
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#define OHCI_GENERAL_TD_ALIGN 16
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@@ -355,22 +355,22 @@ typedef struct ohci_isochronous_transfer_descriptor
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uint16 offset[OHCI_ITD_NOFFSET]; // Buffer offsets
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};
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#define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff)
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#define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff)
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#define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
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#define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21)
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#define OHCI_ITD_NO_INTERRUPT 0x00e00000
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#define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1)
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#define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24)
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#define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28)
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#define OHCI_ITD_NO_CONDITION_CODE 0xf0000000
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#define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff)
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#define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff)
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#define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
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#define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21)
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#define OHCI_ITD_NO_INTERRUPT 0x00e00000
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#define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1)
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#define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24)
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#define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28)
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#define OHCI_ITD_NO_CONDITION_CODE 0xf0000000
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// TO FIX
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#define itd_pswn itd_offset // Packet Status Word
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#define OHCI_ITD_PAGE_SELECT 0x00001000
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#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff))
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#define OHCI_ITD_GET_BUFFER_LENGTH(x) ((x) & 0xfff) // Transfer length
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#define OHCI_ITD_GET_BUFFER_CONDITION_CODE(x) ((x) >> 12) // Condition Code
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#define OHCI_ITD_GET_BUFFER_LENGTH(x) ((x) & 0xfff)
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#define OHCI_ITD_GET_BUFFER_CONDITION_CODE(x) ((x) >> 12)
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#define OHCI_ISOCHRONOUS_TD_ALIGN 32
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@@ -378,26 +378,26 @@ typedef struct ohci_isochronous_transfer_descriptor
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// Completion Codes (section 4.3.3)
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// --------------------------------
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#define OHCI_NO_ERROR 0
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#define OHCI_CRC 1
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#define OHCI_BIT_STUFFING 2
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#define OHCI_DATA_TOGGLE_MISMATCH 3
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#define OHCI_STALL 4
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#define OHCI_DEVICE_NOT_RESPONDING 5
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#define OHCI_PID_CHECK_FAILURE 6
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#define OHCI_UNEXPECTED_PID 7
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#define OHCI_DATA_OVERRUN 8
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#define OHCI_DATA_UNDERRUN 9
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#define OHCI_BUFFER_OVERRUN 12
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#define OHCI_BUFFER_UNDERRUN 13
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#define OHCI_NOT_ACCESSED 15
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#define OHCI_NO_ERROR 0
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#define OHCI_CRC 1
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#define OHCI_BIT_STUFFING 2
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#define OHCI_DATA_TOGGLE_MISMATCH 3
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#define OHCI_STALL 4
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#define OHCI_DEVICE_NOT_RESPONDING 5
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#define OHCI_PID_CHECK_FAILURE 6
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#define OHCI_UNEXPECTED_PID 7
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#define OHCI_DATA_OVERRUN 8
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||||
#define OHCI_DATA_UNDERRUN 9
|
||||
#define OHCI_BUFFER_OVERRUN 12
|
||||
#define OHCI_BUFFER_UNDERRUN 13
|
||||
#define OHCI_NOT_ACCESSED 15
|
||||
|
||||
// --------------------------------
|
||||
// Some delay needed when changing
|
||||
// certain registers.
|
||||
// --------------------------------
|
||||
|
||||
#define OHCI_ENABLE_POWER_DELAY 5
|
||||
#define OHCI_READ_DESC_DELAY 5
|
||||
#define OHCI_ENABLE_POWER_DELAY 5
|
||||
#define OHCI_READ_DESC_DELAY 5
|
||||
|
||||
#endif // OHCI_HARD_H
|
||||
|
||||
Reference in New Issue
Block a user