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Switch to using the PIT in mode 0 (interrupt on 0) instead of mode 2 (rate

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generator). There are chipsets (namely ATI/AMD SBx00) where mode 2 doesn't seem
to work (the counter isn't reloaded after the countdown has completed). Mode 0
has the same resolution as mode 2 and, as interrupts are disabled at this point
in booting, is otherwise equivalent as well. I've tested this on 5 machines
available to me and it doesn't seem to have any negative effect.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41683 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2011-05-23 14:51:42 +00:00
parent 7adc7269d8
commit 2ae3d5121c
1 changed files with 1 additions and 1 deletions
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src/system/boot/platform/bios_ia32/cpu.cpp
+1 -1
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@@ -185,7 +185,7 @@ calibration_loop(uint8 desiredHighByte, uint8 channel, uint64& tscDelta,
double& conversionFactor, uint16& expired) double& conversionFactor, uint16& expired)
{ {
uint8 select = channel << PIT_SELECT_CHANNEL_SHIFT; uint8 select = channel << PIT_SELECT_CHANNEL_SHIFT;
out8(select | PIT_ACCESS_LOW_THEN_HIGH_BYTE | PIT_MODE_RATE_GENERATOR out8(select | PIT_ACCESS_LOW_THEN_HIGH_BYTE | PIT_MODE_INTERRUPT_ON_0
| PIT_BINARY_MODE, PIT_CONTROL); | PIT_BINARY_MODE, PIT_CONTROL);
// Fill in count of 0xffff, low then high byte // Fill in count of 0xffff, low then high byte