openBeOS_Nvidia_V0.02_src
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5447 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
@@ -0,0 +1,308 @@
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/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002-4/2003.
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*/
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#ifndef DRIVERINTERFACE_H
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#define DRIVERINTERFACE_H
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#include <Accelerant.h>
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#include "video_overlay.h"
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#include <Drivers.h>
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#include <PCI.h>
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#include <OS.h>
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#define DRIVER_PREFIX "nv" // apsed
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/*
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Internal driver state (also for sharing info between driver and accelerant)
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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typedef struct {
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sem_id sem;
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int32 ben;
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} benaphore;
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#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0;
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#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
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/*dualhead extensions to flags*/
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#define DUALHEAD_OFF (0<<6)
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#define DUALHEAD_CLONE (1<<6)
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#define DUALHEAD_ON (2<<6)
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#define DUALHEAD_SWITCH (3<<6)
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#define DUALHEAD_BITS (3<<6)
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#define DUALHEAD_CAPABLE (1<<8)
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#define TV_BITS (3<<9)
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#define TV_MON (0<<9
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#define TV_PAL (1<<9)
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#define TV_NTSC (2<<9)
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#define TV_CAPABLE (1<<11)
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#define SKD_MOVE_CURSOR 0x00000001
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#define SKD_PROGRAM_CLUT 0x00000002
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#define SKD_SET_START_ADDR 0x00000004
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#define SKD_SET_CURSOR 0x00000008
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#define SKD_HANDLER_INSTALLED 0x80000000
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enum {
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NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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NV_GET_PCI,
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NV_SET_PCI,
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NV_DEVICE_NAME,
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NV_RUN_INTERRUPTS
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};
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/* max. number of overlay buffers */
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#define MAXBUFFERS 3
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/* max. pixelclock speed the BES supports */
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#define BESMAXSPEED 135000
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/* internal used info on overlay buffers */
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typedef struct
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{
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uint16 slopspace;
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uint32 size;
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} int_buf_info;
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typedef struct settings { // apsed, see comments in nv.settings
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// for driver
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char accelerant[B_FILE_NAME_LENGTH];
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bool dumprom;
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// for accelerant
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uint32 logmask;
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uint32 memory;
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bool usebios;
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bool hardcursor;
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bool greensync;
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} settings;
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/*shared info*/
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typedef struct {
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/*a few ID things*/
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uint16 vendor_id; /* PCI vendor ID, from pci_info */
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uint16 device_id; /* PCI device ID, from pci_info */
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uint8 revision; /* PCI device revsion, from pci_info */
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/* bug workaround for 4.5.0 */
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uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
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uint32 * clone_bugfix_regs;
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/*memory mappings*/
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area_id regs_area; /* Kernel's area_id for the memory mapped registers.
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It will be cloned into the accelerant's address
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space. */
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area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
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area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */
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area_id dma_buffer_area; /* Area assigned for dma*/
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void *framebuffer; /* As viewed from virtual memory */
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void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
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void *pseudo_dma; /* As viewed from virtual memory */
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void *dma_buffer; /* buffer for dma*/
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void *dma_buffer_pci; /* buffer for dma - from PCI bus*/
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/*screenmode list*/
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area_id mode_area; /* Contains the list of display modes the driver supports */
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uint32 mode_count; /* Number of display modes in the list */
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/*flags - used by driver*/
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uint32 flags;
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/*vblank semaphore*/
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sem_id vblank; /* The vertical blank semaphore. Ownership will be
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transfered to the team opening the device first */
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/*cursor information*/
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struct {
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uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
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uint16 hot_y; /* is 0,0 */
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uint16 x; /* The location of the cursor hot spot on the */
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uint16 y; /* desktop */
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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} cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration: head1 */
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display_mode dm2; /* current display mode configuration: head2 */
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bool switched_crtcs; /* dualhead stretch and switch mode info */
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bool acc_mode; /* signals (non)accelerated mode */
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bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
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frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acceleration engine */
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} engine;
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of NV chip design
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NV04 = 0,
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NV05,
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NV05M64,
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NV06,
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NV10,
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NV11,
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NV11M,
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NV15,
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NV17,
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NV17M,
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NV18,
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NV18M,
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NV20,
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NV25,
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NV28,
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NV30,
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NV31,
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NV34,
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NV35,
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G550//remove later on
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};
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enum
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{ // card_arch in order of date of NV chip design
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NV04A = 0,
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NV10A,
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NV20A,
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NV30A
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};
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enum
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{ // tvout_chip_type in order of capability (more or less)
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NONE = 0,
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CH7003,
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CH7004,
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CH7005,
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CH7006,
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CH7007,
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SAA7102,
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SAA7108,
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BT868,
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BT869,
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CX25870,
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CX25871,
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NVIDIA
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};
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struct
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{
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/* specialised registers for card initialisation read from NV BIOS (pins) */
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/* general card information */
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uint32 card_type; /* see card_type enum above */
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uint32 card_arch; /* see card_arch enum above */
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bool laptop; /* mobile chipset or not ('internal' flatpanel!) */
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uint32 tvout_chip_type; /* see tvchip_type enum above */
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status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
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bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */
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/* PINS */
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float f_ref; /* PLL reference-oscillator frequency (Mhz) */
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uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
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uint32 min_system_vco;
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uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
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uint32 min_pixel_vco;
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uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */
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uint32 min_video_vco;
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uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
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uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */
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uint32 max_dac1_clock; /* dac1 limits (Mhz) */
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uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac1_clock_16;
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uint32 max_dac1_clock_24;
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uint32 max_dac1_clock_32;
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uint32 max_dac1_clock_32dh;
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uint32 max_dac2_clock; /* dac2 limits (Mhz) */
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uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac2_clock_16;
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uint32 max_dac2_clock_24;
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uint32 max_dac2_clock_32;
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uint32 max_dac2_clock_32dh;
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bool secondary_head; /* presence of functions */
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bool tvout;
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bool primary_dvi;
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bool secondary_dvi;
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uint32 memory_size; /* memory (Mb) */
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} ps;
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/*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/
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uint8 rom_mirror[32768];
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/*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/
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uint8 crtc_delay;
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/* apsed: some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
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settings settings;
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struct
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{
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overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
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int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
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overlay_token myToken; /* scaler is free/in use */
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benaphore lock; /* for creating buffers and aquiring overlay unit routines */
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} overlay;
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} shared_info;
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/* Read or write a value in PCI configuration space */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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uint32 offset; /* Offset to read/write */
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uint32 size; /* Number of bytes to transfer */
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uint32 value; /* The value read or written */
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} nv_get_set_pci;
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/* Set some boolean condition (like enabling or disabling interrupts) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool do_it; /* state to set */
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} nv_set_bool_state;
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/* Retrieve the area_id of the kernel/accelerant shared info */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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area_id shared_info_area; /* area_id containing the shared information */
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} nv_get_private_data;
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/* Retrieve the device name. Usefull for when we have a file handle, but want
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to know the device name (like when we are cloning the accelerant) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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char *name; /* The name of the device, less the /dev root */
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} nv_device_name;
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enum {
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_WAIT_FOR_VBLANK = (1 << 0)
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif
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@@ -0,0 +1,494 @@
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/* NV registers definitions and macros for access to */
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//new:
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/* PCI_config_space */
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#define NVCFG_DEVID 0x00
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#define NVCFG_DEVCTRL 0x04
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#define NVCFG_CLASS 0x08
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#define NVCFG_HEADER 0x0c
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#define NVCFG_BASE1REGS 0x10
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#define NVCFG_BASE2FB 0x14
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#define NVCFG_BASE3 0x18
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#define NVCFG_BASE4 0x1c //unknown if used
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#define NVCFG_BASE5 0x20 //unknown if used
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#define NVCFG_BASE6 0x24 //unknown if used
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#define NVCFG_BASE7 0x28 //unknown if used
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#define NVCFG_SUBSYSID1 0x2c
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#define NVCFG_ROMBASE 0x30
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#define NVCFG_CFG_0 0x34
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#define NVCFG_CFG_1 0x38 //unknown if used
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#define NVCFG_INTERRUPT 0x3c
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#define NVCFG_SUBSYSID2 0x40
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#define NVCFG_AGPREF 0x44
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#define NVCFG_AGPSTAT 0x48
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#define NVCFG_AGPCMD 0x4c
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#define NVCFG_ROMSHADOW 0x50
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#define NVCFG_VGA 0x54
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#define NVCFG_SCHRATCH 0x58
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#define NVCFG_CFG_10 0x5c
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#define NVCFG_CFG_11 0x60
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#define NVCFG_CFG_12 0x64
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#define NVCFG_CFG_13 0x68 //unknown if used
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#define NVCFG_CFG_14 0x6c //unknown if used
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#define NVCFG_CFG_15 0x70 //unknown if used
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#define NVCFG_CFG_16 0x74 //unknown if used
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#define NVCFG_CFG_17 0x78 //unknown if used
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#define NVCFG_GF2IGPU 0x7c
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#define NVCFG_CFG_19 0x80 //unknown if used
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#define NVCFG_GF4MXIGPU 0x84
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#define NVCFG_CFG_21 0x88 //unknown if used
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#define NVCFG_CFG_22 0x8c //unknown if used
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#define NVCFG_CFG_23 0x90 //unknown if used
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#define NVCFG_CFG_24 0x94 //unknown if used
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#define NVCFG_CFG_25 0x98 //unknown if used
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#define NVCFG_CFG_26 0x9c //unknown if used
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#define NVCFG_CFG_27 0xa0 //unknown if used
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#define NVCFG_CFG_28 0xa4 //unknown if used
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#define NVCFG_CFG_29 0xa8 //unknown if used
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#define NVCFG_CFG_30 0xac //unknown if used
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#define NVCFG_CFG_31 0xb0 //unknown if used
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#define NVCFG_CFG_32 0xb4 //unknown if used
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#define NVCFG_CFG_33 0xb8 //unknown if used
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#define NVCFG_CFG_34 0xbc //unknown if used
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#define NVCFG_CFG_35 0xc0 //unknown if used
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#define NVCFG_CFG_36 0xc4 //unknown if used
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#define NVCFG_CFG_37 0xc8 //unknown if used
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#define NVCFG_CFG_38 0xcc //unknown if used
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#define NVCFG_CFG_39 0xd0 //unknown if used
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#define NVCFG_CFG_40 0xd4 //unknown if used
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#define NVCFG_CFG_41 0xd8 //unknown if used
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#define NVCFG_CFG_42 0xdc //unknown if used
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#define NVCFG_CFG_43 0xe0 //unknown if used
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#define NVCFG_CFG_44 0xe4 //unknown if used
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#define NVCFG_CFG_45 0xe8 //unknown if used
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#define NVCFG_CFG_46 0xec //unknown if used
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#define NVCFG_CFG_47 0xf0 //unknown if used
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#define NVCFG_CFG_48 0xf4 //unknown if used
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#define NVCFG_CFG_49 0xf8 //unknown if used
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#define NVCFG_CFG_50 0xfc //unknown if used
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/* if(pNv->SecondCRTC) {
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pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000;
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pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800;
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pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800;
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pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000;
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} else {
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pNv->riva.PCIO = pNv->riva.PCIO0;
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pNv->riva.PCRTC = pNv->riva.PCRTC0;
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pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0;
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pNv->riva.PDIO = pNv->riva.PDIO0;
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}
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*/
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/*
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* These registers are read/write as 8 bit values. Probably have to map
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* sparse on alpha.
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*/
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/* pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
|
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pNv->PciTag, regBase+0x00601000,
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0x00003000);
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pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
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pNv->PciTag, regBase+0x00681000,
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0x00003000);
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pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
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pNv->PciTag, regBase+0x000C0000,
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0x00001000);
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pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
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regBase+0x00680000, 0x00003000);
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pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
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regBase+0x00600000, 0x00003000);
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*/
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/* Nvidia PCI direct registers */
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#define NV8_MISCW 0x000c03c2
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#define NV8_MISCR 0x000c03cc
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#define NV8_SEQIND 0x000c03c4
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#define NV16_SEQIND 0x000c03c4
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#define NV8_SEQDAT 0x000c03c5
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||||
#define NV8_GRPHIND 0x000c03ce
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||||
#define NV16_GRPHIND 0x000c03ce
|
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#define NV8_GRPHDAT 0x000c03cf
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||||
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/* bootstrap info registers */
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||||
#define NV32_NV4STRAPINFO 0x00100000
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||||
#define NV32_NV10STRAPINFO 0x0010020c
|
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#define NV32_NVSTRAPINFO2 0x00101000
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||||
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||||
/* primary head */
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||||
#define NV8_ATTRINDW 0x006013c0
|
||||
#define NV8_ATTRDATW 0x006013c0
|
||||
#define NV8_ATTRDATR 0x006013c1
|
||||
#define NV8_CRTCIND 0x006013d4
|
||||
#define NV16_CRTCIND 0x006013d4
|
||||
#define NV8_CRTCDAT 0x006013d5
|
||||
#define NV8_INSTAT1 0x006013da
|
||||
#define NV32_NV10FBSTADD32 0x00600800
|
||||
#define NV32_CONFIG 0x00600804//not yet used (coldstart)...
|
||||
#define NV32_NV10CURADD32 0x0060080c
|
||||
#define NV32_CURCONF 0x00600810
|
||||
|
||||
/* secondary head */
|
||||
#define NV8_ATTR2INDW 0x006033c0
|
||||
#define NV8_ATTR2DATW 0x006033c0
|
||||
#define NV8_ATTR2DATR 0x006033c1
|
||||
#define NV8_CRTC2IND 0x006033d4
|
||||
#define NV16_CRTC2IND 0x006033d4
|
||||
#define NV8_CRTC2DAT 0x006033d5
|
||||
#define NV8_2INSTAT1 0x006033da//verify!!!
|
||||
#define NV32_NV10FB2STADD32 0x00602800//verify!!!
|
||||
#define NV32_NV10CUR2ADD32 0x0060280c//verify!!!
|
||||
#define NV32_2CURCONF 0x00602810//verify!!!
|
||||
|
||||
/* Nvidia DAC direct registers (standard VGA palette RAM registers) */
|
||||
/* primary head */
|
||||
#define NV8_PALMASK 0x006813c6
|
||||
#define NV8_PALINDR 0x006813c7
|
||||
#define NV8_PALINDW 0x006813c8
|
||||
#define NV8_PALDATA 0x006813c9
|
||||
/* secondary head */
|
||||
#define NV8_PAL2MASK 0x006833c6//verify!!!
|
||||
#define NV8_PAL2INDR 0x006833c7//verify!!!
|
||||
#define NV8_PAL2INDW 0x006833c8//verify!!!
|
||||
#define NV8_PAL2DATA 0x006833c9//verify!!!
|
||||
|
||||
/* Nvidia PCI direct DAC registers (32bit) */
|
||||
/* primary head */
|
||||
#define NVDAC_CURPOS 0x00680300
|
||||
#define NVDAC_PIXPLLC 0x00680508
|
||||
#define NVDAC_PLLSEL 0x0068050c
|
||||
#define NVDAC_GENCTRL 0x00680600
|
||||
/* secondary head */
|
||||
#define NVDAC2_CURPOS 0x00680b00
|
||||
#define NVDAC2_PIXPLLC 0x00680d20//verify!!!
|
||||
#define NVDAC2_PLLSEL 0x00680d0c//verify!!!
|
||||
#define NVDAC2_GENCTRL 0x00680e00//verify!!!
|
||||
|
||||
/* Nvidia CRTC indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVCRTCX_HTOTAL 0x00
|
||||
#define NVCRTCX_HDISPE 0x01
|
||||
#define NVCRTCX_HBLANKS 0x02
|
||||
#define NVCRTCX_HBLANKE 0x03
|
||||
#define NVCRTCX_HSYNCS 0x04
|
||||
#define NVCRTCX_HSYNCE 0x05
|
||||
#define NVCRTCX_VTOTAL 0x06
|
||||
#define NVCRTCX_OVERFLOW 0x07
|
||||
#define NVCRTCX_PRROWSCN 0x08
|
||||
#define NVCRTCX_MAXSCLIN 0x09
|
||||
#define NVCRTCX_VGACURCTRL 0x0a
|
||||
#define NVCRTCX_FBSTADDH 0x0c //confirmed
|
||||
#define NVCRTCX_FBSTADDL 0x0d //confirmed
|
||||
#define NVCRTCX_VSYNCS 0x10
|
||||
#define NVCRTCX_VSYNCE 0x11
|
||||
#define NVCRTCX_VDISPE 0x12
|
||||
#define NVCRTCX_PITCHL 0x13 //confirmed
|
||||
#define NVCRTCX_VBLANKS 0x15
|
||||
#define NVCRTCX_VBLANKE 0x16
|
||||
#define NVCRTCX_MODECTL 0x17
|
||||
#define NVCRTCX_LINECOMP 0x18
|
||||
/* Nvidia specific registers: */
|
||||
#define NVCRTCX_REPAINT0 0x19
|
||||
#define NVCRTCX_REPAINT1 0x1a
|
||||
#define NVCRTCX_LOCK 0x1f
|
||||
#define NVCRTCX_LSR 0x25
|
||||
#define NVCRTCX_PIXEL 0x28
|
||||
#define NVCRTCX_HEB 0x2d
|
||||
#define NVCRTCX_CURCTL2 0x2f
|
||||
#define NVCRTCX_CURCTL1 0x30
|
||||
#define NVCRTCX_CURCTL0 0x31
|
||||
|
||||
/* Nvidia ATTRIBUTE indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVATBX_MODECTL 0x10
|
||||
#define NVATBX_OSCANCOLOR 0x11
|
||||
#define NVATBX_COLPLANE_EN 0x12
|
||||
#define NVATBX_HORPIXPAN 0x13 //confirmed
|
||||
#define NVATBX_COLSEL 0x14
|
||||
|
||||
/* Nvidia SEQUENCER indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVSEQX_RESET 0x00
|
||||
#define NVSEQX_CLKMODE 0x01
|
||||
#define NVSEQX_MEMMODE 0x04
|
||||
|
||||
/* Nvidia GRAPHICS indexed registers */
|
||||
/* VGA standard registers: */
|
||||
#define NVGRPHX_ENSETRESET 0x01
|
||||
#define NVGRPHX_DATAROTATE 0x03
|
||||
#define NVGRPHX_READMAPSEL 0x04
|
||||
#define NVGRPHX_MODE 0x05
|
||||
#define NVGRPHX_MISC 0x06
|
||||
#define NVGRPHX_BITMASK 0x08
|
||||
//end new.
|
||||
|
||||
/* (D)AC (X) (I)ndexed registers (>= G100) */
|
||||
#define NVDXI_VREFCTRL 0x18
|
||||
#define NVDXI_MULCTRL 0x19
|
||||
#define NVDXI_PIXCLKCTRL 0x1A
|
||||
#define NVDXI_GENCTRL 0x1D
|
||||
#define NVDXI_MISCCTRL 0x1E
|
||||
#define NVDXI_PANELMODE 0x1F
|
||||
#define NVDXI_MAFCDEL 0x20
|
||||
#define NVDXI_GENIOCTRL 0x2A
|
||||
#define NVDXI_GENIODATA 0x2B
|
||||
#define NVDXI_SYSPLLM 0x2C
|
||||
#define NVDXI_SYSPLLN 0x2D
|
||||
#define NVDXI_SYSPLLP 0x2E
|
||||
#define NVDXI_SYSPLLSTAT 0x2F
|
||||
#define NVDXI_ZOOMCTRL 0x38
|
||||
#define NVDXI_SENSETEST 0x3A
|
||||
#define NVDXI_CRCREML 0x3C
|
||||
#define NVDXI_CRCREMH 0x3D
|
||||
#define NVDXI_CRCBITSEL 0x3E
|
||||
#define NVDXI_COLMSK 0x40
|
||||
#define NVDXI_COLKEY 0x42
|
||||
#define NVDXI_PIXPLLAM 0x44
|
||||
#define NVDXI_PIXPLLAN 0x45
|
||||
#define NVDXI_PIXPLLAP 0x46
|
||||
#define NVDXI_PIXPLLBM 0x48
|
||||
#define NVDXI_PIXPLLBN 0x49
|
||||
#define NVDXI_PIXPLLBP 0x4A
|
||||
#define NVDXI_PIXPLLCM 0x4C
|
||||
#define NVDXI_PIXPLLCN 0x4D
|
||||
#define NVDXI_PIXPLLCP 0x4E
|
||||
#define NVDXI_PIXPLLSTAT 0x4F
|
||||
#define NVDXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/
|
||||
|
||||
/* (D)AC (X) (I)ndexed registers (>= G200) */
|
||||
#define NVDXI_KEYOPMODE 0x51
|
||||
#define NVDXI_COLMSK0RED 0x52
|
||||
#define NVDXI_COLMSK0GREEN 0x53
|
||||
#define NVDXI_COLMSK0BLUE 0x54
|
||||
#define NVDXI_COLKEY0RED 0x55
|
||||
#define NVDXI_COLKEY0GREEN 0x56
|
||||
#define NVDXI_COLKEY0BLUE 0x57
|
||||
|
||||
/* (D)AC (X) (I)ndexed registers (>= G450) */
|
||||
#define NVDXI_TVO_IDX 0x87
|
||||
#define NVDXI_TVO_DATA 0x88
|
||||
#define NVDXI_OUTPUTCONN 0x8A
|
||||
#define NVDXI_SYNCCTRL 0x8B
|
||||
#define NVDXI_VIDPLLSTAT 0x8C
|
||||
#define NVDXI_VIDPLLP 0x8D
|
||||
#define NVDXI_VIDPLLM 0x8E
|
||||
#define NVDXI_VIDPLLN 0x8F
|
||||
#define NVDXI_PWRCTRL 0xA0
|
||||
#define NVDXI_PANMODE 0xA2
|
||||
|
||||
/* NV 1st CRTC registers */
|
||||
#define NVCR1_VCOUNT 0x1E20
|
||||
|
||||
/* NV 2nd CRTC registers (>= G400) */
|
||||
#define NVCR2_CTL 0x3C10
|
||||
#define NVCR2_HPARAM 0x3C14
|
||||
#define NVCR2_HSYNC 0x3C18
|
||||
#define NVCR2_VPARAM 0x3C1C
|
||||
#define NVCR2_VSYNC 0x3C20
|
||||
#define NVCR2_PRELOAD 0x3C24
|
||||
#define NVCR2_STARTADD0 0x3C28
|
||||
#define NVCR2_STARTADD1 0x3C2C
|
||||
#define NVCR2_OFFSET 0x3C40
|
||||
#define NVCR2_MISC 0x3C44
|
||||
#define NVCR2_VCOUNT 0x3C48
|
||||
#define NVCR2_DATACTL 0x3C4C
|
||||
|
||||
/* NV ACCeleration registers */
|
||||
#define NVACC_DWGCTL 0x1C00
|
||||
#define NVACC_MACCESS 0x1C04
|
||||
#define NVACC_MCTLWTST 0x1C08
|
||||
#define NVACC_ZORG 0x1C0C
|
||||
#define NVACC_PLNWT 0x1C1C
|
||||
#define NVACC_BCOL 0x1C20
|
||||
#define NVACC_FCOL 0x1C24
|
||||
#define NVACC_XYSTRT 0x1C40
|
||||
#define NVACC_XYEND 0x1C44
|
||||
#define NVACC_SGN 0x1C58
|
||||
#define NVACC_LEN 0x1C5C
|
||||
#define NVACC_AR0 0x1C60
|
||||
#define NVACC_AR3 0x1C6C
|
||||
#define NVACC_AR5 0x1C74
|
||||
#define NVACC_CXBNDRY 0x1C80
|
||||
#define NVACC_FXBNDRY 0x1C84
|
||||
#define NVACC_YDSTLEN 0x1C88
|
||||
#define NVACC_PITCH 0x1C8C
|
||||
#define NVACC_YDST 0x1C90
|
||||
#define NVACC_YDSTORG 0x1C94
|
||||
#define NVACC_YTOP 0x1C98
|
||||
#define NVACC_YBOT 0x1C9C
|
||||
#define NVACC_CXLEFT 0x1CA0
|
||||
#define NVACC_CXRIGHT 0x1CA4
|
||||
#define NVACC_FXLEFT 0x1CA8
|
||||
#define NVACC_FXRIGHT 0x1CAC
|
||||
#define NVACC_STATUS 0x1E14
|
||||
#define NVACC_ICLEAR 0x1E18 /* required for interrupt stuff */
|
||||
#define NVACC_IEN 0x1E1C /* required for interrupt stuff */
|
||||
#define NVACC_RST 0x1E40
|
||||
#define NVACC_MEMRDBK 0x1E44
|
||||
#define NVACC_OPMODE 0x1E54
|
||||
#define NVACC_PRIMADDRESS 0x1E58
|
||||
#define NVACC_PRIMEND 0x1E5C
|
||||
#define NVACC_TEXORG 0x2C24 // >= G100
|
||||
#define NVACC_DWGSYNC 0x2C4C // >= G200
|
||||
#define NVACC_TEXORG1 0x2CA4 // >= G200
|
||||
#define NVACC_TEXORG2 0x2CA8 // >= G200
|
||||
#define NVACC_TEXORG3 0x2CAC // >= G200
|
||||
#define NVACC_TEXORG4 0x2CB0 // >= G200
|
||||
#define NVACC_SRCORG 0x2CB4 // >= G200
|
||||
#define NVACC_DSTORG 0x2CB8 // >= G200
|
||||
|
||||
/*NV BES (Back End Scaler) registers (>= G200) */
|
||||
#define NVBES_A1ORG 0x3D00
|
||||
#define NVBES_A2ORG 0x3D04
|
||||
#define NVBES_B1ORG 0x3D08
|
||||
#define NVBES_B2ORG 0x3D0C
|
||||
#define NVBES_A1CORG 0x3D10
|
||||
#define NVBES_A2CORG 0x3D14
|
||||
#define NVBES_B1CORG 0x3D18
|
||||
#define NVBES_B2CORG 0x3D1C
|
||||
#define NVBES_CTL 0x3D20
|
||||
#define NVBES_PITCH 0x3D24
|
||||
#define NVBES_HCOORD 0x3D28
|
||||
#define NVBES_VCOORD 0x3D2C
|
||||
#define NVBES_HISCAL 0x3D30
|
||||
#define NVBES_VISCAL 0x3D34
|
||||
#define NVBES_HSRCST 0x3D38
|
||||
#define NVBES_HSRCEND 0x3D3C
|
||||
#define NVBES_LUMACTL 0x3D40
|
||||
#define NVBES_V1WGHT 0x3D48
|
||||
#define NVBES_V2WGHT 0x3D4C
|
||||
#define NVBES_HSRCLST 0x3D50
|
||||
#define NVBES_V1SRCLST 0x3D54
|
||||
#define NVBES_V2SRCLST 0x3D58
|
||||
#define NVBES_A1C3ORG 0x3D60
|
||||
#define NVBES_A2C3ORG 0x3D64
|
||||
#define NVBES_B1C3ORG 0x3D68
|
||||
#define NVBES_B2C3ORG 0x3D6C
|
||||
#define NVBES_GLOBCTL 0x3DC0
|
||||
#define NVBES_STATUS 0x3DC4
|
||||
|
||||
/*MAVEN registers (<= G400) */
|
||||
#define NVMAV_PGM 0x3E
|
||||
#define NVMAV_PIXPLLM 0x80
|
||||
#define NVMAV_PIXPLLN 0x81
|
||||
#define NVMAV_PIXPLLP 0x82
|
||||
#define NVMAV_GAMMA1 0x83
|
||||
#define NVMAV_GAMMA2 0x84
|
||||
#define NVMAV_GAMMA3 0x85
|
||||
#define NVMAV_GAMMA4 0x86
|
||||
#define NVMAV_GAMMA5 0x87
|
||||
#define NVMAV_GAMMA6 0x88
|
||||
#define NVMAV_GAMMA7 0x89
|
||||
#define NVMAV_GAMMA8 0x8A
|
||||
#define NVMAV_GAMMA9 0x8B
|
||||
#define NVMAV_MONSET 0x8C
|
||||
#define NVMAV_TEST 0x8D
|
||||
#define NVMAV_WREG_0X8E_L 0x8E
|
||||
#define NVMAV_WREG_0X8E_H 0x8F
|
||||
#define NVMAV_HSCALETV 0x90
|
||||
#define NVMAV_TSCALETVL 0x91
|
||||
#define NVMAV_TSCALETVH 0x92
|
||||
#define NVMAV_FFILTER 0x93
|
||||
#define NVMAV_MONEN 0x94
|
||||
#define NVMAV_RESYNC 0x95
|
||||
#define NVMAV_LASTLINEL 0x96
|
||||
#define NVMAV_LASTLINEH 0x97
|
||||
#define NVMAV_WREG_0X98_L 0x98
|
||||
#define NVMAV_WREG_0X98_H 0x99
|
||||
#define NVMAV_HSYNCLENL 0x9A
|
||||
#define NVMAV_HSYNCLENH 0x9B
|
||||
#define NVMAV_HSYNCSTRL 0x9C
|
||||
#define NVMAV_HSYNCSTRH 0x9D
|
||||
#define NVMAV_HDISPLAYL 0x9E
|
||||
#define NVMAV_HDISPLAYH 0x9F
|
||||
#define NVMAV_HTOTALL 0xA0
|
||||
#define NVMAV_HTOTALH 0xA1
|
||||
#define NVMAV_VSYNCLENL 0xA2
|
||||
#define NVMAV_VSYNCLENH 0xA3
|
||||
#define NVMAV_VSYNCSTRL 0xA4
|
||||
#define NVMAV_VSYNCSTRH 0xA5
|
||||
#define NVMAV_VDISPLAYL 0xA6
|
||||
#define NVMAV_VDISPLAYH 0xA7
|
||||
#define NVMAV_VTOTALL 0xA8
|
||||
#define NVMAV_VTOTALH 0xA9
|
||||
#define NVMAV_HVIDRSTL 0xAA
|
||||
#define NVMAV_HVIDRSTH 0xAB
|
||||
#define NVMAV_VVIDRSTL 0xAC
|
||||
#define NVMAV_VVIDRSTH 0xAD
|
||||
#define NVMAV_VSOMETHINGL 0xAE
|
||||
#define NVMAV_VSOMETHINGH 0xAF
|
||||
#define NVMAV_OUTMODE 0xB0
|
||||
#define NVMAV_LOCK 0xB3
|
||||
#define NVMAV_LUMA 0xB9
|
||||
#define NVMAV_VDISPLAYTV 0xBE
|
||||
#define NVMAV_STABLE 0xBF
|
||||
#define NVMAV_HDISPLAYTV 0xC2
|
||||
#define NVMAV_BREG_0XC6 0xC6
|
||||
|
||||
//new:
|
||||
/* Macros for convenient accesses to the NV chips */
|
||||
#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
|
||||
#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
|
||||
#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
|
||||
|
||||
/* read and write to PCI config space */
|
||||
#define CFGR(A) (nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), nv_pci_access.value)
|
||||
#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access)))
|
||||
|
||||
/* read and write from the dac registers */
|
||||
#define DACR(A) (NV_REG32(NVDAC_##A))
|
||||
#define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
|
||||
#define DAC2R(A) (NV_REG32(NVDAC2_##A))
|
||||
#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)
|
||||
//end new.
|
||||
|
||||
/* read and write from the dac index register */
|
||||
#define DXIR(A) (DACW(PALWTADD,NVDXI_##A),DACR(X_DATAREG))
|
||||
#define DXIW(A,B) (DACW(PALWTADD,NVDXI_##A),DACW(X_DATAREG,B))
|
||||
|
||||
/* read and write from the vga registers */
|
||||
#define VGAR(A) (NV_REG8(NVVGA_##A))
|
||||
#define VGAW(A,B) (NV_REG8(NVVGA_##A)=B)
|
||||
|
||||
/* read and write from the indexed vga registers */
|
||||
#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D))
|
||||
#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C))
|
||||
|
||||
/* read and write from the powergraphics registers */
|
||||
#define ACCR(A) (NV_REG32(NVACC_##A))
|
||||
#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
|
||||
#define ACCGO(A,B) (NV_REG32(NVACC_##A + 0x0100)=B)
|
||||
|
||||
/* read and write from the backend scaler registers */
|
||||
#define BESR(A) (NV_REG32(NVBES_##A))
|
||||
#define BESW(A,B) (NV_REG32(NVBES_##A)=B)
|
||||
|
||||
/* read and write from first CRTC */
|
||||
#define CR1R(A) (NV_REG32(NVCR1_##A))
|
||||
#define CR1W(A,B) (NV_REG32(NVCR1_##A)=B)
|
||||
|
||||
/* read and write from second CRTC */
|
||||
#define CR2R(A) (NV_REG32(NVCR2_##A))
|
||||
#define CR2W(A,B) (NV_REG32(NVCR2_##A)=B)
|
||||
|
||||
//new:
|
||||
/* read and write from CRTC indexed registers */
|
||||
#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8)))
|
||||
#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT))
|
||||
|
||||
/* read and write from ATTRIBUTE indexed registers */
|
||||
#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B))
|
||||
#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR))
|
||||
|
||||
/* read and write from SEQUENCER indexed registers */
|
||||
#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8)))
|
||||
#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT))
|
||||
|
||||
/* read and write from PCI GRAPHICS indexed registers (>= NM2097) */
|
||||
#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8)))
|
||||
#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT))
|
||||
//end new.
|
||||
|
||||
/* read and write from maven (<= G400) */
|
||||
#define MAVR(A) (i2c_maven_read (NVMAV_##A ))
|
||||
#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B))
|
||||
#define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8))
|
||||
#define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8))
|
||||
Reference in New Issue
Block a user