sis900: Import from FreeBSD 11.2.
This replaces the old Haiku-native driver that was removed in the last commit. It should support all the same chips that one did, in addition to the SiS 7014, and the DP83815 also. I don't have this hardware, so for anyone who does, please test. Fixes #1657.
This commit is contained in:
Augustin Cavalier
@@ -12,11 +12,11 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
|
||||
broadcom440x broadcom570x ipro1000
|
||||
rtl8139 rtl81xx
|
||||
via_rhine ipro100 nforce
|
||||
marvell_yukon syskonnect
|
||||
marvell_yukon sis900 syskonnect
|
||||
attansic_l2 ar81xx
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||||
}@ # x86
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||||
|
||||
etherpci pegasus sis900 usb_ecm wb840
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||||
etherpci pegasus usb_ecm wb840
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#vlance
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] ;
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||||
SYSTEM_ADD_ONS_BUS_MANAGERS = [ FFilterByBuildFeatures
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||||
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||||
@@ -190,13 +190,12 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
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||||
nforce
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||||
pcnet
|
||||
rtl8139 rtl81xx
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||||
sis19x syskonnect
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sis19x sis900 syskonnect
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||||
via_rhine vt612x
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||||
}@ # x86,x86_64
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||||
|
||||
etherpci
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||||
pegasus
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||||
sis900
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||||
usb_asix usb_davicom usb_ecm
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||||
wb840
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||||
|
||||
|
||||
@@ -9,7 +9,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network etherpci ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network pegasus ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network virtio ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network sis19x ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network sis900 ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network usb_asix ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network usb_davicom ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network usb_ecm ;
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||||
@@ -41,3 +40,4 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network vt612x ;
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||||
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||||
# FreeBSD 11.2 drivers
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network emulex_oce ;
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||||
SubInclude HAIKU_TOP src add-ons kernel drivers network sis900 ;
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|
||||
@@ -0,0 +1,28 @@
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||||
SubDir HAIKU_TOP src add-ons kernel drivers network sis900 ;
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||||
|
||||
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd11_network compat ]
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||||
: true ;
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||||
UsePrivateHeaders net system ;
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UsePrivateKernelHeaders ;
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||||
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||||
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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||||
|
||||
UseHeaders [ FDirName $(SUBDIR) ] : true ;
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||||
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||||
SEARCH_SOURCE += [ FDirName $(SUBDIR) dev mii ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) dev sis ] ;
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||||
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KernelAddon sis900 :
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||||
glue.c
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icsphy.c
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nsphyter.c
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ukphy.c
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ukphy_subr.c
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if_sis.c
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: libfreebsd11_network.a
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;
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ObjectHdrs [ FGristFiles icsphy$(SUFOBJ) nsphyter$(SUFOBJ) ukphy$(SUFOBJ) ]
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: [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR_$(TARGET_PACKAGING_ARCH)) libs
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compat freebsd11_network ] ;
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Includes [ FGristFiles icsphy.c nsphyter.c ukphy.c ] : <src!libs!compat!freebsd11_network>miidevs.h ;
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||||
@@ -0,0 +1,240 @@
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||||
/* $NetBSD: icsphy.c,v 1.41 2006/11/16 21:24:07 christos Exp $ */
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||||
|
||||
/*-
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||||
* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
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||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
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||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
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||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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||||
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||||
#include <sys/cdefs.h>
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||||
__FBSDID("$FreeBSD: stable/11/sys/dev/mii/icsphy.c 337755 2018-08-14 14:17:20Z markj $");
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||||
/*
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* driver for Integrated Circuit Systems' ICS1889-1893 ethernet 10/100 PHY
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* datasheet from www.icst.com
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*/
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||||
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||||
#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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||||
#include <sys/bus.h>
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||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
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||||
#include "miidevs.h"
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||||
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||||
#include <dev/mii/icsphyreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int icsphy_probe(device_t dev);
|
||||
static int icsphy_attach(device_t dev);
|
||||
|
||||
static device_method_t icsphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, icsphy_probe),
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||||
DEVMETHOD(device_attach, icsphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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||||
};
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||||
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static devclass_t icsphy_devclass;
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||||
static driver_t icsphy_driver = {
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"icsphy",
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icsphy_methods,
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sizeof(struct mii_softc)
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||||
};
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||||
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||||
DRIVER_MODULE(icsphy, miibus, icsphy_driver, icsphy_devclass, 0, 0);
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||||
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static int icsphy_service(struct mii_softc *, struct mii_data *, int);
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static void icsphy_status(struct mii_softc *);
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static void icsphy_reset(struct mii_softc *);
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static const struct mii_phydesc icsphys[] = {
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MII_PHY_DESC(ICS, 1889),
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MII_PHY_DESC(ICS, 1890),
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MII_PHY_DESC(ICS, 1892),
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||||
MII_PHY_DESC(ICS, 1893),
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||||
MII_PHY_DESC(ICS, 1893C),
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MII_PHY_END
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||||
};
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static const struct mii_phy_funcs icsphy_funcs = {
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icsphy_service,
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icsphy_status,
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icsphy_reset
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};
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static int
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icsphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, icsphys, BUS_PROBE_DEFAULT));
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}
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static int
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icsphy_attach(device_t dev)
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{
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mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
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&icsphy_funcs, 1);
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return (0);
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}
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static int
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icsphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return (0);
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break;
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}
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/* Update the media status. */
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PHY_STATUS(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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icsphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int bmcr, qpr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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/*
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* Don't get link from the BMSR. It's available in the QPR,
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* and we have to read it twice to unlatch it anyhow. This
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* gives us fewer register reads.
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*/
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qpr = PHY_READ(sc, MII_ICSPHY_QPR); /* unlatch */
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qpr = PHY_READ(sc, MII_ICSPHY_QPR); /* real value */
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if (qpr & QPR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if (bmcr & BMCR_ISO) {
|
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mii->mii_media_active |= IFM_NONE;
|
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mii->mii_media_status = 0;
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||||
return;
|
||||
}
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||||
|
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if (bmcr & BMCR_LOOP)
|
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mii->mii_media_active |= IFM_LOOP;
|
||||
|
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if (bmcr & BMCR_AUTOEN) {
|
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if ((qpr & QPR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
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mii->mii_media_active |= IFM_NONE;
|
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return;
|
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}
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if (qpr & QPR_SPEED)
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mii->mii_media_active |= IFM_100_TX;
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else
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mii->mii_media_active |= IFM_10_T;
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if (qpr & QPR_FDX)
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mii->mii_media_active |=
|
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IFM_FDX | mii_phy_flowstatus(sc);
|
||||
else
|
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mii->mii_media_active |= IFM_HDX;
|
||||
} else
|
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mii->mii_media_active = ife->ifm_media;
|
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}
|
||||
|
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static void
|
||||
icsphy_reset(struct mii_softc *sc)
|
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{
|
||||
|
||||
mii_phy_reset(sc);
|
||||
/* set powerdown feature */
|
||||
switch (sc->mii_mpd_model) {
|
||||
case MII_MODEL_ICS_1890:
|
||||
case MII_MODEL_ICS_1893:
|
||||
PHY_WRITE(sc, MII_ICSPHY_ECR2, ECR2_100AUTOPWRDN);
|
||||
break;
|
||||
case MII_MODEL_ICS_1892:
|
||||
PHY_WRITE(sc, MII_ICSPHY_ECR2,
|
||||
ECR2_10AUTOPWRDN|ECR2_100AUTOPWRDN);
|
||||
break;
|
||||
default:
|
||||
/* 1889 have no ECR2 */
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* There is no description that the reset do auto-negotiation in the
|
||||
* data sheet.
|
||||
*/
|
||||
PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_STARTNEG|BMCR_FDX);
|
||||
}
|
||||
@@ -0,0 +1,129 @@
|
||||
/* $NetBSD: icsphyreg.h,v 1.2 2003/07/01 22:46:08 msaitoh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_ICSPHYREG_H_
|
||||
#define _DEV_MII_ICSPHYREG_H_
|
||||
|
||||
/*
|
||||
* ICS1890 registers.
|
||||
* http://www.icst.com/pdf/18??.pdf
|
||||
*/
|
||||
|
||||
/* HEX 1889 1890 1892 1893
|
||||
*--------------------------------------------------------------
|
||||
* 0 Control * * * *
|
||||
* 1 Status * * * *
|
||||
* 2 PHY Identifier * * * *
|
||||
* 3 PHY Identifier * * * *
|
||||
* 4 Auto-Neg. Advertisement * * *
|
||||
* 5 Auto-Neg. Link Parent Adv * * *
|
||||
* 6 Auto-Neg. Expansion * * *
|
||||
* 7 Auto-Neg. Next Page Tx * *
|
||||
* 8 ANg Nxt Page Lnk Parnt Abl * *
|
||||
* 10 Extended Control * * * *
|
||||
* 11 Quick Poll Status * * * *
|
||||
* 12 10Base-T Operation * * *
|
||||
* 13 Extended Control2 * * *
|
||||
*/
|
||||
|
||||
#define MII_ICSPHY_ECR 0x10 /* Extended Control Register */
|
||||
#define ECR_OVR 0x8000 /* disable command reg overwrites */
|
||||
#define ECR_PHYADDR_MASK 0x07c0 /* PHY address mask */
|
||||
#define ECR_CTEST 0x0020 /* Stream Cipher Test Mode */
|
||||
#define ECR_IECT 0x0004 /* Invalid Error Code Test */
|
||||
#define ECR_SSD 0x0001 /* Stream Cipher Disable */
|
||||
|
||||
#define MII_ICSPHY_QPR 0x11 /* Quick Poll Register */
|
||||
#define QPR_SPEED 0x8000 /* 100Mbps */
|
||||
#define QPR_FDX 0x4000 /* Full dupled */
|
||||
#define QPR_ANB2 0x2000 /* Autoneg monitor bit 2 */
|
||||
#define QPR_ANB1 0x1000 /* Autoneg monitor bit 1 */
|
||||
#define QPR_ANB0 0x0800 /* Autoneg monitor bit 0 */
|
||||
#define QPR_RXERR 0x0400 /* Receive signal lost */
|
||||
#define QPR_PLLERR 0x0200 /* PLL error */
|
||||
#define QPR_FCARR 0x0100 /* False carrier detected */
|
||||
#define QPR_INVALSYM 0x0080 /* Invalid Symbol Detected */
|
||||
#define QPR_HALT 0x0040 /* Halt Symbol Detected */
|
||||
#define QPR_PREEM 0x0020 /* Two Idle Symbols together */
|
||||
#define QPR_ACOMP 0x0010 /* Autonegotiation complete */
|
||||
#define QPR_SDETECT 0x0008 /* signal detect */
|
||||
#define QPR_JABBER 0x0004 /* Jabber detected */
|
||||
#define QPR_RFAULT 0x0002 /* Remote Fault */
|
||||
#define QPR_LINK 0x0001 /* Link */
|
||||
|
||||
#define MII_ICSPHY_TTR 0x12 /* 10baseT Operations Register */
|
||||
#define TTR_RJABBER 0x8000 /* Remote Jabber */
|
||||
#define TTR_POLARITY 0x4000 /* Polarity Reversed */
|
||||
#define TTR_NOJABBER 0x0020 /* Disable Jabber Check */
|
||||
#define TTR_LOOP 0x0010 /* Loopback mode */
|
||||
#define TTR_NOAPOLARITY 0x0008 /* Disable auto polarity correction */
|
||||
#define TTR_NOSQE 0x0004 /* Disable SQE check */
|
||||
#define TTR_NOLINK 0x0002 /* Disable Link check */
|
||||
#define TTR_NOSQUELCH 0x0001 /* Disable squelch */
|
||||
|
||||
|
||||
/*
|
||||
* Extended Control Register 2
|
||||
*
|
||||
* HEX 1889 1890 1892 1893
|
||||
*-------------------------------------------------------------------
|
||||
* 8000 Node/Repeater Mode * * *
|
||||
* 4000 Hardware/Software Mode * * *
|
||||
* 2000 Link Partner Support Remote Flt *
|
||||
* 2000 Remote Fault * *
|
||||
* 1000
|
||||
* 0800
|
||||
* 0400 Xmitted Remote Fault status *
|
||||
* 0200
|
||||
* 0100
|
||||
* 0080 Tri-state Enable *
|
||||
* 0040
|
||||
* 0020
|
||||
* 0010 A-N Powerup Remote Flt *
|
||||
* 0008
|
||||
* 0004
|
||||
* 0002 Automatic 10Base-T Power Down *
|
||||
* 0001 Automatic 100Base-TX Power Down * * *
|
||||
*/
|
||||
|
||||
#define MII_ICSPHY_ECR2 0x13 /* Extended Control Register 2 */
|
||||
#define ECR2_REPEATER 0x8000 /* Repeater Mode */
|
||||
#define ECR2_HWSW 0x4000 /* hw/sw config priority */
|
||||
#define ECR2_LPRF 0x2000 /* link partner supports rem fault */
|
||||
#define ECR2_FORCERF 0x0400 /* Force transmit of rem fault */
|
||||
#define ECR2_RFPUP 0x0010 /* A-N Powerup Remote fault */
|
||||
#define ECR2_10AUTOPWRDN 0x0002 /* Automatic 10baseT power down */
|
||||
#define ECR2_100AUTOPWRDN 0x0001 /* Automatic 100baseTX power down */
|
||||
|
||||
#endif /* _DEV_MII_ICSPHYREG_H_ */
|
||||
@@ -0,0 +1,262 @@
|
||||
/* $NetBSD: nsphyter.c,v 1.28 2008/01/20 07:58:19 msaitoh Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Driver for the National Semiconductor's DP83843, DP83847 and DP83849
|
||||
* `PHYTER' Ethernet 10/100 PHYs
|
||||
* Data Sheets are available from http://www.national.com
|
||||
*
|
||||
* We also support the DP83815 `MacPHYTER' internal PHY since, for our
|
||||
* purposes, they are compatible.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/socket.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include "miidevs.h"
|
||||
|
||||
#include <dev/mii/nsphyterreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static device_probe_t nsphyter_probe;
|
||||
static device_attach_t nsphyter_attach;
|
||||
|
||||
static device_method_t nsphyter_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, nsphyter_probe),
|
||||
DEVMETHOD(device_attach, nsphyter_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t nsphyter_devclass;
|
||||
|
||||
static driver_t nsphyter_driver = {
|
||||
"nsphyter",
|
||||
nsphyter_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(nsphyter, miibus, nsphyter_driver, nsphyter_devclass, 0, 0);
|
||||
|
||||
static int nsphyter_service(struct mii_softc *, struct mii_data *, int);
|
||||
static void nsphyter_status(struct mii_softc *);
|
||||
static void nsphyter_reset(struct mii_softc *);
|
||||
|
||||
static const struct mii_phydesc nsphyters[] = {
|
||||
MII_PHY_DESC(xxNATSEMI, DP83815),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83843),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83847),
|
||||
MII_PHY_DESC(xxNATSEMI, DP83849),
|
||||
MII_PHY_END
|
||||
};
|
||||
|
||||
static const struct mii_phy_funcs nsphyter_funcs = {
|
||||
nsphyter_service,
|
||||
nsphyter_status,
|
||||
nsphyter_reset
|
||||
};
|
||||
|
||||
static int
|
||||
nsphyter_probe(device_t dev)
|
||||
{
|
||||
|
||||
return (mii_phy_dev_probe(dev, nsphyters, BUS_PROBE_DEFAULT));
|
||||
}
|
||||
|
||||
static int
|
||||
nsphyter_attach(device_t dev)
|
||||
{
|
||||
|
||||
mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &nsphyter_funcs, 1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nsphyter_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
PHY_STATUS(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
nsphyter_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, physts;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
physts = PHY_READ(sc, MII_NSPHYTER_PHYSTS);
|
||||
|
||||
if ((physts & PHYSTS_LINK) != 0)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(sc, MII_BMCR);
|
||||
if ((bmcr & BMCR_ISO) != 0) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((bmcr & BMCR_LOOP) != 0)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if ((bmcr & BMCR_AUTOEN) != 0) {
|
||||
/*
|
||||
* The media status bits are only valid if autonegotiation
|
||||
* has completed (or it's disabled).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((physts & PHYSTS_SPEED10) != 0)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
if ((physts & PHYSTS_DUPLEX) != 0)
|
||||
mii->mii_media_active |=
|
||||
IFM_FDX | mii_phy_flowstatus(sc);
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
|
||||
static void
|
||||
nsphyter_reset(struct mii_softc *sc)
|
||||
{
|
||||
struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
|
||||
int reg, i;
|
||||
|
||||
if ((sc->mii_flags & MIIF_NOISOLATE) != 0)
|
||||
reg = BMCR_RESET;
|
||||
else
|
||||
reg = BMCR_RESET | BMCR_ISO;
|
||||
PHY_WRITE(sc, MII_BMCR, reg);
|
||||
|
||||
/*
|
||||
* It is best to allow a little time for the reset to settle
|
||||
* in before we start polling the BMCR again. Notably, the
|
||||
* DP8384{3,7} manuals state that there should be a 500us delay
|
||||
* between asserting software reset and attempting MII serial
|
||||
* operations. Be conservative. Also, a DP83815 can get into
|
||||
* a bad state on cable removal and reinsertion if we do not
|
||||
* delay here.
|
||||
*/
|
||||
DELAY(1000);
|
||||
|
||||
/*
|
||||
* Wait another 2s for it to complete.
|
||||
* This is only a little overkill as under normal circumstances
|
||||
* the PHY can take up to 1s to complete reset.
|
||||
* This is also a bit odd because after a reset, the BMCR will
|
||||
* clear the reset bit and simply reports 0 even though the reset
|
||||
* is not yet complete.
|
||||
*/
|
||||
for (i = 0; i < 1000; i++) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
if (reg != 0 && (reg & BMCR_RESET) == 0)
|
||||
break;
|
||||
DELAY(2000);
|
||||
}
|
||||
|
||||
if ((sc->mii_flags & MIIF_NOISOLATE) == 0) {
|
||||
if ((ife == NULL && sc->mii_inst != 0) ||
|
||||
(ife != NULL && IFM_INST(ife->ifm_media) != sc->mii_inst))
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,179 @@
|
||||
/* $NetBSD: nsphyterreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999, 2001 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_NSPHYTERREG_H_
|
||||
#define _DEV_MII_NSPHYTERREG_H_
|
||||
|
||||
/*
|
||||
* DP83843 registers; We also have the MacPHYTER (DP83815) internal
|
||||
* PHY register definitions here, since the two are, for our purposes,
|
||||
* compatible.
|
||||
*/
|
||||
|
||||
#define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
|
||||
#define PHYSTS_REL 0x8000 /* receive error latch */
|
||||
#define PHYSTS_CIML 0x4000 /* CIM latch */
|
||||
#define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
|
||||
#define PHYSTS_DEVRDY 0x0800 /* device ready */
|
||||
#define PHYSTS_PGRX 0x0400 /* page received */
|
||||
#define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
|
||||
#define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
|
||||
#define PHYSTS_REMFAULT 0x0080 /* remote fault */
|
||||
#define PHYSTS_JABBER 0x0040 /* jabber detect */
|
||||
#define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */
|
||||
#define PHYSTS_RESETSTAT 0x0010 /* reset status */
|
||||
#define PHYSTS_LOOPBACK 0x0008 /* loopback status */
|
||||
#define PHYSTS_DUPLEX 0x0004 /* full duplex */
|
||||
#define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */
|
||||
#define PHYSTS_LINK 0x0001 /* link up */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PHYSTS_MP_REL 0x2000 /* receive error latch */
|
||||
#define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
|
||||
#define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */
|
||||
#define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
|
||||
#define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
|
||||
#define PHYSTS_MP_PGRX 0x0100 /* page received */
|
||||
#define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */
|
||||
#define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */
|
||||
#define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
|
||||
#define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
|
||||
control */
|
||||
|
||||
#define MIPSCR_INTEN 0x0002 /* interrupt enable */
|
||||
#define MIPSCR_TINT 0x0001 /* test interrupt */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
|
||||
status */
|
||||
#define MIPGSR_MINT 0x8000 /* MII interrupt pending */
|
||||
/* The bits below are MacPHYTER only. */
|
||||
#define MIPGSR_MSK_LINK 0x4000 /* mask link status event */
|
||||
#define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */
|
||||
#define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */
|
||||
#define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
|
||||
#define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */
|
||||
#define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
|
||||
|
||||
#define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */
|
||||
|
||||
#define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */
|
||||
|
||||
#define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
|
||||
#define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
|
||||
#define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
|
||||
#define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */
|
||||
#define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */
|
||||
#define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */
|
||||
#define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */
|
||||
#define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */
|
||||
#define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */
|
||||
#define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */
|
||||
#define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */
|
||||
#define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */
|
||||
#define PCSR_CODE_ERR 0x0008 /* code errors */
|
||||
#define PCSR_PME_ERR 0x0004 /* premature end errors */
|
||||
#define PCSR_LINK_ERR 0x0002 /* link errors */
|
||||
#define PCSR_PKT_ERR 0x0001 /* packet errors */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
|
||||
#define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */
|
||||
#define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
|
||||
#define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */
|
||||
#define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
|
||||
#define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
|
||||
|
||||
|
||||
/* The bits below are not on MacPHYTER. */
|
||||
#define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
|
||||
#define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
|
||||
#define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */
|
||||
#define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */
|
||||
#define LBR_BP_RX 0x0800 /* bypass receive function */
|
||||
#define LBR_BP_TX 0x0400 /* bypass transmit function */
|
||||
#define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */
|
||||
#define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
|
||||
#define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
|
||||
|
||||
|
||||
/* The bits below are not on MacPHYTER. */
|
||||
#define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
|
||||
#define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
|
||||
#define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
|
||||
#define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
|
||||
#define BTSCR_POL_DS 0x0400 /* polarity detection and correction
|
||||
disable */
|
||||
#define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */
|
||||
#define BTSCR_LP_DS 0x0100 /* link pulse disable */
|
||||
#define BTSCR_HB_DS 0x0080 /* heartbeat disabled */
|
||||
#define BTSCR_LS_SEL 0x0040 /* low squelch select */
|
||||
#define BTSCR_AUI_SEL 0x0020 /* AUI select */
|
||||
#define BTSCR_JAB_DS 0x0010 /* jabber disable */
|
||||
#define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
|
||||
#define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
|
||||
|
||||
|
||||
#define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
|
||||
#define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
|
||||
#define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
|
||||
#define PHYCTRL_REPEATER 0x0200 /* repeater mode */
|
||||
#define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
|
||||
#define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */
|
||||
#define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */
|
||||
#define PHYCTRL_PHYADDR 0x001f /* PHY address */
|
||||
/* Below are the MacPHYTER bits that are different. */
|
||||
#define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
|
||||
#define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
|
||||
#define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
|
||||
#define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
|
||||
#define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
|
||||
|
||||
|
||||
/* The bits below are MacPHYTER only. */
|
||||
#define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
|
||||
#define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */
|
||||
#define TBTCTL_LP_DIS 0x0080 /* link pulse disable */
|
||||
#define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */
|
||||
#define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */
|
||||
#define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
|
||||
#define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
|
||||
#define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */
|
||||
#define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */
|
||||
|
||||
#endif /* _DEV_MII_NSPHYTERREG_H_ */
|
||||
@@ -0,0 +1,158 @@
|
||||
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: releng/11.1/sys/dev/mii/ukphy.c 257184 2013-10-26 18:40:17Z glebius $");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int ukphy_probe(device_t);
|
||||
static int ukphy_attach(device_t);
|
||||
|
||||
static device_method_t ukphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ukphy_probe),
|
||||
DEVMETHOD(device_attach, ukphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t ukphy_devclass;
|
||||
|
||||
static driver_t ukphy_driver = {
|
||||
"ukphy",
|
||||
ukphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
|
||||
|
||||
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
|
||||
static const struct mii_phy_funcs ukphy_funcs = {
|
||||
ukphy_service,
|
||||
ukphy_status,
|
||||
mii_phy_reset
|
||||
};
|
||||
|
||||
static int
|
||||
ukphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
/*
|
||||
* We know something is here, so always match at a low priority.
|
||||
*/
|
||||
device_set_desc(dev, "Generic IEEE 802.3u media interface");
|
||||
return (BUS_PROBE_GENERIC);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &ukphy_funcs, 1);
|
||||
mii_phy_setmedia(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
PHY_STATUS(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
@@ -0,0 +1,129 @@
|
||||
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: releng/11.1/sys/dev/mii/ukphy_subr.c 215297 2010-11-14 13:26:10Z marius $");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
/*
|
||||
* Media status subroutine. If a PHY driver does media detection simply
|
||||
* by decoding the NWay autonegotiation, use this routine.
|
||||
*/
|
||||
void
|
||||
ukphy_status(struct mii_softc *phy)
|
||||
{
|
||||
struct mii_data *mii = phy->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, anlpar, gtcr, gtsr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(phy, MII_BMCR);
|
||||
if (bmcr & BMCR_ISO) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (bmcr & BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & BMCR_AUTOEN) {
|
||||
/*
|
||||
* NWay autonegotiation takes the highest-order common
|
||||
* bit of the ANAR and ANLPAR (i.e. best media advertised
|
||||
* both by us and our link partner).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||
(phy->mii_extcapabilities &
|
||||
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||
} else
|
||||
gtcr = gtsr = 0;
|
||||
|
||||
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_HDX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_HDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
|
||||
if ((mii->mii_media_active & IFM_1000_T) != 0 &&
|
||||
(gtsr & GTSR_MS_RES) != 0)
|
||||
mii->mii_media_active |= IFM_ETH_MASTER;
|
||||
|
||||
if ((mii->mii_media_active & IFM_FDX) != 0)
|
||||
mii->mii_media_active |= mii_phy_flowstatus(phy);
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,542 @@
|
||||
/*-
|
||||
* Copyright (c) 1997, 1998, 1999
|
||||
* Bill Paul <[email protected]>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Register definitions for the SiS 900 and SiS 7016 chipsets. The
|
||||
* 7016 is actually an older chip and some of its registers differ
|
||||
* from the 900, however the core operational registers are the same:
|
||||
* the differences lie in the OnNow/Wake on LAN stuff which we don't
|
||||
* use anyway. The 7016 needs an external MII compliant PHY while the
|
||||
* SiS 900 has one built in. All registers are 32-bits wide.
|
||||
*/
|
||||
|
||||
/* Registers common to SiS 900 and SiS 7016 */
|
||||
#define SIS_CSR 0x00
|
||||
#define SIS_CFG 0x04
|
||||
#define SIS_EECTL 0x08
|
||||
#define SIS_PCICTL 0x0C
|
||||
#define SIS_ISR 0x10
|
||||
#define SIS_IMR 0x14
|
||||
#define SIS_IER 0x18
|
||||
#define SIS_PHYCTL 0x1C
|
||||
#define SIS_TX_LISTPTR 0x20
|
||||
#define SIS_TX_CFG 0x24
|
||||
#define SIS_RX_LISTPTR 0x30
|
||||
#define SIS_RX_CFG 0x34
|
||||
#define SIS_FLOWCTL 0x38
|
||||
#define SIS_RXFILT_CTL 0x48
|
||||
#define SIS_RXFILT_DATA 0x4C
|
||||
#define SIS_PWRMAN_CTL 0xB0
|
||||
#define SIS_PWERMAN_WKUP_EVENT 0xB4
|
||||
#define SIS_WKUP_FRAME_CRC 0xBC
|
||||
#define SIS_WKUP_FRAME_MASK0 0xC0
|
||||
#define SIS_WKUP_FRAME_MASKXX 0xEC
|
||||
|
||||
/* SiS 7016 specific registers */
|
||||
#define SIS_SILICON_REV 0x5C
|
||||
#define SIS_MIB_CTL0 0x60
|
||||
#define SIS_MIB_CTL1 0x64
|
||||
#define SIS_MIB_CTL2 0x68
|
||||
#define SIS_MIB_CTL3 0x6C
|
||||
#define SIS_MIB 0x80
|
||||
#define SIS_LINKSTS 0xA0
|
||||
#define SIS_TIMEUNIT 0xA4
|
||||
#define SIS_GPIO 0xB8
|
||||
|
||||
/* NS DP83815/6 registers */
|
||||
#define NS_IHR 0x1C
|
||||
#define NS_CLKRUN 0x3C
|
||||
#define NS_WCSR 0x40
|
||||
#define NS_SRR 0x58
|
||||
#define NS_BMCR 0x80
|
||||
#define NS_BMSR 0x84
|
||||
#define NS_PHYIDR1 0x88
|
||||
#define NS_PHYIDR2 0x8C
|
||||
#define NS_ANAR 0x90
|
||||
#define NS_ANLPAR 0x94
|
||||
#define NS_ANER 0x98
|
||||
#define NS_ANNPTR 0x9C
|
||||
|
||||
#define NS_PHY_CR 0xE4
|
||||
#define NS_PHY_10BTSCR 0xE8
|
||||
#define NS_PHY_PAGE 0xCC
|
||||
#define NS_PHY_EXTCFG 0xF0
|
||||
#define NS_PHY_DSPCFG 0xF4
|
||||
#define NS_PHY_SDCFG 0xF8
|
||||
#define NS_PHY_TDATA 0xFC
|
||||
|
||||
#define NS_CLKRUN_PMESTS 0x00008000
|
||||
#define NS_CLKRUN_PMEENB 0x00000100
|
||||
#define NS_CLNRUN_CLKRUN_ENB 0x00000001
|
||||
|
||||
#define NS_WCSR_WAKE_PHYINTR 0x00000001
|
||||
#define NS_WCSR_WAKE_UCAST 0x00000002
|
||||
#define NS_WCSR_WAKE_MCAST 0x00000004
|
||||
#define NS_WCSR_WAKE_BCAST 0x00000008
|
||||
#define NS_WCSR_WAKE_ARP 0x00000010
|
||||
#define NS_WCSR_WAKE_PATTERN0 0x00000020
|
||||
#define NS_WCSR_WAKE_PATTERN1 0x00000040
|
||||
#define NS_WCSR_WAKE_PATTERN2 0x00000080
|
||||
#define NS_WCSR_WAKE_PATTERN3 0x00000100
|
||||
#define NS_WCSR_WAKE_MAGIC 0x00000200
|
||||
#define NS_WCSR_WAKE_MAGIC_SEC 0x00000400
|
||||
#define NS_WCSR_DET_MAGIC_SECH 0x00100000
|
||||
#define NS_WCSR_DET_PHYINTR 0x00400000
|
||||
#define NS_WCSR_DET_UCAST 0x00800000
|
||||
#define NS_WCSR_DET_MCAST 0x01000000
|
||||
#define NS_WCSR_DET_BCAST 0x02000000
|
||||
#define NS_WCSR_DET_ARP 0x04000000
|
||||
#define NS_WCSR_DET_PATTERN0 0x08000000
|
||||
#define NS_WCSR_DET_PATTERN1 0x10000000
|
||||
#define NS_WCSR_DET_PATTERN2 0x20000000
|
||||
#define NS_WCSR_DET_PATTERN3 0x40000000
|
||||
#define NS_WCSR_DET_MAGIC 0x80000000
|
||||
|
||||
/* NS silicon revisions */
|
||||
#define NS_SRR_15C 0x302
|
||||
#define NS_SRR_15D 0x403
|
||||
#define NS_SRR_16A 0x505
|
||||
|
||||
#define SIS_CSR_TX_ENABLE 0x00000001
|
||||
#define SIS_CSR_TX_DISABLE 0x00000002
|
||||
#define SIS_CSR_RX_ENABLE 0x00000004
|
||||
#define SIS_CSR_RX_DISABLE 0x00000008
|
||||
#define SIS_CSR_TX_RESET 0x00000010
|
||||
#define SIS_CSR_RX_RESET 0x00000020
|
||||
#define SIS_CSR_SOFTINTR 0x00000080
|
||||
#define SIS_CSR_RESET 0x00000100
|
||||
#define SIS_CSR_ACCESS_MODE 0x00000200
|
||||
#define SIS_CSR_RELOAD 0x00000400
|
||||
|
||||
#define SIS_CFG_BIGENDIAN 0x00000001
|
||||
#define SIS_CFG_PERR_DETECT 0x00000008
|
||||
#define SIS_CFG_DEFER_DISABLE 0x00000010
|
||||
#define SIS_CFG_OUTOFWIN_TIMER 0x00000020
|
||||
#define SIS_CFG_SINGLE_BACKOFF 0x00000040
|
||||
#define SIS_CFG_PCIREQ_ALG 0x00000080
|
||||
#define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */
|
||||
#define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */
|
||||
#define SIS_CFG_EDB_MASTER_EN 0x00002000
|
||||
|
||||
#define SIS_EECTL_DIN 0x00000001
|
||||
#define SIS_EECTL_DOUT 0x00000002
|
||||
#define SIS_EECTL_CLK 0x00000004
|
||||
#define SIS_EECTL_CSEL 0x00000008
|
||||
|
||||
#define SIS_MII_CLK 0x00000040
|
||||
#define SIS_MII_DIR 0x00000020
|
||||
#define SIS_MII_DATA 0x00000010
|
||||
|
||||
#define SIS_EECMD_WRITE 0x140
|
||||
#define SIS_EECMD_READ 0x180
|
||||
#define SIS_EECMD_ERASE 0x1c0
|
||||
|
||||
/*
|
||||
* EEPROM Commands for SiS96x
|
||||
* chipsets.
|
||||
*/
|
||||
#define SIS_EECMD_REQ 0x00000400
|
||||
#define SIS_EECMD_DONE 0x00000200
|
||||
#define SIS_EECMD_GNT 0x00000100
|
||||
|
||||
#define SIS_EE_NODEADDR 0x8
|
||||
#define NS_EE_NODEADDR 0x6
|
||||
|
||||
#define SIS_PCICTL_SRAMADDR 0x0000001F
|
||||
#define SIS_PCICTL_RAMTSTENB 0x00000020
|
||||
#define SIS_PCICTL_TXTSTENB 0x00000040
|
||||
#define SIS_PCICTL_RXTSTENB 0x00000080
|
||||
#define SIS_PCICTL_BMTSTENB 0x00000200
|
||||
#define SIS_PCICTL_RAMADDR 0x001F0000
|
||||
#define SIS_PCICTL_ROMTIME 0x0F000000
|
||||
#define SIS_PCICTL_DISCTEST 0x40000000
|
||||
|
||||
#define SIS_ISR_RX_OK 0x00000001
|
||||
#define SIS_ISR_RX_DESC_OK 0x00000002
|
||||
#define SIS_ISR_RX_ERR 0x00000004
|
||||
#define SIS_ISR_RX_EARLY 0x00000008
|
||||
#define SIS_ISR_RX_IDLE 0x00000010
|
||||
#define SIS_ISR_RX_OFLOW 0x00000020
|
||||
#define SIS_ISR_TX_OK 0x00000040
|
||||
#define SIS_ISR_TX_DESC_OK 0x00000080
|
||||
#define SIS_ISR_TX_ERR 0x00000100
|
||||
#define SIS_ISR_TX_IDLE 0x00000200
|
||||
#define SIS_ISR_TX_UFLOW 0x00000400
|
||||
#define SIS_ISR_SOFTINTR 0x00000800
|
||||
#define SIS_ISR_HIBITS 0x00008000
|
||||
#define SIS_ISR_RX_FIFO_OFLOW 0x00010000
|
||||
#define SIS_ISR_TGT_ABRT 0x00100000
|
||||
#define SIS_ISR_BM_ABRT 0x00200000
|
||||
#define SIS_ISR_SYSERR 0x00400000
|
||||
#define SIS_ISR_PARITY_ERR 0x00800000
|
||||
#define SIS_ISR_RX_RESET_DONE 0x01000000
|
||||
#define SIS_ISR_TX_RESET_DONE 0x02000000
|
||||
#define SIS_ISR_TX_PAUSE_START 0x04000000
|
||||
#define SIS_ISR_TX_PAUSE_DONE 0x08000000
|
||||
#define SIS_ISR_WAKE_EVENT 0x10000000
|
||||
|
||||
#define SIS_IMR_RX_OK 0x00000001
|
||||
#define SIS_IMR_RX_DESC_OK 0x00000002
|
||||
#define SIS_IMR_RX_ERR 0x00000004
|
||||
#define SIS_IMR_RX_EARLY 0x00000008
|
||||
#define SIS_IMR_RX_IDLE 0x00000010
|
||||
#define SIS_IMR_RX_OFLOW 0x00000020
|
||||
#define SIS_IMR_TX_OK 0x00000040
|
||||
#define SIS_IMR_TX_DESC_OK 0x00000080
|
||||
#define SIS_IMR_TX_ERR 0x00000100
|
||||
#define SIS_IMR_TX_IDLE 0x00000200
|
||||
#define SIS_IMR_TX_UFLOW 0x00000400
|
||||
#define SIS_IMR_SOFTINTR 0x00000800
|
||||
#define SIS_IMR_HIBITS 0x00008000
|
||||
#define SIS_IMR_RX_FIFO_OFLOW 0x00010000
|
||||
#define SIS_IMR_TGT_ABRT 0x00100000
|
||||
#define SIS_IMR_BM_ABRT 0x00200000
|
||||
#define SIS_IMR_SYSERR 0x00400000
|
||||
#define SIS_IMR_PARITY_ERR 0x00800000
|
||||
#define SIS_IMR_RX_RESET_DONE 0x01000000
|
||||
#define SIS_IMR_TX_RESET_DONE 0x02000000
|
||||
#define SIS_IMR_TX_PAUSE_START 0x04000000
|
||||
#define SIS_IMR_TX_PAUSE_DONE 0x08000000
|
||||
#define SIS_IMR_WAKE_EVENT 0x10000000
|
||||
|
||||
#define SIS_INTRS \
|
||||
(SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\
|
||||
SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\
|
||||
SIS_IMR_RX_IDLE|\
|
||||
SIS_IMR_SYSERR)
|
||||
|
||||
#define SIS_IER_INTRENB 0x00000001
|
||||
|
||||
#define SIS_PHYCTL_ACCESS 0x00000010
|
||||
#define SIS_PHYCTL_OP 0x00000020
|
||||
#define SIS_PHYCTL_REGADDR 0x000007C0
|
||||
#define SIS_PHYCTL_PHYADDR 0x0000F800
|
||||
#define SIS_PHYCTL_PHYDATA 0xFFFF0000
|
||||
|
||||
#define SIS_PHYOP_READ 0x00000020
|
||||
#define SIS_PHYOP_WRITE 0x00000000
|
||||
|
||||
#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */
|
||||
#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */
|
||||
#define SIS_TXCFG_DMABURST 0x00700000
|
||||
#define SIS_TXCFG_AUTOPAD 0x10000000
|
||||
#define SIS_TXCFG_LOOPBK 0x20000000
|
||||
#define SIS_TXCFG_IGN_HBEAT 0x40000000
|
||||
#define SIS_TXCFG_IGN_CARR 0x80000000
|
||||
|
||||
#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH)
|
||||
#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH)
|
||||
|
||||
#define SIS_TXDMA_512BYTES 0x00000000
|
||||
#define SIS_TXDMA_4BYTES 0x00100000
|
||||
#define SIS_TXDMA_8BYTES 0x00200000
|
||||
#define SIS_TXDMA_16BYTES 0x00300000
|
||||
#define SIS_TXDMA_32BYTES 0x00400000
|
||||
#define SIS_TXDMA_64BYTES 0x00500000
|
||||
#define SIS_TXDMA_128BYTES 0x00600000
|
||||
#define SIS_TXDMA_256BYTES 0x00700000
|
||||
|
||||
#define SIS_TXCFG_100 \
|
||||
(SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
|
||||
SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
|
||||
|
||||
#define SIS_TXCFG_10 \
|
||||
(SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
|
||||
SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
|
||||
|
||||
#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
|
||||
#define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */
|
||||
#define SIS_RXCFG_DMABURST 0x00700000
|
||||
#define SIS_RXCFG_RX_JABBER 0x08000000
|
||||
#define SIS_RXCFG_RX_TXPKTS 0x10000000
|
||||
#define SIS_RXCFG_RX_RUNTS 0x40000000
|
||||
#define SIS_RXCFG_RX_GIANTS 0x80000000
|
||||
|
||||
#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH)
|
||||
|
||||
#define SIS_RXDMA_512BYTES 0x00000000
|
||||
#define SIS_RXDMA_4BYTES 0x00100000
|
||||
#define SIS_RXDMA_8BYTES 0x00200000
|
||||
#define SIS_RXDMA_16BYTES 0x00300000
|
||||
#define SIS_RXDMA_32BYTES 0x00400000
|
||||
#define SIS_RXDMA_64BYTES 0x00500000
|
||||
#define SIS_RXDMA_128BYTES 0x00600000
|
||||
#define SIS_RXDMA_256BYTES 0x00700000
|
||||
|
||||
#define SIS_RXCFG256 \
|
||||
(SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
|
||||
#define SIS_RXCFG64 \
|
||||
(SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES)
|
||||
|
||||
#define SIS_RXFILTCTL_ADDR 0x000F0000
|
||||
#define NS_RXFILTCTL_MCHASH 0x00200000
|
||||
#define NS_RXFILTCTL_ARP 0x00400000
|
||||
#define NS_RXFILTCTL_PERFECT 0x08000000
|
||||
#define SIS_RXFILTCTL_ALLPHYS 0x10000000
|
||||
#define SIS_RXFILTCTL_ALLMULTI 0x20000000
|
||||
#define SIS_RXFILTCTL_BROAD 0x40000000
|
||||
#define SIS_RXFILTCTL_ENABLE 0x80000000
|
||||
|
||||
#define SIS_FILTADDR_PAR0 0x00000000
|
||||
#define SIS_FILTADDR_PAR1 0x00010000
|
||||
#define SIS_FILTADDR_PAR2 0x00020000
|
||||
#define SIS_FILTADDR_MAR0 0x00040000
|
||||
#define SIS_FILTADDR_MAR1 0x00050000
|
||||
#define SIS_FILTADDR_MAR2 0x00060000
|
||||
#define SIS_FILTADDR_MAR3 0x00070000
|
||||
#define SIS_FILTADDR_MAR4 0x00080000
|
||||
#define SIS_FILTADDR_MAR5 0x00090000
|
||||
#define SIS_FILTADDR_MAR6 0x000A0000
|
||||
#define SIS_FILTADDR_MAR7 0x000B0000
|
||||
|
||||
#define NS_FILTADDR_PAR0 0x00000000
|
||||
#define NS_FILTADDR_PAR1 0x00000002
|
||||
#define NS_FILTADDR_PAR2 0x00000004
|
||||
|
||||
#define NS_FILTADDR_FMEM_LO 0x00000200
|
||||
#define NS_FILTADDR_FMEM_HI 0x000003FE
|
||||
|
||||
#define SIS_PWRMAN_WOL_LINK_OFF 0x00000001
|
||||
#define SIS_PWRMAN_WOL_LINK_ON 0x00000002
|
||||
#define SIS_PWRMAN_WOL_MAGIC 0x00000400
|
||||
|
||||
/*
|
||||
* TX/RX DMA descriptor structures.
|
||||
*/
|
||||
struct sis_desc {
|
||||
/* SiS hardware descriptor section */
|
||||
uint32_t sis_next;
|
||||
volatile uint32_t sis_cmdsts;
|
||||
volatile uint32_t sis_ptr;
|
||||
};
|
||||
|
||||
#define SIS_CMDSTS_BUFLEN 0x00000FFF
|
||||
#define SIS_CMDSTS_PKT_OK 0x08000000
|
||||
#define SIS_CMDSTS_CRC 0x10000000
|
||||
#define SIS_CMDSTS_INTR 0x20000000
|
||||
#define SIS_CMDSTS_MORE 0x40000000
|
||||
#define SIS_CMDSTS_OWN 0x80000000
|
||||
|
||||
#define SIS_RXSTAT_COLL 0x00010000
|
||||
#define SIS_RXSTAT_LOOPBK 0x00020000
|
||||
#define SIS_RXSTAT_ALIGNERR 0x00040000
|
||||
#define SIS_RXSTAT_CRCERR 0x00080000
|
||||
#define SIS_RXSTAT_SYMBOLERR 0x00100000
|
||||
#define SIS_RXSTAT_RUNT 0x00200000
|
||||
#define SIS_RXSTAT_GIANT 0x00400000
|
||||
#define SIS_RXSTAT_DSTCLASS 0x01800000
|
||||
#define SIS_RXSTAT_OVERRUN 0x02000000
|
||||
#define SIS_RXSTAT_RX_ABORT 0x04000000
|
||||
|
||||
#define SIS_RXSTAT_ERROR(x) \
|
||||
((x) & (SIS_RXSTAT_RX_ABORT | SIS_RXSTAT_OVERRUN | \
|
||||
SIS_RXSTAT_GIANT | SIS_RXSTAT_SYMBOLERR | SIS_RXSTAT_RUNT | \
|
||||
SIS_RXSTAT_CRCERR | SIS_RXSTAT_ALIGNERR))
|
||||
|
||||
#define SIS_DSTCLASS_REJECT 0x00000000
|
||||
#define SIS_DSTCLASS_UNICAST 0x00800000
|
||||
#define SIS_DSTCLASS_MULTICAST 0x01000000
|
||||
#define SIS_DSTCLASS_BROADCAST 0x02000000
|
||||
|
||||
#define SIS_TXSTAT_COLLCNT 0x000F0000
|
||||
#define SIS_TXSTAT_EXCESSCOLLS 0x00100000
|
||||
#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000
|
||||
#define SIS_TXSTAT_EXCESS_DEFER 0x00400000
|
||||
#define SIS_TXSTAT_DEFERED 0x00800000
|
||||
#define SIS_TXSTAT_CARR_LOST 0x01000000
|
||||
#define SIS_TXSTAT_UNDERRUN 0x02000000
|
||||
#define SIS_TXSTAT_TX_ABORT 0x04000000
|
||||
|
||||
#define SIS_DESC_ALIGN 16
|
||||
#define SIS_RX_BUF_ALIGN 4
|
||||
#define SIS_MAXTXSEGS 16
|
||||
#define SIS_RX_LIST_CNT 64
|
||||
#define SIS_TX_LIST_CNT 128
|
||||
|
||||
#define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc)
|
||||
#define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc)
|
||||
|
||||
#define SIS_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff)
|
||||
#define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32)
|
||||
|
||||
#define SIS_RX_RING_ADDR(sc, i) \
|
||||
((sc)->sis_rx_paddr + sizeof(struct sis_desc) * (i))
|
||||
#define SIS_TX_RING_ADDR(sc, i) \
|
||||
((sc)->sis_tx_paddr + sizeof(struct sis_desc) * (i))
|
||||
|
||||
#define SIS_INC(x, y) (x) = (x + 1) % (y)
|
||||
|
||||
#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
|
||||
|
||||
#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
|
||||
|
||||
/*
|
||||
* SiS PCI vendor ID.
|
||||
*/
|
||||
#define SIS_VENDORID 0x1039
|
||||
|
||||
/*
|
||||
* SiS PCI device IDs
|
||||
*/
|
||||
#define SIS_DEVICEID_900 0x0900
|
||||
#define SIS_DEVICEID_7016 0x7016
|
||||
|
||||
/*
|
||||
* SiS 900 PCI revision codes.
|
||||
*/
|
||||
#define SIS_REV_900B 0x0003
|
||||
#define SIS_REV_630A 0x0080
|
||||
#define SIS_REV_630E 0x0081
|
||||
#define SIS_REV_630S 0x0082
|
||||
#define SIS_REV_630EA1 0x0083
|
||||
#define SIS_REV_630ET 0x0084
|
||||
#define SIS_REV_635 0x0090
|
||||
#define SIS_REV_96x 0x0091
|
||||
|
||||
/*
|
||||
* NatSemi vendor ID
|
||||
*/
|
||||
#define NS_VENDORID 0x100B
|
||||
|
||||
/*
|
||||
* DP83815 device ID
|
||||
*/
|
||||
#define NS_DEVICEID_DP83815 0x0020
|
||||
|
||||
struct sis_type {
|
||||
uint16_t sis_vid;
|
||||
uint16_t sis_did;
|
||||
const char *sis_name;
|
||||
};
|
||||
|
||||
#define SIS_TYPE_900 1
|
||||
#define SIS_TYPE_7016 2
|
||||
#define SIS_TYPE_83815 3
|
||||
|
||||
struct sis_txdesc {
|
||||
struct mbuf *tx_m;
|
||||
bus_dmamap_t tx_dmamap;
|
||||
};
|
||||
|
||||
struct sis_rxdesc {
|
||||
struct mbuf *rx_m;
|
||||
bus_dmamap_t rx_dmamap;
|
||||
struct sis_desc *rx_desc;
|
||||
};
|
||||
|
||||
struct sis_softc {
|
||||
struct ifnet *sis_ifp; /* interface info */
|
||||
struct resource *sis_res[2];
|
||||
void *sis_intrhand;
|
||||
device_t sis_dev;
|
||||
device_t sis_miibus;
|
||||
uint8_t sis_type;
|
||||
uint8_t sis_rev;
|
||||
uint32_t sis_flags;
|
||||
#define SIS_FLAG_MANUAL_PAD 0x0800
|
||||
#define SIS_FLAG_LINK 0x8000
|
||||
int sis_manual_pad;
|
||||
uint32_t sis_srr;
|
||||
struct sis_desc *sis_rx_list;
|
||||
struct sis_desc *sis_tx_list;
|
||||
bus_dma_tag_t sis_rx_list_tag;
|
||||
bus_dmamap_t sis_rx_list_map;
|
||||
bus_dma_tag_t sis_tx_list_tag;
|
||||
bus_dmamap_t sis_tx_list_map;
|
||||
bus_dma_tag_t sis_parent_tag;
|
||||
bus_dma_tag_t sis_rx_tag;
|
||||
bus_dmamap_t sis_rx_sparemap;
|
||||
bus_dma_tag_t sis_tx_tag;
|
||||
struct sis_rxdesc sis_rxdesc[SIS_RX_LIST_CNT];
|
||||
struct sis_txdesc sis_txdesc[SIS_TX_LIST_CNT];
|
||||
int sis_tx_prod;
|
||||
int sis_tx_cons;
|
||||
int sis_tx_cnt;
|
||||
int sis_rx_cons;
|
||||
bus_addr_t sis_rx_paddr;
|
||||
bus_addr_t sis_tx_paddr;
|
||||
struct callout sis_stat_ch;
|
||||
int sis_watchdog_timer;
|
||||
int sis_if_flags;
|
||||
#ifdef DEVICE_POLLING
|
||||
int rxcycles;
|
||||
#endif
|
||||
struct mtx sis_mtx;
|
||||
#ifdef __HAIKU__
|
||||
uint32_t haiku_interrupt_status;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define SIS_TIMEOUT 1000
|
||||
#define ETHER_ALIGN 2
|
||||
#define SIS_RXLEN 1536
|
||||
#define SIS_MIN_FRAMELEN 60
|
||||
|
||||
/*
|
||||
* PCI low memory base and low I/O base register, and
|
||||
* other PCI registers.
|
||||
*/
|
||||
|
||||
#define SIS_PCI_VENDOR_ID 0x00
|
||||
#define SIS_PCI_DEVICE_ID 0x02
|
||||
#define SIS_PCI_COMMAND 0x04
|
||||
#define SIS_PCI_STATUS 0x06
|
||||
#define SIS_PCI_REVID 0x08
|
||||
#define SIS_PCI_CLASSCODE 0x09
|
||||
#define SIS_PCI_CACHELEN 0x0C
|
||||
#define SIS_PCI_LATENCY_TIMER 0x0D
|
||||
#define SIS_PCI_HEADER_TYPE 0x0E
|
||||
#define SIS_PCI_LOIO 0x10
|
||||
#define SIS_PCI_LOMEM 0x14
|
||||
#define SIS_PCI_BIOSROM 0x30
|
||||
#define SIS_PCI_INTLINE 0x3C
|
||||
#define SIS_PCI_INTPIN 0x3D
|
||||
#define SIS_PCI_MINGNT 0x3E
|
||||
#define SIS_PCI_MINLAT 0x0F
|
||||
#define SIS_PCI_RESETOPT 0x48
|
||||
#define SIS_PCI_EEPROM_DATA 0x4C
|
||||
|
||||
/* power management registers */
|
||||
#define SIS_PCI_CAPID 0x50 /* 8 bits */
|
||||
#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */
|
||||
#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */
|
||||
#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
|
||||
|
||||
#define SIS_PSTATE_MASK 0x0003
|
||||
#define SIS_PSTATE_D0 0x0000
|
||||
#define SIS_PSTATE_D1 0x0001
|
||||
#define SIS_PSTATE_D2 0x0002
|
||||
#define SIS_PSTATE_D3 0x0003
|
||||
#define SIS_PME_EN 0x0010
|
||||
#define SIS_PME_STATUS 0x8000
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright 2018, Haiku, Inc. All rights reserved.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/sis/if_sisreg.h>
|
||||
|
||||
|
||||
HAIKU_FBSD_DRIVER_GLUE(sis900, sis, pci);
|
||||
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE);
|
||||
NO_HAIKU_REENABLE_INTERRUPTS();
|
||||
|
||||
|
||||
extern driver_t* DRIVER_MODULE_NAME(icsphy, miibus);
|
||||
extern driver_t* DRIVER_MODULE_NAME(nsphyter, miibus);
|
||||
extern driver_t* DRIVER_MODULE_NAME(ukphy, miibus);
|
||||
|
||||
|
||||
driver_t *
|
||||
__haiku_select_miibus_driver(device_t dev)
|
||||
{
|
||||
driver_t *drivers[] = {
|
||||
DRIVER_MODULE_NAME(icsphy, miibus),
|
||||
DRIVER_MODULE_NAME(nsphyter, miibus),
|
||||
DRIVER_MODULE_NAME(ukphy, miibus),
|
||||
NULL
|
||||
};
|
||||
|
||||
return __haiku_probe_miibus(dev, drivers);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
|
||||
{
|
||||
struct sis_softc *sc = device_get_softc(dev);
|
||||
uint32_t status;
|
||||
|
||||
/* Reading the ISR register clears all interrupts. */
|
||||
status = CSR_READ_4(sc, SIS_ISR);
|
||||
if ((status & SIS_INTRS) == 0) {
|
||||
/* Not ours. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Disable interrupts. */
|
||||
CSR_WRITE_4(sc, SIS_IER, 0);
|
||||
|
||||
sc->haiku_interrupt_status = status;
|
||||
return 1;
|
||||
}
|
||||
Reference in New Issue
Block a user