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* some methods to access stream registers were defined with wrong types

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* use HDAC_BIDIR_STREAM_OFFSET and HDAC_OUTPUT_STREAM_OFFSET when applicable
* use a PAGE_ALIGN macro


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26330 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
2008-07-08 21:48:50 +00:00
parent f67bbdb2a6
commit 3787196a5a
2 changed files with 14 additions and 12 deletions
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src/add-ons/kernel/drivers/audio/hda/driver.h
+5 -5
View File
@@ -149,8 +149,8 @@ struct hda_stream {
/* Physical addresses for buffer */
sem_id buffer_ready_sem;
bigtime_t real_time;
uint32 frames_count;
uint32 buffer_cycle;
uint64 frames_count;
int32 buffer_cycle;
uint32 rate, bps; /* Samplerate & bits per sample */
@@ -168,7 +168,7 @@ struct hda_stream {
return controller->Read16(HDAC_STREAM_BASE + offset + reg);
}
uint8 Read32(uint32 reg)
uint32 Read32(uint32 reg)
{
return controller->Read32(HDAC_STREAM_BASE + offset + reg);
}
@@ -178,12 +178,12 @@ struct hda_stream {
*(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
}
void Write16(uint32 reg, uint8 value)
void Write16(uint32 reg, uint16 value)
{
*(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
}
void Write32(uint32 reg, uint8 value)
void Write32(uint32 reg, uint32 value)
{
*(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
}
src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp
+9 -7
View File
@@ -26,6 +26,8 @@
(((controller)->num_input_streams + (controller)->num_output_streams \
+ (index)) * HDAC_STREAM_SIZE)
#define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1))
static const struct {
uint32 multi_rate;
uint32 hw_rate;
@@ -197,15 +199,15 @@ reset_controller(hda_controller* controller)
}
for (uint32 i = 0; i < controller->num_output_streams; i++) {
controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
+ HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0);
controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
+ HDAC_OUTPUT_STREAM_OFFSET(controller, i), 0);
}
for (uint32 i = 0; i < controller->num_bidir_streams; i++) {
controller->Write8(HDAC_STREAM_CONTROL0 + HDAC_STREAM_BASE
+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
+ HDAC_BIDIR_STREAM_OFFSET(controller, i), 0);
controller->Write8(HDAC_STREAM_STATUS + HDAC_STREAM_BASE
+ HDAC_INPUT_STREAM_OFFSET(controller, i), 0);
+ HDAC_BIDIR_STREAM_OFFSET(controller, i), 0);
}
// stop DMA
@@ -305,7 +307,7 @@ init_corb_rirb_pos(hda_controller* controller)
posSize = 8 * (controller->num_input_streams
+ controller->num_output_streams + controller->num_bidir_streams);
memSize = (posOffset + posSize + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
memSize = PAGE_ALIGN(posOffset + posSize);
/* Allocate memory area */
controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos",
@@ -504,7 +506,7 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
/* Calculate total size of all buffers (aligned to size of B_PAGE_SIZE) */
alloc = bufferSize * stream->num_buffers;
alloc = (alloc + B_PAGE_SIZE - 1) & (~(B_PAGE_SIZE -1));
alloc = PAGE_ALIGN(alloc);
/* Allocate memory for buffers */
stream->buffer_area = create_area("hda buffers", (void**)&buffer,
@@ -533,7 +535,7 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
/* Now allocate BDL for buffer range */
alloc = stream->num_buffers * sizeof(bdl_entry_t);
alloc = (alloc + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
alloc = PAGE_ALIGN(alloc);
stream->buffer_descriptors_area = create_area("hda buffer descriptors",
(void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc,