i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

expanded CRTC1 FIFO watermark/burst programming: only using if coldstarted, and only on TNT2-M64. Minimizes output distortions on this card. Other cards seem fast enough to not need this (still checking..)

Browse Source 
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12602 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-05-09 11:23:28 +00:00
parent 82581f548d
commit 3c4c050540
2 changed files with 61 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/accelerants/nvidia/SetDisplayMode.c
+6 -4
View File
@@ -6,7 +6,7 @@
Other authors:
Mark Watson,
Apsed,
Rudolf Cornelissen 11/2002-4/2005
Rudolf Cornelissen 11/2002-5/2005
*/
#define MODULE_BIT 0x00200000
@@ -311,6 +311,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* update driver's mode store */
si->dm = target;
/* update FIFO data fetching according to mode */
nv_crtc_update_fifo();
/* turn screen one on */
head1_dpms(display, h, v);
/* turn screen two on if a dualhead mode is active */
@@ -318,9 +321,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* set up acceleration for this mode */
/* note:
* attempting DMA on NV40 and higher because without it I can't get it going ATM.
* Later on this can become a nv.settings switch, and maybe later we can even
* forget about non-DMA completely (depends on 3D acceleration attempts). */
* Maybe later we can forget about non-DMA mode (depends on 3D acceleration
* attempts). */
if (!si->settings.dma_acc)
nv_acc_init();
else
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
+55 -8
View File
@@ -11,25 +11,72 @@
//fixme: this is a _very_ basic setup, and it's preliminary...
status_t nv_crtc_update_fifo()
{
uint8 bytes_per_pixel = 1;
uint32 drain;
/* we are only using this on coldstarted cards which really need this */
if ((si->settings.usebios) || (si->ps.card_arch != NV04A)) return B_OK;
if ((si->settings.usebios) || (si->ps.card_type != NV05M64)) return B_OK;
/* enable access to primary head */
set_crtc_owner(0);
/* set CRTC FIFO burst size to 256 (is BIOS default) */
CRTCW(FIFO, 0x03);
/* set CRTC FIFO low watermark according to mode */
if ((si->dm.timing.h_display * si->dm.timing.v_display) > (1280 * 1024))
/* set CRTC FIFO low watermark according to memory drain */
switch(si->dm.space)
{
case B_CMAP8:
bytes_per_pixel = 1;
break;
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
bytes_per_pixel = 2;
break;
case B_RGB24_LITTLE:
bytes_per_pixel = 3;
break;
case B_RGB32_LITTLE:
bytes_per_pixel = 4;
break;
}
/* fixme:
* - I should probably include the refreshrate as well;
* - and the memory clocking speed, core clocking speed, RAM buswidth.. */
drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;
/* Doesn't work for other than 32bit space (yet?) */
if (si->dm.space != B_RGB32_LITTLE)
{
/* BIOS defaults */
CRTCW(FIFO, 0x03);
CRTCW(FIFO_LWM, 0x20);
LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
return B_OK;
}
if (drain > (((uint32)1280) * 1024 * 4))
{
/* set CRTC FIFO burst size for 'smaller' bursts */
CRTCW(FIFO, 0x01);
/* Instruct CRTC to fetch new data 'earlier' */
CRTCW(FIFO_LWM, 0x40);
LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 64\n"));
}
else
{
/* BIOS default */
CRTCW(FIFO_LWM, 0x20);
if (drain > (((uint32)1024) * 768 * 4))
{
/* BIOS default */
CRTCW(FIFO, 0x02);
/* Instruct CRTC to fetch new data 'earlier' */
CRTCW(FIFO_LWM, 0x40);
LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 128\n"));
}
else
{
/* BIOS defaults */
CRTCW(FIFO, 0x03);
CRTCW(FIFO_LWM, 0x20);
LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
}
}
return B_OK;