Applied patch by Euan Kirkhope:
* Imported FreeBSD driver "sk" as syskonnect into the Haiku tree, and wrote the necessary glue code to let it run. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@24723 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
@@ -19,6 +19,7 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect ;
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SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
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SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;
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@@ -0,0 +1,3 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network syskonnect ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect dev ;
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@@ -0,0 +1,4 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network syskonnect dev ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect dev mii ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect dev sk ;
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@@ -0,0 +1,17 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network syskonnect dev mii ;
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UsePrivateHeaders kernel net ;
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UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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KernelStaticLibrary syskonnect_mii.a
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:
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xmphy.c
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e1000phy.c
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ukphy.c
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ukphy_subr.c
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;
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@@ -0,0 +1,364 @@
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/*-
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* Copyright (c) 2000
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* Bill Paul <[email protected]>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.6.2.2 2007/06/14 21:07:19 davidch Exp $
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*/
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#ifndef _DEV_MII_BRGPHYREG_H_
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#define _DEV_MII_BRGPHYREG_H_
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/*
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* Broadcom BCM5400 registers
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*/
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#define BRGPHY_MII_BMCR 0x00
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#define BRGPHY_BMCR_RESET 0x8000
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#define BRGPHY_BMCR_LOOP 0x4000
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#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
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#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
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#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
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#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
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#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
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#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
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#define BRGPHY_S10 0 /* 10mbps */
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#define BRGPHY_MII_BMSR 0x01
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#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
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#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
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#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define BRGPHY_BMSR_LINK 0x0004 /* Link status */
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#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
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#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */
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#define BRGPHY_MII_ANAR 0x04
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#define BRGPHY_ANAR_NP 0x8000 /* Next page */
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#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */
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#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
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#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */
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#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */
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#define BRGPHY_MII_ANLPAR 0x05
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#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */
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#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */
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#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
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#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */
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#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */
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#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */
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#define BRGPHY_MII_ANER 0x06
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#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
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#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define BRGPHY_ANER_RX 0x0002 /* Next page received */
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#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
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#define BRGPHY_MII_NEXTP 0x07 /* Next page */
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#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
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#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */
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#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */
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#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */
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#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */
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#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
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#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */
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#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
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#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */
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#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */
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#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
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#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
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#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
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#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */
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#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */
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#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
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#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
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#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
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#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
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#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
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#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
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#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */
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#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
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#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
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#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */
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#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */
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#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */
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#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */
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#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */
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#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */
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#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */
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#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */
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#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */
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#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */
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#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */
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#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */
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#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */
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#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */
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#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */
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#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */
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#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */
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#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */
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#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */
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#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */
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#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */
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#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */
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#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */
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#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */
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#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */
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#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
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#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */
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#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
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#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
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#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */
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#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */
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#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */
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#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */
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#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00
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#define BRGPHY_DSP_AGC_A 0x00
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#define BRGPHY_DSP_AGC_B 0x01
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#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02
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#define BRGPHY_DSP_SOFT_DECISION 0x03
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#define BRGPHY_DSP_PHASE_REG 0x04
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#define BRGPHY_DSP_SKEW 0x05
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#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06
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#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07
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#define BRGPHY_DSP_LAST_ECHO 0x08
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#define BRGPHY_DSP_FREQUENCY 0x09
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#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A
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#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B
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#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00
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#define BRGPHY_DSP_FILTER_FEXT3 0x0B00
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#define BRGPHY_DSP_FILTER_FEXT2 0x0A00
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#define BRGPHY_DSP_FILTER_FEXT1 0x0900
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#define BRGPHY_DSP_FILTER_FEXT0 0x0800
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#define BRGPHY_DSP_FILTER_NEXT3 0x0700
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#define BRGPHY_DSP_FILTER_NEXT2 0x0600
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#define BRGPHY_DSP_FILTER_NEXT1 0x0500
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#define BRGPHY_DSP_FILTER_NEXT0 0x0400
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#define BRGPHY_DSP_FILTER_ECHO 0x0300
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#define BRGPHY_DSP_FILTER_DFE 0x0200
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#define BRGPHY_DSP_FILTER_FFE 0x0100
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#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000
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#define BRGPHY_DSP_SEL_CH_0 0x0000
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#define BRGPHY_DSP_SEL_CH_1 0x2000
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#define BRGPHY_DSP_SEL_CH_2 0x4000
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#define BRGPHY_DSP_SEL_CH_3 0x6000
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#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */
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#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */
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#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */
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#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */
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#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */
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#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */
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#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
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#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
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#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */
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#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */
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#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */
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#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */
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#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */
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#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
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#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */
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#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */
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#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */
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#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */
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#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
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#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */
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#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */
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#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */
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#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */
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#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */
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#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */
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#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */
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#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
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#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
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||||
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||||
#define BRGPHY_MII_ISR 0x1A /* Interrupt status */
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#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */
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#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */
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||||
#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
|
||||
#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
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||||
#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
|
||||
#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */
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#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */
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||||
#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */
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||||
#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */
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||||
#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
|
||||
#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
|
||||
#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
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||||
#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */
|
||||
|
||||
#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */
|
||||
#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
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||||
#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */
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||||
#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */
|
||||
#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
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||||
#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
|
||||
#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */
|
||||
#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */
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||||
#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */
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||||
#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */
|
||||
#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
|
||||
#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
|
||||
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
|
||||
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/* SerDes autoneg is different from copper */
|
||||
#define BRGPHY_SERDES_ANAR 0x04
|
||||
#define BRGPHY_SERDES_ANAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANAR_HDX 0x0040
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||||
#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
#define BRGPHY_SERDES_ANLPAR 0x05
|
||||
#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
|
||||
#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
/*******************************************************/
|
||||
/* End: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*
|
||||
* Shadow register 0x1C, bit 15 is write enable,
|
||||
* bits 14-10 select function (0x00 to 0x1F).
|
||||
*/
|
||||
#define BRGPHY_MII_SHADOW_1C 0x1C
|
||||
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
|
||||
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
|
||||
|
||||
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
|
||||
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
|
||||
/* When set, Regs 0-0x0F are 1000X, else 1000T */
|
||||
#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
|
||||
|
||||
#define BRGPHY_MII_TEST1 0x1E
|
||||
#define BRGPHY_TEST1_TRIM_EN 0x0010
|
||||
#define BRGPHY_TEST1_CRC_EN 0x8000
|
||||
|
||||
#define BRGPHY_MII_TEST2 0x1F
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/* Autoneg Next Page Transmit 1 Regiser */
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
|
||||
|
||||
/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
|
||||
#define BRGPHY_5708S_BLOCK_ADDR 0x1f
|
||||
#define BRGPHY_5708S_DIG_PG0 0x0000
|
||||
#define BRGPHY_5708S_DIG3_PG2 0x0002
|
||||
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
|
||||
|
||||
/* 5708S SerDes "Digital" Registers (page 0) */
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
|
||||
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
|
||||
|
||||
/* 5708S SerDes "Digital 3" Registers (page 2) */
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
|
||||
|
||||
/* 5708S SerDes "TX Misc" Registers (page 5) */
|
||||
#define BRGPHY_5708S_PG5_2500STATUS1 0x10
|
||||
#define BRGPHY_5708S_PG5_TXACTL1 0x15
|
||||
#define BRGPHY_5708S_PG5_TXACTL3 0x17
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
#define BRGPHY_INTRS \
|
||||
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
|
||||
|
||||
#endif /* _DEV_BRGPHY_MIIREG_H_ */
|
||||
@@ -0,0 +1,513 @@
|
||||
/*-
|
||||
* Principal Author: Parag Patel
|
||||
* Copyright (c) 2001
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Additonal Copyright (c) 2001 by Traakan Software under same licence.
|
||||
* Secondary Author: Matthew Jacob
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/e1000phy.c,v 1.18 2006/12/11 11:09:48 yongari Exp $");
|
||||
|
||||
/*
|
||||
* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
|
||||
* 1000baseSX PHY.
|
||||
* Nathan Binkert <[email protected]>
|
||||
* Jung-uk Kim <[email protected]>
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include "miidevs.h"
|
||||
|
||||
#include <dev/mii/e1000phyreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int e1000phy_probe(device_t);
|
||||
static int e1000phy_attach(device_t);
|
||||
|
||||
struct e1000phy_softc {
|
||||
struct mii_softc mii_sc;
|
||||
int mii_model;
|
||||
};
|
||||
|
||||
static device_method_t e1000phy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, e1000phy_probe),
|
||||
DEVMETHOD(device_attach, e1000phy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t e1000phy_devclass;
|
||||
static driver_t e1000phy_driver = {
|
||||
"e1000phy",
|
||||
e1000phy_methods,
|
||||
sizeof(struct e1000phy_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
|
||||
|
||||
static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
|
||||
static void e1000phy_status(struct mii_softc *);
|
||||
static void e1000phy_reset(struct mii_softc *);
|
||||
static int e1000phy_mii_phy_auto(struct e1000phy_softc *);
|
||||
|
||||
static const struct mii_phydesc e1000phys[] = {
|
||||
MII_PHY_DESC(MARVELL, E1000),
|
||||
MII_PHY_DESC(MARVELL, E1011),
|
||||
MII_PHY_DESC(MARVELL, E1000_3),
|
||||
MII_PHY_DESC(MARVELL, E1000S),
|
||||
MII_PHY_DESC(MARVELL, E1000_5),
|
||||
MII_PHY_DESC(MARVELL, E1000_6),
|
||||
MII_PHY_DESC(MARVELL, E3082),
|
||||
MII_PHY_DESC(MARVELL, E1112),
|
||||
MII_PHY_DESC(MARVELL, E1149),
|
||||
MII_PHY_DESC(MARVELL, E1111),
|
||||
MII_PHY_DESC(MARVELL, E1116),
|
||||
MII_PHY_DESC(MARVELL, E1118),
|
||||
MII_PHY_DESC(xxMARVELL, E1000),
|
||||
MII_PHY_DESC(xxMARVELL, E1011),
|
||||
MII_PHY_DESC(xxMARVELL, E1000_3),
|
||||
MII_PHY_DESC(xxMARVELL, E1000_5),
|
||||
MII_PHY_DESC(xxMARVELL, E1111),
|
||||
MII_PHY_END
|
||||
};
|
||||
|
||||
static int
|
||||
e1000phy_probe(device_t dev)
|
||||
{
|
||||
|
||||
return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
|
||||
}
|
||||
|
||||
static int
|
||||
e1000phy_attach(device_t dev)
|
||||
{
|
||||
struct e1000phy_softc *esc;
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
int fast_ether;
|
||||
|
||||
esc = device_get_softc(dev);
|
||||
sc = &esc->mii_sc;
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = e1000phy_service;
|
||||
sc->mii_pdata = mii;
|
||||
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
|
||||
mii->mii_instance++;
|
||||
|
||||
fast_ether = 0;
|
||||
esc->mii_model = MII_MODEL(ma->mii_id2);
|
||||
switch (esc->mii_model) {
|
||||
case MII_MODEL_MARVELL_E1011:
|
||||
case MII_MODEL_MARVELL_E1112:
|
||||
if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
|
||||
sc->mii_flags |= MIIF_HAVEFIBER;
|
||||
break;
|
||||
case MII_MODEL_MARVELL_E3082:
|
||||
/* 88E3082 10/100 Fast Ethernet PHY. */
|
||||
sc->mii_anegticks = MII_ANEGTICKS;
|
||||
fast_ether = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
e1000phy_reset(sc);
|
||||
|
||||
device_printf(dev, " ");
|
||||
|
||||
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
|
||||
E1000_CR_ISOLATE);
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
|
||||
E1000_CR_SPEED_10);
|
||||
printf("10baseT, ");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
|
||||
E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX);
|
||||
printf("10baseT-FDX, ");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
|
||||
E1000_CR_SPEED_100);
|
||||
printf("100baseTX, ");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
|
||||
E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX);
|
||||
printf("100baseTX-FDX, ");
|
||||
if (fast_ether == 0) {
|
||||
/*
|
||||
* 1000BT-simplex not supported; driver must ignore
|
||||
* this entry, but it must be present in order to
|
||||
* manually set full-duplex.
|
||||
*/
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
|
||||
sc->mii_inst), E1000_CR_SPEED_1000);
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX,
|
||||
sc->mii_inst),
|
||||
E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
|
||||
printf("1000baseTX-FDX, ");
|
||||
}
|
||||
} else {
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
|
||||
E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
|
||||
printf("1000baseSX-FDX, ");
|
||||
}
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
|
||||
printf("auto\n");
|
||||
#undef ADD
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
e1000phy_reset(struct mii_softc *sc)
|
||||
{
|
||||
struct e1000phy_softc *esc;
|
||||
uint16_t reg;
|
||||
|
||||
esc = (struct e1000phy_softc *)sc;
|
||||
reg = PHY_READ(sc, E1000_SCR);
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
|
||||
reg &= ~E1000_SCR_AUTO_X_MODE;
|
||||
PHY_WRITE(sc, E1000_SCR, reg);
|
||||
if (esc->mii_model == MII_MODEL_MARVELL_E1112) {
|
||||
/* Select 1000BASE-X only mode. */
|
||||
PHY_WRITE(sc, E1000_EADR, 2);
|
||||
reg = PHY_READ(sc, E1000_SCR);
|
||||
reg &= ~E1000_SCR_MODE_MASK;
|
||||
reg |= E1000_SCR_MODE_1000BX;
|
||||
PHY_WRITE(sc, E1000_SCR, reg);
|
||||
PHY_WRITE(sc, E1000_EADR, 1);
|
||||
}
|
||||
} else {
|
||||
switch (esc->mii_model) {
|
||||
case MII_MODEL_MARVELL_E1111:
|
||||
case MII_MODEL_MARVELL_E1112:
|
||||
case MII_MODEL_MARVELL_E1116:
|
||||
case MII_MODEL_MARVELL_E1118:
|
||||
case MII_MODEL_MARVELL_E1149:
|
||||
/* Disable energy detect mode. */
|
||||
reg &= ~E1000_SCR_EN_DETECT_MASK;
|
||||
reg |= E1000_SCR_AUTO_X_MODE;
|
||||
break;
|
||||
case MII_MODEL_MARVELL_E3082:
|
||||
reg |= (E1000_SCR_AUTO_X_MODE >> 1);
|
||||
break;
|
||||
default:
|
||||
reg &= ~E1000_SCR_AUTO_X_MODE;
|
||||
break;
|
||||
}
|
||||
/* Enable CRS on TX. */
|
||||
reg |= E1000_SCR_ASSERT_CRS_ON_TX;
|
||||
/* Auto correction for reversed cable polarity. */
|
||||
reg &= ~E1000_SCR_POLARITY_REVERSAL;
|
||||
PHY_WRITE(sc, E1000_SCR, reg);
|
||||
}
|
||||
|
||||
switch (MII_MODEL(esc->mii_model)) {
|
||||
case MII_MODEL_MARVELL_E3082:
|
||||
case MII_MODEL_MARVELL_E1112:
|
||||
case MII_MODEL_MARVELL_E1116:
|
||||
case MII_MODEL_MARVELL_E1118:
|
||||
case MII_MODEL_MARVELL_E1149:
|
||||
break;
|
||||
default:
|
||||
/* Force TX_CLK to 25MHz clock. */
|
||||
reg = PHY_READ(sc, E1000_ESCR);
|
||||
reg |= E1000_ESCR_TX_CLK_25;
|
||||
PHY_WRITE(sc, E1000_ESCR, reg);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Reset the PHY so all changes take effect. */
|
||||
reg = PHY_READ(sc, E1000_CR);
|
||||
reg |= E1000_CR_RESET;
|
||||
PHY_WRITE(sc, E1000_CR, reg);
|
||||
}
|
||||
|
||||
static int
|
||||
e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
struct e1000phy_softc *esc = (struct e1000phy_softc *)sc;
|
||||
uint16_t speed, gig;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, E1000_CR);
|
||||
PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
|
||||
e1000phy_mii_phy_auto(esc);
|
||||
break;
|
||||
}
|
||||
|
||||
speed = 0;
|
||||
switch (IFM_SUBTYPE(ife->ifm_media)) {
|
||||
case IFM_1000_T:
|
||||
if (esc->mii_model == MII_MODEL_MARVELL_E3082)
|
||||
return (EINVAL);
|
||||
speed = E1000_CR_SPEED_1000;
|
||||
break;
|
||||
case IFM_1000_SX:
|
||||
if (esc->mii_model == MII_MODEL_MARVELL_E3082)
|
||||
return (EINVAL);
|
||||
speed = E1000_CR_SPEED_1000;
|
||||
break;
|
||||
case IFM_100_TX:
|
||||
speed = E1000_CR_SPEED_100;
|
||||
break;
|
||||
case IFM_10_T:
|
||||
speed = E1000_CR_SPEED_10;
|
||||
break;
|
||||
case IFM_NONE:
|
||||
reg = PHY_READ(sc, E1000_CR);
|
||||
PHY_WRITE(sc, E1000_CR,
|
||||
reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
|
||||
goto done;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
|
||||
speed |= E1000_CR_FULL_DUPLEX;
|
||||
gig = E1000_1GCR_1000T_FD;
|
||||
} else
|
||||
gig = E1000_1GCR_1000T;
|
||||
|
||||
reg = PHY_READ(sc, E1000_CR);
|
||||
reg &= ~E1000_CR_AUTO_NEG_ENABLE;
|
||||
PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
|
||||
|
||||
/*
|
||||
* When setting the link manually, one side must
|
||||
* be the master and the other the slave. However
|
||||
* ifmedia doesn't give us a good way to specify
|
||||
* this, so we fake it by using one of the LINK
|
||||
* flags. If LINK0 is set, we program the PHY to
|
||||
* be a master, otherwise it's a slave.
|
||||
*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T ||
|
||||
(IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX)) {
|
||||
if ((mii->mii_ifp->if_flags & IFF_LINK0))
|
||||
PHY_WRITE(sc, E1000_1GCR, gig |
|
||||
E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE);
|
||||
else
|
||||
PHY_WRITE(sc, E1000_1GCR, gig |
|
||||
E1000_1GCR_MS_ENABLE);
|
||||
} else {
|
||||
if (esc->mii_model != MII_MODEL_MARVELL_E3082)
|
||||
PHY_WRITE(sc, E1000_1GCR, 0);
|
||||
}
|
||||
PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
|
||||
PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
|
||||
done:
|
||||
break;
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Is the interface even up?
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Only used for autonegotiation.
|
||||
*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
|
||||
break;
|
||||
|
||||
/*
|
||||
* check for link.
|
||||
* Read the status register twice; BMSR_LINK is latch-low.
|
||||
*/
|
||||
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
if (reg & BMSR_LINK) {
|
||||
sc->mii_ticks = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Announce link loss right after it happens. */
|
||||
if (sc->mii_ticks <= sc->mii_anegticks)
|
||||
return (0);
|
||||
|
||||
sc->mii_ticks = 0;
|
||||
e1000phy_reset(sc);
|
||||
e1000phy_mii_phy_auto(esc);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
e1000phy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
e1000phy_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int bmsr, bmcr, esr, gsr, ssr, isr, ar, lpar;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
|
||||
esr = PHY_READ(sc, E1000_ESR);
|
||||
bmcr = PHY_READ(sc, E1000_CR);
|
||||
ssr = PHY_READ(sc, E1000_SSR);
|
||||
isr = PHY_READ(sc, E1000_ISR);
|
||||
ar = PHY_READ(sc, E1000_AR);
|
||||
lpar = PHY_READ(sc, E1000_LPAR);
|
||||
|
||||
if (bmsr & E1000_SR_LINK_STATUS)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
if (bmcr & E1000_CR_LOOPBACK)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if ((((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0) &&
|
||||
((bmsr & E1000_SR_AUTO_NEG_COMPLETE) == 0)) ||
|
||||
((ssr & E1000_SSR_LINK) == 0) ||
|
||||
((ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0)) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
if (ssr & E1000_SSR_1000MBS)
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
else if (ssr & E1000_SSR_100MBS)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
} else {
|
||||
if (ssr & E1000_SSR_1000MBS)
|
||||
mii->mii_media_active |= IFM_1000_SX;
|
||||
}
|
||||
|
||||
if (ssr & E1000_SSR_DUPLEX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
|
||||
if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
|
||||
mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
|
||||
} else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
|
||||
(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
|
||||
mii->mii_media_active |= IFM_FLAG1;
|
||||
} else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
|
||||
!(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
|
||||
mii->mii_media_active |= IFM_FLAG0;
|
||||
}
|
||||
}
|
||||
|
||||
/* FLAG2 : local PHY resolved to MASTER */
|
||||
if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) ||
|
||||
(IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)) {
|
||||
PHY_READ(sc, E1000_1GSR);
|
||||
gsr = PHY_READ(sc, E1000_1GSR);
|
||||
if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0)
|
||||
mii->mii_media_active |= IFM_FLAG2;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
e1000phy_mii_phy_auto(struct e1000phy_softc *esc)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
|
||||
sc = &esc->mii_sc;
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
|
||||
PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD |
|
||||
E1000_AR_100TX | E1000_AR_100TX_FD |
|
||||
E1000_AR_PAUSE | E1000_AR_ASM_DIR);
|
||||
else
|
||||
PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X |
|
||||
E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
|
||||
if (esc->mii_model != MII_MODEL_MARVELL_E3082)
|
||||
PHY_WRITE(sc, E1000_1GCR,
|
||||
E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
|
||||
PHY_WRITE(sc, E1000_CR,
|
||||
E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
|
||||
|
||||
return (EJUSTRETURN);
|
||||
}
|
||||
@@ -0,0 +1,324 @@
|
||||
/* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.4 2006/12/11 10:43:32 yongari Exp $ */
|
||||
/*-
|
||||
* Principal Author: Parag Patel
|
||||
* Copyright (c) 2001
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Additonal Copyright (c) 2001 by Traakan Software under same licence.
|
||||
* Secondary Author: Matthew Jacob
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Derived by information released by Intel under the following license:
|
||||
*
|
||||
* Copyright (c) 1999 - 2001, Intel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Intel Corporation nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Marvell E1000 PHY registers
|
||||
*/
|
||||
|
||||
#define E1000_MAX_REG_ADDRESS 0x1F
|
||||
|
||||
#define E1000_CR 0x00 /* control register */
|
||||
#define E1000_CR_SPEED_SELECT_MSB 0x0040
|
||||
#define E1000_CR_COLL_TEST_ENABLE 0x0080
|
||||
#define E1000_CR_FULL_DUPLEX 0x0100
|
||||
#define E1000_CR_RESTART_AUTO_NEG 0x0200
|
||||
#define E1000_CR_ISOLATE 0x0400
|
||||
#define E1000_CR_POWER_DOWN 0x0800
|
||||
#define E1000_CR_AUTO_NEG_ENABLE 0x1000
|
||||
#define E1000_CR_SPEED_SELECT_LSB 0x2000
|
||||
#define E1000_CR_LOOPBACK 0x4000
|
||||
#define E1000_CR_RESET 0x8000
|
||||
|
||||
#define E1000_CR_SPEED_1000 0x0040
|
||||
#define E1000_CR_SPEED_100 0x2000
|
||||
#define E1000_CR_SPEED_10 0x0000
|
||||
|
||||
#define E1000_SR 0x01 /* status register */
|
||||
#define E1000_SR_EXTENDED 0x0001
|
||||
#define E1000_SR_JABBER_DETECT 0x0002
|
||||
#define E1000_SR_LINK_STATUS 0x0004
|
||||
#define E1000_SR_AUTO_NEG 0x0008
|
||||
#define E1000_SR_REMOTE_FAULT 0x0010
|
||||
#define E1000_SR_AUTO_NEG_COMPLETE 0x0020
|
||||
#define E1000_SR_PREAMBLE_SUPPRESS 0x0040
|
||||
#define E1000_SR_EXTENDED_STATUS 0x0100
|
||||
#define E1000_SR_100T2 0x0200
|
||||
#define E1000_SR_100T2_FD 0x0400
|
||||
#define E1000_SR_10T 0x0800
|
||||
#define E1000_SR_10T_FD 0x1000
|
||||
#define E1000_SR_100TX 0x2000
|
||||
#define E1000_SR_100TX_FD 0x4000
|
||||
#define E1000_SR_100T4 0x8000
|
||||
|
||||
#define E1000_ID1 0x02 /* ID register 1 */
|
||||
#define E1000_ID2 0x03 /* ID register 2 */
|
||||
#define E1000_ID_88E1000 0x01410C50
|
||||
#define E1000_ID_88E1000S 0x01410C40
|
||||
#define E1000_ID_88E1011 0x01410C20
|
||||
#define E1000_ID_MASK 0xFFFFFFF0
|
||||
|
||||
#define E1000_AR 0x04 /* autonegotiation advertise reg */
|
||||
#define E1000_AR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_AR_10T 0x0020
|
||||
#define E1000_AR_10T_FD 0x0040
|
||||
#define E1000_AR_100TX 0x0080
|
||||
#define E1000_AR_100TX_FD 0x0100
|
||||
#define E1000_AR_100T4 0x0200
|
||||
#define E1000_AR_PAUSE 0x0400
|
||||
#define E1000_AR_ASM_DIR 0x0800
|
||||
#define E1000_AR_REMOTE_FAULT 0x2000
|
||||
#define E1000_AR_NEXT_PAGE 0x8000
|
||||
#define E1000_AR_SPEED_MASK 0x01E0
|
||||
|
||||
/* Autonegotiation register bits for fiber cards (Alaska Only!) */
|
||||
#define E1000_FA_1000X_FD 0x0020
|
||||
#define E1000_FA_1000X 0x0040
|
||||
#define E1000_FA_SYM_PAUSE 0x0080
|
||||
#define E1000_FA_ASYM_PAUSE 0x0100
|
||||
#define E1000_FA_FAULT1 0x1000
|
||||
#define E1000_FA_FAULT2 0x2000
|
||||
#define E1000_FA_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
|
||||
#define E1000_LPAR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_LPAR_10T 0x0020
|
||||
#define E1000_LPAR_10T_FD 0x0040
|
||||
#define E1000_LPAR_100TX 0x0080
|
||||
#define E1000_LPAR_100TX_FD 0x0100
|
||||
#define E1000_LPAR_100T4 0x0200
|
||||
#define E1000_LPAR_PAUSE 0x0400
|
||||
#define E1000_LPAR_ASM_DIR 0x0800
|
||||
#define E1000_LPAR_REMOTE_FAULT 0x2000
|
||||
#define E1000_LPAR_ACKNOWLEDGE 0x4000
|
||||
#define E1000_LPAR_NEXT_PAGE 0x8000
|
||||
|
||||
/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
|
||||
#define E1000_FPAR_1000X_FD 0x0020
|
||||
#define E1000_FPAR_1000X 0x0040
|
||||
#define E1000_FPAR_SYM_PAUSE 0x0080
|
||||
#define E1000_FPAR_ASYM_PAUSE 0x0100
|
||||
#define E1000_FPAR_FAULT1 0x1000
|
||||
#define E1000_FPAR_FAULT2 0x2000
|
||||
#define E1000_FPAR_ACK 0x4000
|
||||
#define E1000_FPAR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_ER 0x06 /* autoneg expansion reg */
|
||||
#define E1000_ER_LP_NWAY 0x0001
|
||||
#define E1000_ER_PAGE_RXD 0x0002
|
||||
#define E1000_ER_NEXT_PAGE 0x0004
|
||||
#define E1000_ER_LP_NEXT_PAGE 0x0008
|
||||
#define E1000_ER_PAR_DETECT_FAULT 0x0100
|
||||
|
||||
#define E1000_NPTX 0x07 /* autoneg next page TX */
|
||||
#define E1000_NPTX_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_NPTX_TOGGLE 0x0800
|
||||
#define E1000_NPTX_ACKNOWLDGE2 0x1000
|
||||
#define E1000_NPTX_MSG_PAGE 0x2000
|
||||
#define E1000_NPTX_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
|
||||
#define E1000_RNPR_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_RNPR_TOGGLE 0x0800
|
||||
#define E1000_RNPR_ACKNOWLDGE2 0x1000
|
||||
#define E1000_RNPR_MSG_PAGE 0x2000
|
||||
#define E1000_RNPR_ACKNOWLDGE 0x4000
|
||||
#define E1000_RNPR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_1GCR 0x09 /* 1000T (1G) control reg */
|
||||
#define E1000_1GCR_ASYM_PAUSE 0x0080
|
||||
#define E1000_1GCR_1000T 0x0100
|
||||
#define E1000_1GCR_1000T_FD 0x0200
|
||||
#define E1000_1GCR_REPEATER_DTE 0x0400
|
||||
#define E1000_1GCR_MS_VALUE 0x0800
|
||||
#define E1000_1GCR_MS_ENABLE 0x1000
|
||||
#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
|
||||
#define E1000_1GCR_TEST_MODE_1 0x2000
|
||||
#define E1000_1GCR_TEST_MODE_2 0x4000
|
||||
#define E1000_1GCR_TEST_MODE_3 0x6000
|
||||
#define E1000_1GCR_TEST_MODE_4 0x8000
|
||||
#define E1000_1GCR_SPEED_MASK 0x0300
|
||||
|
||||
#define E1000_1GSR 0x0A /* 1000T (1G) status reg */
|
||||
#define E1000_1GSR_IDLE_ERROR_CNT 0x0000
|
||||
#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
|
||||
#define E1000_1GSR_LP 0x0400
|
||||
#define E1000_1GSR_LP_FD 0x0800
|
||||
#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
|
||||
#define E1000_1GSR_LOCAL_RX_STATUS 0x2000
|
||||
#define E1000_1GSR_MS_CONFIG_RES 0x4000
|
||||
#define E1000_1GSR_MS_CONFIG_FAULT 0x8000
|
||||
|
||||
#define E1000_ESR 0x0F /* IEEE extended status reg */
|
||||
#define E1000_ESR_1000T 0x1000
|
||||
#define E1000_ESR_1000T_FD 0x2000
|
||||
#define E1000_ESR_1000X 0x4000
|
||||
#define E1000_ESR_1000X_FD 0x8000
|
||||
|
||||
#define E1000_TX_POLARITY_MASK 0x0100
|
||||
#define E1000_TX_NORMAL_POLARITY 0
|
||||
|
||||
#define E1000_AUTO_POLARITY_DISABLE 0x0010
|
||||
|
||||
#define E1000_SCR 0x10 /* special control register */
|
||||
#define E1000_SCR_JABBER_DISABLE 0x0001
|
||||
#define E1000_SCR_POLARITY_REVERSAL 0x0002
|
||||
#define E1000_SCR_SQE_TEST 0x0004
|
||||
#define E1000_SCR_INT_FIFO_DISABLE 0x0008
|
||||
#define E1000_SCR_CLK125_DISABLE 0x0010
|
||||
#define E1000_SCR_MDI_MANUAL_MODE 0x0000
|
||||
#define E1000_SCR_MDIX_MANUAL_MODE 0x0020
|
||||
#define E1000_SCR_AUTO_X_1000T 0x0040
|
||||
#define E1000_SCR_AUTO_X_MODE 0x0060
|
||||
#define E1000_SCR_10BT_EXT_ENABLE 0x0080
|
||||
#define E1000_SCR_MII_5BIT_ENABLE 0x0100
|
||||
#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
|
||||
#define E1000_SCR_FORCE_LINK_GOOD 0x0400
|
||||
#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
|
||||
|
||||
#define E1000_SCR_EN_DETECT_MASK 0x0300
|
||||
|
||||
/* 88E1112 page 2 */
|
||||
#define E1000_SCR_MODE_MASK 0x0380
|
||||
#define E1000_SCR_MODE_AUTO 0x0180
|
||||
#define E1000_SCR_MODE_COPPER 0x0280
|
||||
#define E1000_SCR_MODE_1000BX 0x0380
|
||||
|
||||
#define E1000_SSR 0x11 /* special status register */
|
||||
#define E1000_SSR_JABBER 0x0001
|
||||
#define E1000_SSR_REV_POLARITY 0x0002
|
||||
#define E1000_SSR_MDIX 0x0020
|
||||
#define E1000_SSR_LINK 0x0400
|
||||
#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
|
||||
#define E1000_SSR_PAGE_RCVD 0x1000
|
||||
#define E1000_SSR_DUPLEX 0x2000
|
||||
#define E1000_SSR_SPEED 0xC000
|
||||
#define E1000_SSR_10MBS 0x0000
|
||||
#define E1000_SSR_100MBS 0x4000
|
||||
#define E1000_SSR_1000MBS 0x8000
|
||||
|
||||
#define E1000_IER 0x12 /* interrupt enable reg */
|
||||
#define E1000_IER_JABBER 0x0001
|
||||
#define E1000_IER_POLARITY_CHANGE 0x0002
|
||||
#define E1000_IER_MDIX_CHANGE 0x0040
|
||||
#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
|
||||
#define E1000_IER_FALSE_CARRIER 0x0100
|
||||
#define E1000_IER_SYMBOL_ERROR 0x0200
|
||||
#define E1000_IER_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
|
||||
#define E1000_IER_PAGE_RECEIVED 0x1000
|
||||
#define E1000_IER_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_IER_SPEED_CHANGED 0x4000
|
||||
#define E1000_IER_AUTO_NEG_ERR 0x8000
|
||||
|
||||
#define E1000_ISR 0x13 /* interrupt status reg */
|
||||
#define E1000_ISR_JABBER 0x0001
|
||||
#define E1000_ISR_POLARITY_CHANGE 0x0002
|
||||
#define E1000_ISR_MDIX_CHANGE 0x0040
|
||||
#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
|
||||
#define E1000_ISR_FALSE_CARRIER 0x0100
|
||||
#define E1000_ISR_SYMBOL_ERROR 0x0200
|
||||
#define E1000_ISR_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
|
||||
#define E1000_ISR_PAGE_RECEIVED 0x1000
|
||||
#define E1000_ISR_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_ISR_SPEED_CHANGED 0x4000
|
||||
#define E1000_ISR_AUTO_NEG_ERR 0x8000
|
||||
|
||||
#define E1000_ESCR 0x14 /* extended special control reg */
|
||||
#define E1000_ESCR_FIBER_LOOPBACK 0x4000
|
||||
#define E1000_ESCR_DOWN_NO_IDLE 0x8000
|
||||
#define E1000_ESCR_TX_CLK_2_5 0x0060
|
||||
#define E1000_ESCR_TX_CLK_25 0x0070
|
||||
#define E1000_ESCR_TX_CLK_0 0x0000
|
||||
|
||||
#define E1000_RECR 0x15 /* RX error counter reg */
|
||||
|
||||
#define E1000_EADR 0x16 /* extended address reg */
|
||||
|
||||
#define E1000_LCR 0x18 /* LED control reg */
|
||||
#define E1000_LCR_LED_TX 0x0001
|
||||
#define E1000_LCR_LED_RX 0x0002
|
||||
#define E1000_LCR_LED_DUPLEX 0x0004
|
||||
#define E1000_LCR_LINK 0x0008
|
||||
#define E1000_LCR_BLINK_42MS 0x0000
|
||||
#define E1000_LCR_BLINK_84MS 0x0100
|
||||
#define E1000_LCR_BLINK_170MS 0x0200
|
||||
#define E1000_LCR_BLINK_340MS 0x0300
|
||||
#define E1000_LCR_BLINK_670MS 0x0400
|
||||
#define E1000_LCR_PULSE_OFF 0x0000
|
||||
#define E1000_LCR_PULSE_21_42MS 0x1000
|
||||
#define E1000_LCR_PULSE_42_84MS 0x2000
|
||||
#define E1000_LCR_PULSE_84_170MS 0x3000
|
||||
#define E1000_LCR_PULSE_170_340MS 0x4000
|
||||
#define E1000_LCR_PULSE_340_670MS 0x5000
|
||||
#define E1000_LCR_PULSE_670_13S 0x6000
|
||||
#define E1000_LCR_PULSE_13_26S 0x7000
|
||||
|
||||
/* The following register is found only on the 88E1011 Alaska PHY */
|
||||
#define E1000_ESSR 0x1B /* Extended PHY specific sts */
|
||||
#define E1000_ESSR_FIBER_LINK 0x2000
|
||||
#define E1000_ESSR_GMII_COPPER 0x000f
|
||||
#define E1000_ESSR_GMII_FIBER 0x0007
|
||||
#define E1000_ESSR_TBI_COPPER 0x000d
|
||||
#define E1000_ESSR_TBI_FIBER 0x0005
|
||||
@@ -0,0 +1,55 @@
|
||||
#define MII_OUI_MARVELL 0x005043
|
||||
#define MII_OUI_xxMARVELL 0x000ac2
|
||||
|
||||
#define MII_MODEL_MARVELL_E1000 0x0000
|
||||
#define MII_MODEL_MARVELL_E1011 0x0002
|
||||
#define MII_MODEL_MARVELL_E1000_3 0x0003
|
||||
#define MII_MODEL_MARVELL_E1000S 0x0004
|
||||
#define MII_MODEL_MARVELL_E1000_5 0x0005
|
||||
#define MII_MODEL_MARVELL_E1000_6 0x0006
|
||||
#define MII_MODEL_MARVELL_E3082 0x0008
|
||||
#define MII_MODEL_MARVELL_E1112 0x0009
|
||||
#define MII_MODEL_MARVELL_E1149 0x000b
|
||||
#define MII_MODEL_MARVELL_E1111 0x000c
|
||||
#define MII_MODEL_MARVELL_E1116 0x0021
|
||||
#define MII_MODEL_MARVELL_E1118 0x0022
|
||||
|
||||
#define MII_MODEL_xxMARVELL_E1000 0x0005
|
||||
#define MII_MODEL_xxMARVELL_E1011 0x0002
|
||||
#define MII_MODEL_xxMARVELL_E1000_3 0x0003
|
||||
#define MII_MODEL_xxMARVELL_E1000_5 0x0005
|
||||
#define MII_MODEL_xxMARVELL_E1111 0x000c
|
||||
|
||||
#define MII_STR_MARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY"
|
||||
#define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
|
||||
|
||||
#define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
|
||||
|
||||
#define MII_OUI_JATO 0x00e083 /*Jato Technologies*/
|
||||
#define MII_OUI_XAQTI 0x00e0ae /*XaQti Corp.*/
|
||||
|
||||
#define MII_OUI_xxXAQTI 0x350700 /*XaQti Corp.*/
|
||||
|
||||
/* Jato Technologies PHYs */
|
||||
#define MII_MODEL_JATO_BASEX 0x0000
|
||||
#define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
|
||||
|
||||
/* XaQti Corp. PHYs. */
|
||||
#define MII_MODEL_XAQTI_XMACII 0x0000
|
||||
#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
|
||||
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int ukphy_probe(device_t);
|
||||
static int ukphy_attach(device_t);
|
||||
|
||||
static device_method_t ukphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ukphy_probe),
|
||||
DEVMETHOD(device_attach, ukphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t ukphy_devclass;
|
||||
|
||||
static driver_t ukphy_driver = {
|
||||
"ukphy",
|
||||
ukphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
|
||||
|
||||
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
|
||||
static int
|
||||
ukphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
/*
|
||||
* We know something is here, so always match at a low priority.
|
||||
*/
|
||||
device_set_desc(dev, "Generic IEEE 802.3u media interface");
|
||||
return (BUS_PROBE_GENERIC);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
if (bootverbose)
|
||||
device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
|
||||
MII_OUI(ma->mii_id1, ma->mii_id2),
|
||||
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = ukphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
mii->mii_instance++;
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
sc->mii_capabilities =
|
||||
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
|
||||
if (sc->mii_capabilities & BMSR_EXTSTAT)
|
||||
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
|
||||
device_printf(dev, " ");
|
||||
mii_phy_add_media(sc);
|
||||
printf("\n");
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
mii_phy_setmedia(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
ukphy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
@@ -0,0 +1,129 @@
|
||||
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
/*
|
||||
* Media status subroutine. If a PHY driver does media detection simply
|
||||
* by decoding the NWay autonegotiation, use this routine.
|
||||
*/
|
||||
void
|
||||
ukphy_status(struct mii_softc *phy)
|
||||
{
|
||||
struct mii_data *mii = phy->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, anlpar, gtcr, gtsr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(phy, MII_BMCR);
|
||||
if (bmcr & BMCR_ISO) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (bmcr & BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & BMCR_AUTOEN) {
|
||||
/*
|
||||
* NWay autonegotiation takes the highest-order common
|
||||
* bit of the ANAR and ANLPAR (i.e. best media advertised
|
||||
* both by us and our link partner).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||
(phy->mii_extcapabilities &
|
||||
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||
} else
|
||||
gtcr = gtsr = 0;
|
||||
|
||||
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
@@ -0,0 +1,324 @@
|
||||
/*-
|
||||
* Copyright (c) 2000
|
||||
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/xmphy.c,v 1.21 2006/12/02 19:36:25 marius Exp $");
|
||||
|
||||
/*
|
||||
* driver for the XaQti XMAC II's internal PHY. This is sort of
|
||||
* like a 10/100 PHY, except the only thing we're really autoselecting
|
||||
* here is full/half duplex. Speed is always 1000mbps.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include "miidevs.h"
|
||||
|
||||
#include <dev/mii/xmphyreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int xmphy_probe(device_t);
|
||||
static int xmphy_attach(device_t);
|
||||
|
||||
static device_method_t xmphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, xmphy_probe),
|
||||
DEVMETHOD(device_attach, xmphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t xmphy_devclass;
|
||||
|
||||
static driver_t xmphy_driver = {
|
||||
"xmphy",
|
||||
xmphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(xmphy, miibus, xmphy_driver, xmphy_devclass, 0, 0);
|
||||
|
||||
static int xmphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
static void xmphy_status(struct mii_softc *);
|
||||
static int xmphy_mii_phy_auto(struct mii_softc *);
|
||||
|
||||
static const struct mii_phydesc xmphys[] = {
|
||||
{ MII_OUI_xxXAQTI, MII_MODEL_XAQTI_XMACII, MII_STR_XAQTI_XMACII },
|
||||
MII_PHY_DESC(JATO, BASEX),
|
||||
MII_PHY_END
|
||||
};
|
||||
|
||||
static int
|
||||
xmphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
return (mii_phy_dev_probe(dev, xmphys, BUS_PROBE_DEFAULT));
|
||||
}
|
||||
|
||||
static int
|
||||
xmphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
const char *sep = "";
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = xmphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
sc->mii_flags |= MIIF_NOISOLATE;
|
||||
mii->mii_instance++;
|
||||
|
||||
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
|
||||
#define PRINT(s) printf("%s%s", sep, s); sep = ", "
|
||||
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
|
||||
BMCR_ISO);
|
||||
#if 0
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
|
||||
BMCR_LOOP|BMCR_S100);
|
||||
#endif
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
device_printf(dev, " ");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, sc->mii_inst),
|
||||
XMPHY_BMCR_FDX);
|
||||
PRINT("1000baseSX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 0);
|
||||
PRINT("1000baseSX-FDX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
|
||||
PRINT("auto");
|
||||
|
||||
printf("\n");
|
||||
#undef ADD
|
||||
#undef PRINT
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
xmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
switch (IFM_SUBTYPE(ife->ifm_media)) {
|
||||
case IFM_AUTO:
|
||||
#ifdef foo
|
||||
/*
|
||||
* If we're already in auto mode, just return.
|
||||
*/
|
||||
if (PHY_READ(sc, XMPHY_MII_BMCR) & XMPHY_BMCR_AUTOEN)
|
||||
return (0);
|
||||
#endif
|
||||
(void) xmphy_mii_phy_auto(sc);
|
||||
break;
|
||||
case IFM_1000_SX:
|
||||
mii_phy_reset(sc);
|
||||
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
|
||||
PHY_WRITE(sc, XMPHY_MII_ANAR, XMPHY_ANAR_FDX);
|
||||
PHY_WRITE(sc, XMPHY_MII_BMCR, XMPHY_BMCR_FDX);
|
||||
} else {
|
||||
PHY_WRITE(sc, XMPHY_MII_ANAR, XMPHY_ANAR_HDX);
|
||||
PHY_WRITE(sc, XMPHY_MII_BMCR, 0);
|
||||
}
|
||||
break;
|
||||
case IFM_100_T4:
|
||||
case IFM_100_TX:
|
||||
case IFM_10_T:
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Is the interface even up?
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Only used for autonegotiation.
|
||||
*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Check to see if we have link. If we do, we don't
|
||||
* need to restart the autonegotiation process. Read
|
||||
* the BMSR twice in case it's latched.
|
||||
*/
|
||||
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
if (reg & BMSR_LINK)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Only retry autonegotiation every 5 seconds.
|
||||
*/
|
||||
if (++sc->mii_ticks <= MII_ANEGTICKS)
|
||||
break;
|
||||
|
||||
sc->mii_ticks = 0;
|
||||
|
||||
mii_phy_reset(sc);
|
||||
xmphy_mii_phy_auto(sc);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
xmphy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
xmphy_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int bmsr, bmcr, anlpar;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, XMPHY_MII_BMSR) |
|
||||
PHY_READ(sc, XMPHY_MII_BMSR);
|
||||
if (bmsr & XMPHY_BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
/* Do dummy read of extended status register. */
|
||||
bmcr = PHY_READ(sc, XMPHY_MII_EXTSTS);
|
||||
|
||||
bmcr = PHY_READ(sc, XMPHY_MII_BMCR);
|
||||
|
||||
if (bmcr & XMPHY_BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
|
||||
if (bmcr & XMPHY_BMCR_AUTOEN) {
|
||||
if ((bmsr & XMPHY_BMSR_ACOMP) == 0) {
|
||||
if (bmsr & XMPHY_BMSR_LINK) {
|
||||
mii->mii_media_active |= IFM_1000_SX|IFM_HDX;
|
||||
return;
|
||||
}
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
mii->mii_media_active |= IFM_1000_SX;
|
||||
anlpar = PHY_READ(sc, XMPHY_MII_ANAR) &
|
||||
PHY_READ(sc, XMPHY_MII_ANLPAR);
|
||||
if (anlpar & XMPHY_ANLPAR_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
return;
|
||||
}
|
||||
|
||||
mii->mii_media_active |= IFM_1000_SX;
|
||||
if (bmcr & XMPHY_BMCR_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
}
|
||||
|
||||
static int
|
||||
xmphy_mii_phy_auto(struct mii_softc *mii)
|
||||
{
|
||||
int anar = 0;
|
||||
|
||||
anar = PHY_READ(mii, XMPHY_MII_ANAR);
|
||||
anar |= XMPHY_ANAR_FDX|XMPHY_ANAR_HDX;
|
||||
PHY_WRITE(mii, XMPHY_MII_ANAR, anar);
|
||||
DELAY(1000);
|
||||
PHY_WRITE(mii, XMPHY_MII_BMCR,
|
||||
XMPHY_BMCR_AUTOEN | XMPHY_BMCR_STARTNEG);
|
||||
|
||||
return (EJUSTRETURN);
|
||||
}
|
||||
@@ -0,0 +1,117 @@
|
||||
/*-
|
||||
* Copyright (c) 2000
|
||||
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/mii/xmphyreg.h,v 1.4 2005/01/06 01:42:56 imp Exp $
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_XMPHYREG_H_
|
||||
#define _DEV_MII_XMPHYREG_H_
|
||||
|
||||
/*
|
||||
* XaQti XMAC II PHY registers
|
||||
*/
|
||||
|
||||
#define XMPHY_MII_BMCR 0x00
|
||||
#define XMPHY_BMCR_RESET 0x8000
|
||||
#define XMPHY_BMCR_LOOP 0x4000
|
||||
#define XMPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define XMPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define XMPHY_BMCR_ISO 0x0400 /* Isolate */
|
||||
#define XMPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define XMPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
|
||||
#define XMPHY_MII_BMSR 0x01
|
||||
#define XMPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
#define XMPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define XMPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define XMPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define XMPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define XMPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
#define XMPHY_MII_ANAR 0x04
|
||||
#define XMPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define XMPHY_ANAR_ACK 0x4000 /* Next page or base received */
|
||||
#define XMPHY_ANAR_RFBITS 0x3000 /* Remote fault bits */
|
||||
#define XMPHY_ANAR_PAUSEBITS 0x0180 /* Pause bits */
|
||||
#define XMPHY_ANAR_HDX 0x0040 /* Select half duplex */
|
||||
#define XMPHY_ANAR_FDX 0x0020 /* Select full duplex */
|
||||
|
||||
#define XMPHY_MII_ANLPAR 0x05
|
||||
#define XMPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define XMPHY_ANLPAR_ACK 0x4000 /* Next page or base received */
|
||||
#define XMPHY_ANLPAR_RFBITS 0x3000 /* Remote fault bits */
|
||||
#define XMPHY_ANLPAR_PAUSEBITS 0x0180 /* Pause bits */
|
||||
#define XMPHY_ANLPAR_HDX 0x0040 /* Select half duplex */
|
||||
#define XMPHY_ANLPAR_FDX 0x0020 /* Select full duplex */
|
||||
|
||||
#define XMPHY_RF_OK 0x0000 /* No error -- link is good */
|
||||
#define XMPHY_RF_LINKFAIL 0x1000 /* Link failure */
|
||||
#define XMPHY_RF_OFFLINE 0x2000 /* Offline */
|
||||
#define XMPHY_RF_ANEGFAIL 0x3000 /* Autonegotiation error */
|
||||
|
||||
#define XMPHY_PAUSE_NOPAUSE 0x0000 /* No pause possible */
|
||||
#define XMPHY_PAUSE_ASYMETRIC 0x0080 /* Asymetric pause toward LP */
|
||||
#define XMPHY_PAUSE_SYMETRIC 0x0100 /* Symetric pause */
|
||||
#define XMPHY_PAUSE_BOTH 0x0180 /* Both sym and asym pause */
|
||||
|
||||
#define XMPHY_MII_ANER 0x06
|
||||
#define XMPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define XMPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define XMPHY_ANER_RX 0x0002 /* Next page received */
|
||||
|
||||
#define XMPHY_MII_NEXTP 0x07 /* Next page */
|
||||
#define XMPHY_NEXTP_MORE 0x8000 /* More next pages to follow */
|
||||
#define XMPHY_NEXTP_ACK1 0x4000 /* Ack bit received OK */
|
||||
#define XMPHY_NEXTP_MP 0x2000 /* Page is message page */
|
||||
#define XMPHY_NEXTP_ACK2 0x1000 /* can comply with message (r/o) */
|
||||
#define XMPHY_NEXTP_TOGGLE 0x0800 /* sync with LP */
|
||||
#define XMPHY_NEXTP_MESSAGE 0x07FF /* message */
|
||||
|
||||
#define XMPHY_MII_NEXTPLP 0x08 /* Next page of link partner */
|
||||
#define XMPHY_NEXTPLP_MORE 0x8000 /* More next pages to follow */
|
||||
#define XMPHY_NEXTPLP_ACK1 0x4000 /* Ack bit received OK */
|
||||
#define XMPHY_NEXTPLP_MP 0x2000 /* Page is message page */
|
||||
#define XMPHY_NEXTPLP_ACK2 0x1000 /* can comply with message (r/o) */
|
||||
#define XMPHY_NEXTPLP_TOGGLE 0x0800 /* sync with LP */
|
||||
#define XMPHY_NEXTPLP_MESSAGE 0x07FF /* message */
|
||||
|
||||
#define XMPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define XMPHY_EXTSTS_FDX 0x8000 /* 1000base-X FD capable */
|
||||
#define XMPHY_EXTSTS_HDX 0x4000 /* 1000base-X HD capable */
|
||||
|
||||
#define XMPHY_MII_RESAB 0x10 /* Resolved ability */
|
||||
#define XMPHY_RESAB_PAUSEBITS 0x0180 /* Pause bits */
|
||||
#define XMPHY_RESAB_HDX 0x0040 /* Half duplex selected */
|
||||
#define XMPHY_RESAB_FDX 0x0020 /* Full duplex selected */
|
||||
#define XMPHY_RESAB_ABLMIS 0x0010 /* Ability mismatch */
|
||||
#define XMPHY_RESAB_PAUSEMIS 0x0008 /* Pause mismatch */
|
||||
|
||||
#endif /* _DEV_MII_XMPHYREG_H_ */
|
||||
@@ -0,0 +1,14 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network syskonnect dev sk ;
|
||||
|
||||
UsePrivateHeaders kernel net ;
|
||||
|
||||
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
|
||||
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
|
||||
|
||||
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
|
||||
|
||||
KernelAddon syskonnect :
|
||||
if_sk.c
|
||||
glue.c
|
||||
: libfreebsd_network.a syskonnect_mii.a
|
||||
;
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright 2007, Hugo Santos. All Rights Reserved.
|
||||
* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include "if_skreg.h"
|
||||
|
||||
#include "xmaciireg.h"
|
||||
|
||||
HAIKU_FBSD_DRIVER_GLUE(syskonnect, skc, pci)
|
||||
|
||||
extern driver_t *DRIVER_MODULE_NAME(e1000phy, miibus);
|
||||
extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
|
||||
extern driver_t *DRIVER_MODULE_NAME(xmphy, miibus);
|
||||
|
||||
HAIKU_DRIVER_REQUIREMENTS(0);
|
||||
|
||||
driver_t *
|
||||
__haiku_select_miibus_driver(device_t dev)
|
||||
{
|
||||
driver_t *drivers[] = {
|
||||
DRIVER_MODULE_NAME(xmphy, miibus),
|
||||
DRIVER_MODULE_NAME(e1000phy, miibus),
|
||||
DRIVER_MODULE_NAME(ukphy, miibus),
|
||||
NULL
|
||||
};
|
||||
|
||||
return __haiku_probe_miibus(dev, drivers);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
__haiku_disable_interrupts(device_t dev)
|
||||
{
|
||||
struct sk_softc* sc = device_get_softc(dev);
|
||||
u_int32_t status;
|
||||
u_int32_t mask;
|
||||
HAIKU_INTR_REGISTER_STATE;
|
||||
|
||||
mask = sc->sk_intrmask;
|
||||
HAIKU_INTR_REGISTER_ENTER();
|
||||
|
||||
status = CSR_READ_4(sc, SK_ISSR);
|
||||
if (status == 0 || status == 0xffffffff || sc->sk_suspended)
|
||||
{
|
||||
HAIKU_INTR_REGISTER_LEAVE();
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sc->sk_if[SK_PORT_A] != NULL)
|
||||
{
|
||||
mask &= ~SK_INTRS1;
|
||||
}
|
||||
|
||||
if (sc->sk_if[SK_PORT_B] != NULL)
|
||||
{
|
||||
mask &= ~SK_INTRS2;
|
||||
}
|
||||
|
||||
mask &= ~SK_ISR_EXTERNAL_REG;
|
||||
CSR_WRITE_4(sc, SK_IMR, mask);
|
||||
|
||||
HAIKU_INTR_REGISTER_LEAVE();
|
||||
|
||||
atomic_or((int32 *)&sc->sk_intstatus, status);
|
||||
return status & sc->sk_intrmask;
|
||||
}
|
||||
|
||||
void
|
||||
__haiku_reenable_interrupts(device_t dev)
|
||||
{
|
||||
struct sk_softc *sc = device_get_softc(dev);
|
||||
|
||||
CSR_READ_4(sc, SK_ISSR);
|
||||
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,406 @@
|
||||
/*-
|
||||
* Copyright (c) 1997, 1998, 1999, 2000
|
||||
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/sk/xmaciireg.h,v 1.5 2006/04/27 05:59:09 yongari Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
* Registers and data structures for the XaQti Corporation XMAC II
|
||||
* Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com.
|
||||
* The XMAC can be programmed for 16-bit or 32-bit register access modes.
|
||||
* The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's
|
||||
* how the registers are laid out here.
|
||||
*/
|
||||
|
||||
#define XM_DEVICEID 0x00E0AE20
|
||||
#define XM_XAQTI_OUI 0x00E0AE
|
||||
|
||||
#define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
|
||||
|
||||
#define XM_XMAC_REV_B2 0x0
|
||||
#define XM_XMAC_REV_C1 0x1
|
||||
|
||||
#define XM_MMUCMD 0x0000
|
||||
#define XM_POFF 0x0008
|
||||
#define XM_BURST 0x000C
|
||||
#define XM_VLAN_TAGLEV1 0x0010
|
||||
#define XM_VLAN_TAGLEV2 0x0014
|
||||
#define XM_TXCMD 0x0020
|
||||
#define XM_TX_RETRYLIMIT 0x0024
|
||||
#define XM_TX_SLOTTIME 0x0028
|
||||
#define XM_TX_IPG 0x003C
|
||||
#define XM_RXCMD 0x0030
|
||||
#define XM_PHY_ADDR 0x0034
|
||||
#define XM_PHY_DATA 0x0038
|
||||
#define XM_GPIO 0x0040
|
||||
#define XM_IMR 0x0044
|
||||
#define XM_ISR 0x0048
|
||||
#define XM_HWCFG 0x004C
|
||||
#define XM_TX_LOWAT 0x0060
|
||||
#define XM_TX_HIWAT 0x0062
|
||||
#define XM_TX_REQTHRESH_LO 0x0064
|
||||
#define XM_TX_REQTHRESH_HI 0x0066
|
||||
#define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO
|
||||
#define XM_PAUSEDST0 0x0068
|
||||
#define XM_PAUSEDST1 0x006A
|
||||
#define XM_PAUSEDST2 0x006C
|
||||
#define XM_CTLPARM_LO 0x0070
|
||||
#define XM_CTLPARM_HI 0x0072
|
||||
#define XM_CTLPARM XM_CTLPARM_LO
|
||||
#define XM_OPCODE_PAUSE_TIMER 0x0074
|
||||
#define XM_TXSTAT_LIFO 0x0078
|
||||
|
||||
/*
|
||||
* Perfect filter registers. The XMAC has a table of 16 perfect
|
||||
* filter entries, spaced 8 bytes apart. This is in addition to
|
||||
* the station address registers, which appear below.
|
||||
*/
|
||||
#define XM_RXFILT_BASE 0x0080
|
||||
#define XM_RXFILT_END 0x0107
|
||||
#define XM_RXFILT_MAX 16
|
||||
#define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8)))
|
||||
|
||||
/* Primary station address. */
|
||||
#define XM_PAR0 0x0108
|
||||
#define XM_PAR1 0x010A
|
||||
#define XM_PAR2 0x010C
|
||||
|
||||
/* 64-bit multicast hash table registers */
|
||||
#define XM_MAR0 0x0110
|
||||
#define XM_MAR1 0x0112
|
||||
#define XM_MAR2 0x0114
|
||||
#define XM_MAR3 0x0116
|
||||
#define XM_RX_LOWAT 0x0118
|
||||
#define XM_RX_HIWAT 0x011A
|
||||
#define XM_RX_REQTHRESH_LO 0x011C
|
||||
#define XM_RX_REQTHRESH_HI 0x011E
|
||||
#define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO
|
||||
#define XM_DEVID_LO 0x0120
|
||||
#define XM_DEVID_HI 0x0122
|
||||
#define XM_DEVID XM_DEVID_LO
|
||||
#define XM_MODE_LO 0x0124
|
||||
#define XM_MODE_HI 0x0126
|
||||
#define XM_MODE XM_MODE_LO
|
||||
#define XM_LASTSRC0 0x0128
|
||||
#define XM_LASTSRC1 0x012A
|
||||
#define XM_LASTSRC2 0x012C
|
||||
#define XM_TSTAMP_READ 0x0130
|
||||
#define XM_TSTAMP_LOAD 0x0134
|
||||
#define XM_STATS_CMD 0x0200
|
||||
#define XM_RXCNT_EVENT_LO 0x0204
|
||||
#define XM_RXCNT_EVENT_HI 0x0206
|
||||
#define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO
|
||||
#define XM_TXCNT_EVENT_LO 0x0208
|
||||
#define XM_TXCNT_EVENT_HI 0x020A
|
||||
#define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO
|
||||
#define XM_RXCNT_EVMASK_LO 0x020C
|
||||
#define XM_RXCNT_EVMASK_HI 0x020E
|
||||
#define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO
|
||||
#define XM_TXCNT_EVMASK_LO 0x0210
|
||||
#define XM_TXCNT_EVMASK_HI 0x0212
|
||||
#define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO
|
||||
|
||||
/* Statistics command register */
|
||||
#define XM_STATCMD_CLR_TX 0x0001
|
||||
#define XM_STATCMD_CLR_RX 0x0002
|
||||
#define XM_STATCMD_COPY_TX 0x0004
|
||||
#define XM_STATCMD_COPY_RX 0x0008
|
||||
#define XM_STATCMD_SNAP_TX 0x0010
|
||||
#define XM_STATCMD_SNAP_RX 0x0020
|
||||
|
||||
/* TX statistics registers */
|
||||
#define XM_TXSTATS_PKTSOK 0x280
|
||||
#define XM_TXSTATS_BYTESOK_HI 0x284
|
||||
#define XM_TXSTATS_BYTESOK_LO 0x288
|
||||
#define XM_TXSTATS_BCASTSOK 0x28C
|
||||
#define XM_TXSTATS_MCASTSOK 0x290
|
||||
#define XM_TXSTATS_UCASTSOK 0x294
|
||||
#define XM_TXSTATS_GIANTS 0x298
|
||||
#define XM_TXSTATS_BURSTCNT 0x29C
|
||||
#define XM_TXSTATS_PAUSEPKTS 0x2A0
|
||||
#define XM_TXSTATS_MACCTLPKTS 0x2A4
|
||||
#define XM_TXSTATS_SINGLECOLS 0x2A8
|
||||
#define XM_TXSTATS_MULTICOLS 0x2AC
|
||||
#define XM_TXSTATS_EXCESSCOLS 0x2B0
|
||||
#define XM_TXSTATS_LATECOLS 0x2B4
|
||||
#define XM_TXSTATS_DEFER 0x2B8
|
||||
#define XM_TXSTATS_EXCESSDEFER 0x2BC
|
||||
#define XM_TXSTATS_UNDERRUN 0x2C0
|
||||
#define XM_TXSTATS_CARRIERSENSE 0x2C4
|
||||
#define XM_TXSTATS_UTILIZATION 0x2C8
|
||||
#define XM_TXSTATS_64 0x2D0
|
||||
#define XM_TXSTATS_65_127 0x2D4
|
||||
#define XM_TXSTATS_128_255 0x2D8
|
||||
#define XM_TXSTATS_256_511 0x2DC
|
||||
#define XM_TXSTATS_512_1023 0x2E0
|
||||
#define XM_TXSTATS_1024_MAX 0x2E4
|
||||
|
||||
/* RX statistics registers */
|
||||
#define XM_RXSTATS_PKTSOK 0x300
|
||||
#define XM_RXSTATS_BYTESOK_HI 0x304
|
||||
#define XM_RXSTATS_BYTESOK_LO 0x308
|
||||
#define XM_RXSTATS_BCASTSOK 0x30C
|
||||
#define XM_RXSTATS_MCASTSOK 0x310
|
||||
#define XM_RXSTATS_UCASTSOK 0x314
|
||||
#define XM_RXSTATS_PAUSEPKTS 0x318
|
||||
#define XM_RXSTATS_MACCTLPKTS 0x31C
|
||||
#define XM_RXSTATS_BADPAUSEPKTS 0x320
|
||||
#define XM_RXSTATS_BADMACCTLPKTS 0x324
|
||||
#define XM_RXSTATS_BURSTCNT 0x328
|
||||
#define XM_RXSTATS_MISSEDPKTS 0x32C
|
||||
#define XM_RXSTATS_FRAMEERRS 0x330
|
||||
#define XM_RXSTATS_OVERRUN 0x334
|
||||
#define XM_RXSTATS_JABBER 0x338
|
||||
#define XM_RXSTATS_CARRLOSS 0x33C
|
||||
#define XM_RXSTATS_INRNGLENERR 0x340
|
||||
#define XM_RXSTATS_SYMERR 0x344
|
||||
#define XM_RXSTATS_SHORTEVENT 0x348
|
||||
#define XM_RXSTATS_RUNTS 0x34C
|
||||
#define XM_RXSTATS_GIANTS 0x350
|
||||
#define XM_RXSTATS_CRCERRS 0x354
|
||||
#define XM_RXSTATS_CEXTERRS 0x35C
|
||||
#define XM_RXSTATS_UTILIZATION 0x360
|
||||
#define XM_RXSTATS_64 0x368
|
||||
#define XM_RXSTATS_65_127 0x36C
|
||||
#define XM_RXSTATS_128_255 0x370
|
||||
#define XM_RXSTATS_256_511 0x374
|
||||
#define XM_RXSTATS_512_1023 0x378
|
||||
#define XM_RXSTATS_1024_MAX 0x37C
|
||||
|
||||
#define XM_MMUCMD_TX_ENB 0x0001
|
||||
#define XM_MMUCMD_RX_ENB 0x0002
|
||||
#define XM_MMUCMD_GMIILOOP 0x0004
|
||||
#define XM_MMUCMD_RATECTL 0x0008
|
||||
#define XM_MMUCMD_GMIIFDX 0x0010
|
||||
#define XM_MMUCMD_NO_MGMT_PRMB 0x0020
|
||||
#define XM_MMUCMD_SIMCOL 0x0040
|
||||
#define XM_MMUCMD_FORCETX 0x0080
|
||||
#define XM_MMUCMD_LOOPENB 0x0200
|
||||
#define XM_MMUCMD_IGNPAUSE 0x0400
|
||||
#define XM_MMUCMD_PHYBUSY 0x0800
|
||||
#define XM_MMUCMD_PHYDATARDY 0x1000
|
||||
|
||||
#define XM_TXCMD_AUTOPAD 0x0001
|
||||
#define XM_TXCMD_NOCRC 0x0002
|
||||
#define XM_TXCMD_NOPREAMBLE 0x0004
|
||||
#define XM_TXCMD_NOGIGAMODE 0x0008
|
||||
#define XM_TXCMD_SAMPLELINE 0x0010
|
||||
#define XM_TXCMD_ENCBYPASS 0x0020
|
||||
#define XM_TXCMD_XMITBK2BK 0x0040
|
||||
#define XM_TXCMD_FAIRSHARE 0x0080
|
||||
|
||||
#define XM_RXCMD_DISABLE_CEXT 0x0001
|
||||
#define XM_RXCMD_STRIPPAD 0x0002
|
||||
#define XM_RXCMD_SAMPLELINE 0x0004
|
||||
#define XM_RXCMD_SELFRX 0x0008
|
||||
#define XM_RXCMD_STRIPFCS 0x0010
|
||||
#define XM_RXCMD_TRANSPARENT 0x0020
|
||||
#define XM_RXCMD_IPGCAPTURE 0x0040
|
||||
#define XM_RXCMD_BIGPKTOK 0x0080
|
||||
#define XM_RXCMD_LENERROK 0x0100
|
||||
|
||||
#define XM_GPIO_GP0_SET 0x0001
|
||||
#define XM_GPIO_RESETSTATS 0x0004
|
||||
#define XM_GPIO_RESETMAC 0x0008
|
||||
#define XM_GPIO_FORCEINT 0x0020
|
||||
#define XM_GPIO_ANEGINPROG 0x0040
|
||||
|
||||
#define XM_IMR_RX_EOF 0x0001
|
||||
#define XM_IMR_TX_EOF 0x0002
|
||||
#define XM_IMR_TX_UNDERRUN 0x0004
|
||||
#define XM_IMR_RX_OVERRUN 0x0008
|
||||
#define XM_IMR_TX_STATS_OFLOW 0x0010
|
||||
#define XM_IMR_RX_STATS_OFLOW 0x0020
|
||||
#define XM_IMR_TSTAMP_OFLOW 0x0040
|
||||
#define XM_IMR_AUTONEG_DONE 0x0080
|
||||
#define XM_IMR_NEXTPAGE_RDY 0x0100
|
||||
#define XM_IMR_PAGE_RECEIVED 0x0200
|
||||
#define XM_IMR_LP_REQCFG 0x0400
|
||||
#define XM_IMR_GP0_SET 0x0800
|
||||
#define XM_IMR_FORCEINTR 0x1000
|
||||
#define XM_IMR_TX_ABORT 0x2000
|
||||
#define XM_IMR_LINKEVENT 0x4000
|
||||
|
||||
#define XM_INTRS \
|
||||
(~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN))
|
||||
|
||||
#define XM_ISR_RX_EOF 0x0001
|
||||
#define XM_ISR_TX_EOF 0x0002
|
||||
#define XM_ISR_TX_UNDERRUN 0x0004
|
||||
#define XM_ISR_RX_OVERRUN 0x0008
|
||||
#define XM_ISR_TX_STATS_OFLOW 0x0010
|
||||
#define XM_ISR_RX_STATS_OFLOW 0x0020
|
||||
#define XM_ISR_TSTAMP_OFLOW 0x0040
|
||||
#define XM_ISR_AUTONEG_DONE 0x0080
|
||||
#define XM_ISR_NEXTPAGE_RDY 0x0100
|
||||
#define XM_ISR_PAGE_RECEIVED 0x0200
|
||||
#define XM_ISR_LP_REQCFG 0x0400
|
||||
#define XM_ISR_GP0_SET 0x0800
|
||||
#define XM_ISR_FORCEINTR 0x1000
|
||||
#define XM_ISR_TX_ABORT 0x2000
|
||||
#define XM_ISR_LINKEVENT 0x4000
|
||||
|
||||
#define XM_HWCFG_GENEOP 0x0008
|
||||
#define XM_HWCFG_SIGSTATCKH 0x0004
|
||||
#define XM_HWCFG_GMIIMODE 0x0001
|
||||
|
||||
#define XM_MODE_FLUSH_RXFIFO 0x00000001
|
||||
#define XM_MODE_FLUSH_TXFIFO 0x00000002
|
||||
#define XM_MODE_BIGENDIAN 0x00000004
|
||||
#define XM_MODE_RX_PROMISC 0x00000008
|
||||
#define XM_MODE_RX_NOBROAD 0x00000010
|
||||
#define XM_MODE_RX_NOMULTI 0x00000020
|
||||
#define XM_MODE_RX_NOUNI 0x00000040
|
||||
#define XM_MODE_RX_BADFRAMES 0x00000080
|
||||
#define XM_MODE_RX_CRCERRS 0x00000100
|
||||
#define XM_MODE_RX_GIANTS 0x00000200
|
||||
#define XM_MODE_RX_INRANGELEN 0x00000400
|
||||
#define XM_MODE_RX_RUNTS 0x00000800
|
||||
#define XM_MODE_RX_MACCTL 0x00001000
|
||||
#define XM_MODE_RX_USE_PERFECT 0x00002000
|
||||
#define XM_MODE_RX_USE_STATION 0x00004000
|
||||
#define XM_MODE_RX_USE_HASH 0x00008000
|
||||
#define XM_MODE_RX_ADDRPAIR 0x00010000
|
||||
#define XM_MODE_PAUSEONHI 0x00020000
|
||||
#define XM_MODE_PAUSEONLO 0x00040000
|
||||
#define XM_MODE_TIMESTAMP 0x00080000
|
||||
#define XM_MODE_SENDPAUSE 0x00100000
|
||||
#define XM_MODE_SENDCONTINUOUS 0x00200000
|
||||
#define XM_MODE_LE_STATUSWORD 0x00400000
|
||||
#define XM_MODE_AUTOFIFOPAUSE 0x00800000
|
||||
#define XM_MODE_EXPAUSEGEN 0x02000000
|
||||
#define XM_MODE_RX_INVERSE 0x04000000
|
||||
|
||||
#define XM_RXSTAT_MACCTL 0x00000001
|
||||
#define XM_RXSTAT_ERRFRAME 0x00000002
|
||||
#define XM_RXSTAT_CRCERR 0x00000004
|
||||
#define XM_RXSTAT_GIANT 0x00000008
|
||||
#define XM_RXSTAT_RUNT 0x00000010
|
||||
#define XM_RXSTAT_FRAMEERR 0x00000020
|
||||
#define XM_RXSTAT_INRANGEERR 0x00000040
|
||||
#define XM_RXSTAT_CARRIERERR 0x00000080
|
||||
#define XM_RXSTAT_COLLERR 0x00000100
|
||||
#define XM_RXSTAT_802_3 0x00000200
|
||||
#define XM_RXSTAT_CARREXTERR 0x00000400
|
||||
#define XM_RXSTAT_BURSTMODE 0x00000800
|
||||
#define XM_RXSTAT_UNICAST 0x00002000
|
||||
#define XM_RXSTAT_MULTICAST 0x00004000
|
||||
#define XM_RXSTAT_BROADCAST 0x00008000
|
||||
#define XM_RXSTAT_VLAN_LEV1 0x00010000
|
||||
#define XM_RXSTAT_VLAN_LEV2 0x00020000
|
||||
#define XM_RXSTAT_LEN 0xFFFC0000
|
||||
#define XM_RXSTAT_LENSHIFT 18
|
||||
|
||||
#define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT)
|
||||
|
||||
/*
|
||||
* XMAC PHY registers, indirectly accessed through
|
||||
* XM_PHY_ADDR and XM_PHY_REG.
|
||||
*/
|
||||
|
||||
#define XM_PHY_BMCR 0x0000 /* control */
|
||||
#define XM_PHY_BMSR 0x0001 /* status */
|
||||
#define XM_PHY_VENID 0x0002 /* vendor id */
|
||||
#define XM_PHY_DEVID 0x0003 /* device id */
|
||||
#define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */
|
||||
#define XM_PHY_LPAR 0x0005 /* link partner ability */
|
||||
#define XM_PHY_ANEXP 0x0006 /* autoneg expansion */
|
||||
#define XM_PHY_NEXTP 0x0007 /* nextpage */
|
||||
#define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */
|
||||
#define XM_PHY_EXTSTS 0x000F /* extented status */
|
||||
#define XM_PHY_RESAB 0x0010 /* resolved ability */
|
||||
|
||||
#define XM_BMCR_DUPLEX 0x0100
|
||||
#define XM_BMCR_RENEGOTIATE 0x0200
|
||||
#define XM_BMCR_AUTONEGENBL 0x1000
|
||||
#define XM_BMCR_LOOPBACK 0x4000
|
||||
#define XM_BMCR_RESET 0x8000
|
||||
|
||||
#define XM_BMSR_EXTCAP 0x0001
|
||||
#define XM_BMSR_LINKSTAT 0x0004
|
||||
#define XM_BMSR_AUTONEGABLE 0x0008
|
||||
#define XM_BMSR_REMFAULT 0x0010
|
||||
#define XM_BMSR_AUTONEGDONE 0x0020
|
||||
#define XM_BMSR_EXTSTAT 0x0100
|
||||
|
||||
#define XM_VENID_XAQTI 0xD14C
|
||||
#define XM_DEVID_XMAC 0x0002
|
||||
|
||||
#define XM_ANAR_FULLDUPLEX 0x0020
|
||||
#define XM_ANAR_HALFDUPLEX 0x0040
|
||||
#define XM_ANAR_PAUSEBITS 0x0180
|
||||
#define XM_ANAR_REMFAULTBITS 0x1800
|
||||
#define XM_ANAR_ACK 0x4000
|
||||
#define XM_ANAR_NEXTPAGE 0x8000
|
||||
|
||||
#define XM_LPAR_FULLDUPLEX 0x0020
|
||||
#define XM_LPAR_HALFDUPLEX 0x0040
|
||||
#define XM_LPAR_PAUSEBITS 0x0180
|
||||
#define XM_LPAR_REMFAULTBITS 0x1800
|
||||
#define XM_LPAR_ACK 0x4000
|
||||
#define XM_LPAR_NEXTPAGE 0x8000
|
||||
|
||||
#define XM_PAUSE_NOPAUSE 0x0000
|
||||
#define XM_PAUSE_SYMPAUSE 0x0080
|
||||
#define XM_PAUSE_ASYMPAUSE 0x0100
|
||||
#define XM_PAUSE_BOTH 0x0180
|
||||
|
||||
#define XM_REMFAULT_LINKOK 0x0000
|
||||
#define XM_REMFAULT_LINKFAIL 0x0800
|
||||
#define XM_REMFAULT_OFFLINE 0x1000
|
||||
#define XM_REMFAULT_ANEGERR 0x1800
|
||||
|
||||
#define XM_ANEXP_GOTPAGE 0x0002
|
||||
#define XM_ANEXP_NEXTPAGE_SELF 0x0004
|
||||
#define XM_ANEXP_NEXTPAGE_LP 0x0008
|
||||
|
||||
#define XM_NEXTP_MESSAGE 0x07FF
|
||||
#define XM_NEXTP_TOGGLE 0x0800
|
||||
#define XM_NEXTP_ACK2 0x1000
|
||||
#define XM_NEXTP_MPAGE 0x2000
|
||||
#define XM_NEXTP_ACK1 0x4000
|
||||
#define XM_NEXTP_NPAGE 0x8000
|
||||
|
||||
#define XM_LPNEXTP_MESSAGE 0x07FF
|
||||
#define XM_LPNEXTP_TOGGLE 0x0800
|
||||
#define XM_LPNEXTP_ACK2 0x1000
|
||||
#define XM_LPNEXTP_MPAGE 0x2000
|
||||
#define XM_LPNEXTP_ACK1 0x4000
|
||||
#define XM_LPNEXTP_NPAGE 0x8000
|
||||
|
||||
#define XM_EXTSTS_HALFDUPLEX 0x4000
|
||||
#define XM_EXTSTS_FULLDUPLEX 0x8000
|
||||
|
||||
#define XM_RESAB_PAUSEMISMATCH 0x0008
|
||||
#define XM_RESAB_ABLMISMATCH 0x0010
|
||||
#define XM_RESAB_FDMODESEL 0x0020
|
||||
#define XM_RESAB_HDMODESEL 0x0040
|
||||
#define XM_RESAB_PAUSEBITS 0x0180
|
||||
@@ -0,0 +1,190 @@
|
||||
/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/sk/yukonreg.h,v 1.3 2006/04/27 05:59:09 yongari Exp $
|
||||
*/
|
||||
|
||||
/* General Purpose Status Register (GPSR) */
|
||||
#define YUKON_GPSR 0x0000
|
||||
|
||||
#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
|
||||
#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
|
||||
#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
|
||||
#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
|
||||
#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
|
||||
#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */
|
||||
#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */
|
||||
#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
|
||||
#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
|
||||
#define YU_GPSR_PARTITION 0x0008 /* partition mode */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */
|
||||
|
||||
/* General Purpose Control Register (GPCR) */
|
||||
#define YUKON_GPCR 0x0004
|
||||
|
||||
#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */
|
||||
#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
|
||||
#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
|
||||
#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */
|
||||
#define YU_GPCR_PAR 0x0100 /* Partition Enable */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */
|
||||
#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
|
||||
#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
|
||||
#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */
|
||||
#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */
|
||||
|
||||
/* Transmit Control Register (TCR) */
|
||||
#define YUKON_TCR 0x0008
|
||||
|
||||
#define YU_TCR_FJ 0x8000 /* force jam / flow control */
|
||||
#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */
|
||||
#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */
|
||||
#define YU_TCR_COLTH 0x1c00 /* collision threshold */
|
||||
|
||||
/* Receive Control Register (RCR) */
|
||||
#define YUKON_RCR 0x000c
|
||||
|
||||
#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */
|
||||
#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */
|
||||
#define YU_RCR_CRCR 0x2000 /* remove CRC */
|
||||
#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */
|
||||
|
||||
/* Transmit Flow Control Register (TFCR) */
|
||||
#define YUKON_TFCR 0x0010 /* Pause Time */
|
||||
|
||||
/* Transmit Parameter Register (TPR) */
|
||||
#define YUKON_TPR 0x0014
|
||||
|
||||
#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14)
|
||||
#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9)
|
||||
#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4)
|
||||
|
||||
/* Serial Mode Register (SMR) */
|
||||
#define YUKON_SMR 0x0018
|
||||
|
||||
#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11)
|
||||
#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */
|
||||
#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */
|
||||
#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */
|
||||
#define YU_SMR_IPG_DATA(x) ((x) & 0x1f)
|
||||
|
||||
/* Source Address Low #1 (SAL1) */
|
||||
#define YUKON_SAL1 0x001c /* SA1[15:0] */
|
||||
|
||||
/* Source Address Middle #1 (SAM1) */
|
||||
#define YUKON_SAM1 0x0020 /* SA1[31:16] */
|
||||
|
||||
/* Source Address High #1 (SAH1) */
|
||||
#define YUKON_SAH1 0x0024 /* SA1[47:32] */
|
||||
|
||||
/* Source Address Low #2 (SAL2) */
|
||||
#define YUKON_SAL2 0x0028 /* SA2[15:0] */
|
||||
|
||||
/* Source Address Middle #2 (SAM2) */
|
||||
#define YUKON_SAM2 0x002c /* SA2[31:16] */
|
||||
|
||||
/* Source Address High #2 (SAH2) */
|
||||
#define YUKON_SAH2 0x0030 /* SA2[47:32] */
|
||||
|
||||
/* Multicatst Address Hash Register 1 (MCAH1) */
|
||||
#define YUKON_MCAH1 0x0034
|
||||
|
||||
/* Multicatst Address Hash Register 2 (MCAH2) */
|
||||
#define YUKON_MCAH2 0x0038
|
||||
|
||||
/* Multicatst Address Hash Register 3 (MCAH3) */
|
||||
#define YUKON_MCAH3 0x003c
|
||||
|
||||
/* Multicatst Address Hash Register 4 (MCAH4) */
|
||||
#define YUKON_MCAH4 0x0040
|
||||
|
||||
/* Transmit Interrupt Register (TIR) */
|
||||
#define YUKON_TIR 0x0044
|
||||
|
||||
#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */
|
||||
#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */
|
||||
#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */
|
||||
#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */
|
||||
#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */
|
||||
#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */
|
||||
|
||||
/* Receive Interrupt Register (RIR) */
|
||||
#define YUKON_RIR 0x0048
|
||||
|
||||
/* Transmit and Receive Interrupt Register (TRIR) */
|
||||
#define YUKON_TRIR 0x004c
|
||||
|
||||
/* Transmit Interrupt Mask Register (TIMR) */
|
||||
#define YUKON_TIMR 0x0050
|
||||
|
||||
/* Receive Interrupt Mask Register (RIMR) */
|
||||
#define YUKON_RIMR 0x0054
|
||||
|
||||
/* Transmit and Receive Interrupt Mask Register (TRIMR) */
|
||||
#define YUKON_TRIMR 0x0058
|
||||
|
||||
/* SMI Control Register (SMICR) */
|
||||
#define YUKON_SMICR 0x0080
|
||||
|
||||
#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11)
|
||||
#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6)
|
||||
#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */
|
||||
#define YU_SMICR_OP_READ 0x0020 /* opcode read */
|
||||
#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */
|
||||
#define YU_SMICR_READ_VALID 0x0010 /* read valid */
|
||||
#define YU_SMICR_BUSY 0x0008 /* busy (writing) */
|
||||
|
||||
/* SMI Data Register (SMIDR) */
|
||||
#define YUKON_SMIDR 0x0084
|
||||
|
||||
/* PHY Addres Register (PAR) */
|
||||
#define YUKON_PAR 0x0088
|
||||
|
||||
#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
|
||||
#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */
|
||||
|
||||
/* Receive status */
|
||||
#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */
|
||||
#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */
|
||||
#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */
|
||||
#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */
|
||||
#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */
|
||||
#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */
|
||||
#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */
|
||||
#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */
|
||||
#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */
|
||||
#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */
|
||||
#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */
|
||||
#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */
|
||||
#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */
|
||||
#define YU_RXSTAT_LENSHIFT 16
|
||||
|
||||
#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
|
||||
Reference in New Issue
Block a user