* Obviously, the i9xx family has changed the order of the PCI mappings, so we need
to take that into account. * Introduced INTEL_TYPE_FAMILY_MASK and INTEL_TYPE_GROUP_MASK to better differentiate the device type. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@18293 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -20,6 +20,8 @@
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#define VENDOR_ID_INTEL 0x8086
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#define INTEL_TYPE_FAMILY_MASK 0x0f
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#define INTEL_TYPE_GROUP_MASK 0xf0
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#define INTEL_TYPE_7xx 0x01
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#define INTEL_TYPE_8xx 0x02
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#define INTEL_TYPE_9xx 0x03
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@@ -297,7 +297,8 @@ intel_get_accelerant_device_info(accelerant_device_info *info)
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TRACE(("intel_get_accelerant_device_info()\n"));
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info->version = B_ACCELERANT_VERSION;
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strcpy(info->name, gInfo->shared_info->device_type == INTEL_TYPE_7xx
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strcpy(info->name,
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(gInfo->shared_info->device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_7xx
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? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
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strcpy(info->chipset, gInfo->shared_info->device_identifier);
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strcpy(info->serial_no, "None");
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@@ -140,7 +140,7 @@ determine_stolen_memory_size(intel_info &info)
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// TODO: test with different models!
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if (info.device_type & INTEL_TYPE_83x) {
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if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i830_LOCAL_MEMORY_ONLY:
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// TODO: determine its size!
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@@ -152,7 +152,7 @@ determine_stolen_memory_size(intel_info &info)
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memorySize *= 8;
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break;
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}
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} else if (info.device_type & INTEL_TYPE_85x) {
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} else if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_85x)) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i855_STOLEN_MEMORY_4M:
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memorySize *= 4;
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@@ -296,6 +296,15 @@ intel_extreme_init(intel_info &info)
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memset((void *)info.shared_info, 0, sizeof(intel_shared_info));
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int fbIndex = 0;
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int mmioIndex = 1;
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if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
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// for some reason Intel saw the need to change the order of the mappings
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// with the introduction of the i9xx family
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mmioIndex = 0;
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fbIndex = 2;
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}
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// evaluate driver settings, if any
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bool ignoreBIOSAllocated;
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@@ -333,7 +342,7 @@ intel_extreme_init(intel_info &info)
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AreaKeeper graphicsMapper;
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info.graphics_memory_area = graphicsMapper.Map("intel extreme graphics memory",
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(void *)info.pci->u.h0.base_registers[0],
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(void *)info.pci->u.h0.base_registers[fbIndex],
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totalSize, B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
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B_READ_AREA | B_WRITE_AREA, (void **)&info.graphics_memory);
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if (graphicsMapper.InitCheck() < B_OK) {
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@@ -341,7 +350,7 @@ intel_extreme_init(intel_info &info)
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dprintf(DEVICE_NAME ": enabling write combined mode failed.\n");
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info.graphics_memory_area = graphicsMapper.Map("intel extreme graphics memory",
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(void *)info.pci->u.h0.base_registers[0],
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(void *)info.pci->u.h0.base_registers[fbIndex],
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totalSize/*info.pci->u.h0.base_register_sizes[0]*/, B_ANY_KERNEL_BLOCK_ADDRESS,
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B_READ_AREA | B_WRITE_AREA, (void **)&info.graphics_memory);
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}
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@@ -354,8 +363,8 @@ intel_extreme_init(intel_info &info)
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AreaKeeper mmioMapper;
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info.registers_area = mmioMapper.Map("intel extreme mmio",
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(void *)info.pci->u.h0.base_registers[1],
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info.pci->u.h0.base_register_sizes[1],
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(void *)info.pci->u.h0.base_registers[mmioIndex],
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info.pci->u.h0.base_register_sizes[mmioIndex],
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B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA /*0*/, (void **)&info.registers);
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if (mmioMapper.InitCheck() < B_OK) {
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dprintf(DEVICE_NAME ": could not map memory I/O!\n");
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