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* redesign pretty much everything frame buffer related

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* don't resize the frame buffer after mapping it.. doesn't make sense
* add memory controller code and program the memory controller for r600
* remove unneeded frame_buffer_int
* don't malloc mc_info, waste of time
* fix scaler setting
* vramStart in mc should be 0... get vertical colored lines however when this
  this is set properly (everything in mc_info is the MC view of FB BAR)
  When vramStart is the FB physical address... i get proper video on some cards
  ... thoughts?


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42924 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-10-26 04:51:51 +00:00
parent 5dfed04886
commit 46af81655d
8 changed files with 195 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/radeon_hd/radeon_hd.h
+3 -4
View File
@@ -93,11 +93,10 @@ struct radeon_shared_info {
addr_t physical_status_page;
uint32 graphics_memory_size;
addr_t frame_buffer_phys; // card PCI BAR address of FB
area_id frame_buffer_area; // area of memory mapped FB
uint32 frame_buffer_int; // card internal FB location
uint32 frame_buffer_size; // card internal FB aperture size
uint8* frame_buffer; // virtual memory mapped FB
area_id frame_buffer_area; // area of memory mapped FB
addr_t frame_buffer_phys; // card PCI BAR address of FB
uint32 frame_buffer_size; // FB size mapped
bool has_edid;
edid1_info edid_info;
src/add-ons/accelerants/radeon_hd/accelerant.cpp
+2 -6
View File
@@ -110,8 +110,6 @@ init_common(int device, bool isClone)
memset(gInfo, 0, sizeof(accelerant_info));
gInfo->mc_info = (gpu_mc_info *)malloc(sizeof(gpu_mc_info));
// malloc memory for active display information
for (uint32 id = 0; id < MAX_DISPLAY; id++) {
gDisplay[id] = (display_info *)malloc(sizeof(display_info));
@@ -156,7 +154,6 @@ init_common(int device, bool isClone)
if (ioctl(device, RADEON_GET_PRIVATE_DATA, &data,
sizeof(radeon_get_private_data)) != 0) {
free(gInfo->mc_info);
free(gInfo);
return B_ERROR;
}
@@ -167,7 +164,6 @@ init_common(int device, bool isClone)
data.shared_info_area);
status_t status = sharedCloner.InitCheck();
if (status < B_OK) {
free(gInfo->mc_info);
free(gInfo);
TRACE("%s, failed to create shared area\n", __func__);
return status;
@@ -179,7 +175,6 @@ init_common(int device, bool isClone)
gInfo->shared_info->registers_area);
status = regsCloner.InitCheck();
if (status < B_OK) {
free(gInfo->mc_info);
free(gInfo);
TRACE("%s, failed to create mmio area\n", __func__);
return status;
@@ -219,7 +214,6 @@ uninit_common(void)
if (gInfo->is_clone)
close(gInfo->device);
free(gInfo->mc_info);
free(gInfo);
}
@@ -285,6 +279,8 @@ radeon_init_accelerant(int device)
// return status;
//}
radeon_gpu_mc_setup();
TRACE("%s done\n", __func__);
return B_OK;
}
src/add-ons/accelerants/radeon_hd/accelerant.h
+12 -3
View File
@@ -25,14 +25,22 @@
// Maximum displays (more then two requires AtomBIOS)
typedef struct {
struct gpu_state_info {
uint32 d1vga_control;
uint32 d2vga_control;
uint32 vga_render_control;
uint32 vga_hdp_control;
uint32 d1crtc_control;
uint32 d2crtc_control;
} gpu_mc_info;
};
struct mc_info {
bool valid;
uint64 vramStart;
uint64 vramEnd;
uint64 vramSize;
};
struct accelerant_info {
@@ -54,7 +62,8 @@ struct accelerant_info {
int device;
bool is_clone;
gpu_mc_info *mc_info; // used for last known mc state
struct gpu_state_info gpu_info; // used for last known gpu state
struct mc_info mc; // used for memory controller info
volatile uint32 dpms_mode; // current driver dpms mode
src/add-ons/accelerants/radeon_hd/display.cpp
+11 -10
View File
@@ -832,7 +832,7 @@ display_crtc_blank(uint8 crtcID, int command)
args.ucCRTC = crtcID;
args.ucBlanking = command;
// DEBUG: AMD red to know when we are blanked :)
// DEBUG: Radeon red to know when we are blanked :)
args.usBlackColorRCr = 255;
args.usBlackColorGY = 0;
args.usBlackColorBCb = 0;
@@ -851,7 +851,7 @@ display_crtc_scale(uint8 crtcID, display_mode *mode)
memset(&args, 0, sizeof(args));
args.ucScaler = crtcID;
args.ucEnable = ATOM_SCALER_EXPANSION;
args.ucEnable = ATOM_SCALER_DISABLE;
atom_execute_table(gAtomContext, index, (uint32*)&args);
}
@@ -942,25 +942,26 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode)
Write32(OUT, regs->vgaControl, 0);
uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int;
TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddressInt);
uint64 fbAddress = gInfo->mc.vramStart;
//uint64 fbAddress = gInfo->shared_info->frame_buffer_phys;
TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress);
if (info.device_chipset >= (RADEON_R700 | 0x70)) {
TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n",
__func__, (fbAddressInt >> 32) & 0xf);
__func__, (fbAddress >> 32) & 0xf);
Write32(OUT, regs->grphPrimarySurfaceAddrHigh,
(fbAddressInt >> 32) & 0xf);
(fbAddress >> 32) & 0xf);
Write32(OUT, regs->grphSecondarySurfaceAddrHigh,
(fbAddressInt >> 32) & 0xf);
(fbAddress >> 32) & 0xf);
}
TRACE("%s: Set SurfaceAddress: 0x%" B_PRIX32 "\n",
__func__, (fbAddressInt & 0xFFFFFFFF));
__func__, (fbAddress & 0xFFFFFFFF));
Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
if (info.device_chipset >= RADEON_R600) {
Write32(CRT, regs->grphControl, fbFormat);
src/add-ons/accelerants/radeon_hd/gpu.cpp
+110 -36
View File
@@ -165,12 +165,12 @@ void
radeon_gpu_mc_halt()
{
// Backup current memory controller state
gInfo->mc_info->d1vga_control = Read32(OUT, D1VGA_CONTROL);
gInfo->mc_info->d2vga_control = Read32(OUT, D2VGA_CONTROL);
gInfo->mc_info->vga_render_control = Read32(OUT, VGA_RENDER_CONTROL);
gInfo->mc_info->vga_hdp_control = Read32(OUT, VGA_HDP_CONTROL);
gInfo->mc_info->d1crtc_control = Read32(OUT, D1CRTC_CONTROL);
gInfo->mc_info->d2crtc_control = Read32(OUT, D2CRTC_CONTROL);
gInfo->gpu_info.d1vga_control = Read32(OUT, D1VGA_CONTROL);
gInfo->gpu_info.d2vga_control = Read32(OUT, D2VGA_CONTROL);
gInfo->gpu_info.vga_render_control = Read32(OUT, VGA_RENDER_CONTROL);
gInfo->gpu_info.vga_hdp_control = Read32(OUT, VGA_HDP_CONTROL);
gInfo->gpu_info.d1crtc_control = Read32(OUT, D1CRTC_CONTROL);
gInfo->gpu_info.d2crtc_control = Read32(OUT, D2CRTC_CONTROL);
// halt all memory controller actions
Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
@@ -189,27 +189,26 @@ radeon_gpu_mc_halt()
void
radeon_gpu_mc_resume()
{
// TODO: do surface addresses disappear on mc halt?
//Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->mc.vramStart);
Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->mc.vramStart);
Write32(OUT, D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->mc.vramStart);
Write32(OUT, D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->mc.vramStart);
Write32(OUT, VGA_MEMORY_BASE_ADDRESS, gInfo->mc.vramStart);
// Rnlock host access
Write32(OUT, VGA_HDP_CONTROL, gInfo->mc_info->vga_hdp_control);
// Unlock host access
Write32(OUT, VGA_HDP_CONTROL, gInfo->gpu_info.vga_hdp_control);
snooze(1);
// Restore memory controller state
Write32(OUT, D1VGA_CONTROL, gInfo->mc_info->d1vga_control);
Write32(OUT, D2VGA_CONTROL, gInfo->mc_info->d2vga_control);
Write32(OUT, D1VGA_CONTROL, gInfo->gpu_info.d1vga_control);
Write32(OUT, D2VGA_CONTROL, gInfo->gpu_info.d2vga_control);
Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, D1CRTC_CONTROL, gInfo->mc_info->d1crtc_control);
Write32(OUT, D2CRTC_CONTROL, gInfo->mc_info->d2crtc_control);
Write32(OUT, D1CRTC_CONTROL, gInfo->gpu_info.d1crtc_control);
Write32(OUT, D2CRTC_CONTROL, gInfo->gpu_info.d2crtc_control);
Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, VGA_RENDER_CONTROL, gInfo->mc_info->vga_render_control);
Write32(OUT, VGA_RENDER_CONTROL, gInfo->gpu_info.vga_render_control);
}
@@ -226,19 +225,22 @@ radeon_gpu_mc_idlecheck()
}
status_t
radeon_gpu_mc_setup()
static status_t
radeon_gpu_mc_setup_r600()
{
uint32 fb_location_int = gInfo->shared_info->frame_buffer_int;
uint32 fb_location = Read32(OUT, R600_MC_VM_FB_LOCATION);
uint16 fb_size = (fb_location >> 16) - (fb_location & 0xFFFF);
uint32 fb_location_tmp = fb_location_int >> 24;
fb_location_tmp |= (fb_location_tmp + fb_size) << 16;
uint32 fb_offset_tmp = (fb_location_int >> 8) & 0xff0000;
radeon_gpu_mc_halt();
// HDP initialization
uint32 i;
uint32 j;
for (i = 0, j = 0; i < 32; i++, j += 0x18) {
Write32(OUT, (0x2c14 + j), 0x00000000);
Write32(OUT, (0x2c18 + j), 0x00000000);
Write32(OUT, (0x2c1c + j), 0x00000000);
Write32(OUT, (0x2c20 + j), 0x00000000);
Write32(OUT, (0x2c24 + j), 0x00000000);
}
Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
// idle the memory controller
uint32 idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) {
TRACE("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n",
@@ -246,20 +248,92 @@ radeon_gpu_mc_setup()
return B_ERROR;
}
TRACE("%s: Setting frame buffer from 0x%" B_PRIX32
" to 0x%" B_PRIX32 " [size 0x%" B_PRIX16 "]\n",
__func__, fb_location, fb_location_tmp, fb_size);
// TODO: Memory Controller AGP
Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
gInfo->mc.vramStart >> 12);
Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
gInfo->mc.vramEnd >> 12);
// The MC Write32 will handle cards needing a special MC read/write register
Write32(MC, R600_MC_VM_FB_LOCATION, fb_location_tmp);
Write32(MC, R600_HDP_NONSURFACE_BASE, fb_offset_tmp);
Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
uint32 tmp = ((gInfo->mc.vramEnd >> 24) & 0xFFFF) << 16;
tmp |= ((gInfo->mc.vramStart >> 24) & 0xFFFF);
Write32(OUT, R6XX_MC_VM_FB_LOCATION, tmp);
Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->mc.vramStart >> 8));
Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7));
Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// TODO: AGP gtt start / end / agp base
// is AGP?
// WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
// WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
// WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
// else?
Write32(OUT, R600_MC_VM_AGP_BASE, 0);
Write32(OUT, R600_MC_VM_AGP_TOP, 0x0FFFFFFF);
Write32(OUT, R600_MC_VM_AGP_BOT, 0x0FFFFFFF);
idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) {
TRACE("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n",
__func__, idleState);
return B_ERROR;
}
radeon_gpu_mc_resume();
// disable render control
Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);
return B_OK;
}
void
radeon_gpu_mc_init()
{
radeon_shared_info &info = *gInfo->shared_info;
if (gInfo->shared_info->frame_buffer_size > 0)
gInfo->mc.valid = true;
// TODO: 0 should be correct here... but it gets me vertical stripes
//uint64 vramBase = 0;
uint64 vramBase = gInfo->shared_info->frame_buffer_phys;
if ((info.chipsetFlags & CHIP_IGP) != 0) {
vramBase = Read32(OUT, R6XX_MC_VM_FB_LOCATION) & 0xFFFF;
vramBase <<= 24;
}
gInfo->mc.vramStart = vramBase;
gInfo->mc.vramSize = gInfo->shared_info->frame_buffer_size * 1024;
gInfo->mc.vramEnd = (vramBase + gInfo->mc.vramSize) - 1;
}
status_t
radeon_gpu_mc_setup()
{
radeon_shared_info &info = *gInfo->shared_info;
radeon_gpu_mc_init();
// init video ram ranges for memory controler
if (gInfo->mc.valid != true) {
ERROR("%s: Memory Controller init failed.\n", __func__);
return B_ERROR;
}
TRACE("%s: vramStart: 0x%" B_PRIX64 ", vramEnd: 0x%" B_PRIX64 "\n",
__func__, gInfo->mc.vramStart, gInfo->mc.vramEnd);
if (info.device_chipset >= RADEON_R600)
return radeon_gpu_mc_setup_r600();
return B_ERROR;
}
status_t
radeon_gpu_irq_setup()
{
src/add-ons/accelerants/radeon_hd/gpu.h
+6
View File
@@ -12,6 +12,12 @@
#include "accelerant.h"
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
// GPU Control registers. These are combined as
// the registers exist on all models, some flags
// are different though and are commented as such
src/add-ons/accelerants/radeon_hd/mode.cpp
+15 -11
View File
@@ -209,16 +209,20 @@ radeon_set_display_mode(display_mode *mode)
}
// for debugging
TRACE("D1CRTC_STATUS Value: 0x%X\n", Read32(CRT, D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS));
TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D1CRTC_CONTROL));
TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D2CRTC_CONTROL));
TRACE("D1GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D1GRPH_ENABLE));
TRACE("D2GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D2GRPH_ENABLE));
TRACE("D1SCL_ENABLE Value: 0x%X\n", Read32(CRT, D1SCL_ENABLE));
TRACE("D2SCL_ENABLE Value: 0x%X\n", Read32(CRT, D2SCL_ENABLE));
TRACE("RV620_DACA_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACA_ENABLE));
TRACE("RV620_DACB_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACB_ENABLE));
TRACE("D1CRTC_STATUS Value: 0x%X\n", Read32(CRT, D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS));
TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D1CRTC_CONTROL));
TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D2CRTC_CONTROL));
TRACE("D1GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D1GRPH_ENABLE));
TRACE("D2GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D2GRPH_ENABLE));
TRACE("D1SCL_ENABLE Value: 0x%X\n", Read32(CRT, D1SCL_ENABLE));
TRACE("D2SCL_ENABLE Value: 0x%X\n", Read32(CRT, D2SCL_ENABLE));
TRACE("RV620_DACA_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACA_ENABLE));
TRACE("RV620_DACB_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACB_ENABLE));
TRACE("D1CRTC_BLANK_CONTROL Value: 0x%X\n",
Read32(CRT, D1CRTC_BLANK_CONTROL));
TRACE("D2CRTC_BLANK_CONTROL Value: 0x%X\n",
Read32(CRT, D2CRTC_BLANK_CONTROL));
return B_OK;
}
@@ -240,7 +244,7 @@ radeon_get_frame_buffer_config(frame_buffer_config *config)
TRACE("%s\n", __func__);
config->frame_buffer = gInfo->shared_info->frame_buffer;
config->frame_buffer_dma = (uint8 *)gInfo->shared_info->frame_buffer_phys;
config->frame_buffer_dma = (uint8*)gInfo->shared_info->frame_buffer_phys;
config->bytes_per_row = gInfo->shared_info->bytes_per_row;
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
+36 -44
View File
@@ -467,6 +467,7 @@ radeon_hd_init(radeon_info &info)
}
memset((void *)info.shared_info, 0, sizeof(radeon_shared_info));
sharedCreator.Detach();
// *** Map Memory mapped IO
AreaKeeper mmioMapper;
@@ -480,16 +481,44 @@ radeon_hd_init(radeon_info &info)
__func__, info.id);
return info.registers_area;
}
mmioMapper.Detach();
// *** Populate frame buffer information
if (info.shared_info->device_chipset >= RADEON_R1000) {
// R800+ has memory stored in MB
info.shared_info->graphics_memory_size
= read32(info.registers + R6XX_CONFIG_MEMSIZE) * 1024;
} else {
// R600-R700 has memory stored in bytes
info.shared_info->graphics_memory_size
= read32(info.registers + R6XX_CONFIG_MEMSIZE) / 1024;
}
uint32 barSize = info.pci->u.h0.base_register_sizes[RHD_FB_BAR] / 1024;
// if graphics memory is larger then PCI bar, just map bar
if (info.shared_info->graphics_memory_size > barSize) {
TRACE("%s: shrinking frame buffer to PCI bar...\n",
__func__);
info.shared_info->frame_buffer_size = barSize;
} else {
info.shared_info->frame_buffer_size
= info.shared_info->graphics_memory_size;
}
TRACE("%s: mapping a frame buffer of %" B_PRIu32 "MB out of %" B_PRIu32
"MB video ram\n", __func__, info.shared_info->frame_buffer_size / 1024,
info.shared_info->graphics_memory_size / 1024);
// *** Framebuffer mapping
AreaKeeper frambufferMapper;
info.framebuffer_area = frambufferMapper.Map("radeon hd framebuffer",
info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer",
(void *)info.pci->u.h0.base_registers[RHD_FB_BAR],
info.pci->u.h0.base_register_sizes[RHD_FB_BAR],
info.shared_info->frame_buffer_size * 1024,
B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void **)&info.shared_info->frame_buffer);
if (frambufferMapper.InitCheck() < B_OK) {
ERROR("%s: card(%ld): couldn't map framebuffer!\n",
ERROR("%s: card(%ld): couldn't map frame buffer!\n",
__func__, info.id);
return info.framebuffer_area;
}
@@ -498,10 +527,12 @@ radeon_hd_init(radeon_info &info)
vm_set_area_memory_type(info.framebuffer_area,
info.pci->u.h0.base_registers[RHD_FB_BAR], B_MTR_WC);
sharedCreator.Detach();
mmioMapper.Detach();
frambufferMapper.Detach();
info.shared_info->frame_buffer_area = info.framebuffer_area;
info.shared_info->frame_buffer_phys
= info.pci->u.h0.base_registers[RHD_FB_BAR];
// Pass common information to accelerant
info.shared_info->device_index = info.id;
info.shared_info->device_id = info.device_id;
@@ -512,12 +543,6 @@ radeon_hd_init(radeon_info &info)
info.shared_info->registers_area = info.registers_area;
strcpy(info.shared_info->device_identifier, info.device_identifier);
info.shared_info->frame_buffer_area = info.framebuffer_area;
info.shared_info->frame_buffer_phys
= info.pci->u.h0.base_registers[RHD_FB_BAR];
info.shared_info->frame_buffer_int
= read32(info.registers + R6XX_CONFIG_FB_BASE);
// *** AtomBIOS mapping
// First we try an active bios read
status_t biosStatus = radeon_hd_getbios(info);
@@ -584,39 +609,6 @@ radeon_hd_init(radeon_info &info)
info.shared_info->has_edid = false;
}
// *** Populate graphics_memory/aperture_size with KB
if (info.shared_info->device_chipset >= RADEON_R1000) {
// R800+ has memory stored in MB
info.shared_info->graphics_memory_size
= read32(info.registers + R6XX_CONFIG_MEMSIZE) * 1024;
info.shared_info->frame_buffer_size
= read32(info.registers + R6XX_CONFIG_APER_SIZE) * 1024;
} else {
// R600-R700 has memory stored in bytes
info.shared_info->graphics_memory_size
= read32(info.registers + R6XX_CONFIG_MEMSIZE) / 1024;
info.shared_info->frame_buffer_size
= read32(info.registers + R6XX_CONFIG_APER_SIZE) / 1024;
}
uint32 barSize = info.pci->u.h0.base_register_sizes[RHD_FB_BAR] / 1024;
// if graphics memory is larger then PCI bar, just map bar
if (info.shared_info->graphics_memory_size > barSize)
info.shared_info->frame_buffer_size = barSize;
else
info.shared_info->frame_buffer_size
= info.shared_info->graphics_memory_size;
int32 memory_size = info.shared_info->graphics_memory_size / 1024;
int32 frame_buffer_size = info.shared_info->frame_buffer_size / 1024;
TRACE("card(%ld): Found %ld MB memory on card\n", info.id,
memory_size);
TRACE("card(%ld): Frame buffer aperture size is %ld MB\n", info.id,
frame_buffer_size);
TRACE("card(%ld): %s completed successfully!\n", info.id, __func__);
return B_OK;
}