make math easier to read; fix chipset int length; additions to CardScale
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41561 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -106,7 +106,7 @@ struct radeon_shared_info {
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uint16 cursor_hot_x;
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uint16 cursor_hot_x;
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uint16 cursor_hot_y;
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uint16 cursor_hot_y;
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uint32 device_chipset;
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uint16 device_chipset;
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char device_identifier[32];
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char device_identifier[32];
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struct pll_info pll_info;
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struct pll_info pll_info;
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};
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};
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@@ -165,14 +165,8 @@ uninit_common(void)
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/*! Populate gRegister with device dependant register locations */
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/*! Populate gRegister with device dependant register locations */
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static status_t
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static status_t
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init_registers()
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init_registers(uint16 chipset)
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{
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{
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// gInfo should always be populated before running this
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if (gInfo == NULL)
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return B_ERROR;
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uint16_t chipset = gInfo->shared_info->device_chipset;
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if (chipset >= RADEON_R800) {
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if (chipset >= RADEON_R800) {
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gRegister->regOffsetCRT0 = EVERGREEN_CRTC0_REGISTER_OFFSET;
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gRegister->regOffsetCRT0 = EVERGREEN_CRTC0_REGISTER_OFFSET;
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gRegister->regOffsetCRT1 = EVERGREEN_CRTC1_REGISTER_OFFSET;
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gRegister->regOffsetCRT1 = EVERGREEN_CRTC1_REGISTER_OFFSET;
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@@ -233,15 +227,14 @@ radeon_init_accelerant(int device)
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if (status != B_OK)
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if (status != B_OK)
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return status;
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return status;
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status = init_registers();
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if (status != B_OK)
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return status;
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radeon_shared_info &info = *gInfo->shared_info;
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radeon_shared_info &info = *gInfo->shared_info;
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init_lock(&info.accelerant_lock, "radeon hd accelerant");
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init_lock(&info.accelerant_lock, "radeon hd accelerant");
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init_lock(&info.engine_lock, "radeon hd engine");
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init_lock(&info.engine_lock, "radeon hd engine");
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status = init_registers(info.device_chipset);
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if (status != B_OK)
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return status;
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status = create_mode_list();
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status = create_mode_list();
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if (status != B_OK) {
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if (status != B_OK) {
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@@ -136,7 +136,7 @@ CardBlankSet(int crtNumber, bool blank)
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int blackColorReg;
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int blackColorReg;
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int blankControlReg;
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int blankControlReg;
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if (crtNumber == 2) {
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if (crtNumber == 1) {
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blackColorReg = D2CRTC_BLACK_COLOR;
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blackColorReg = D2CRTC_BLACK_COLOR;
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blankControlReg = D2CRTC_BLANK_CONTROL;
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blankControlReg = D2CRTC_BLANK_CONTROL;
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} else {
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} else {
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@@ -287,7 +287,6 @@ CardModeScale(int crtNumber, display_mode *mode)
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uint16_t regOffset = (crtNumber == 0)
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uint16_t regOffset = (crtNumber == 0)
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? gRegister->regOffsetCRT0 : gRegister->regOffsetCRT1;
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? gRegister->regOffsetCRT0 : gRegister->regOffsetCRT1;
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/* D1Mode registers */
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write32(regOffset + gRegister->viewportSize,
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write32(regOffset + gRegister->viewportSize,
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mode->timing.v_display | (mode->timing.h_display << 16));
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mode->timing.v_display | (mode->timing.h_display << 16));
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write32(regOffset + gRegister->viewportStart, 0);
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write32(regOffset + gRegister->viewportStart, 0);
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@@ -300,6 +299,19 @@ CardModeScale(int crtNumber, display_mode *mode)
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write32(regOffset + D1SCL_ENABLE, 0);
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write32(regOffset + D1SCL_ENABLE, 0);
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write32(regOffset + D1SCL_TAP_CONTROL, 0);
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write32(regOffset + D1SCL_TAP_CONTROL, 0);
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write32(regOffset + D1MODE_CENTER, 2);
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write32(regOffset + D1MODE_CENTER, 2);
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write32(regOffset + D1SCL_UPDATE, 0);
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write32(regOffset + D1SCL_FLIP_CONTROL, 0);
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write32(regOffset + D1SCL_ENABLE, 1);
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write32(regOffset + D1SCL_HVSCALE, 0x00010001);
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write32(regOffset + D1SCL_TAP_CONTROL, 0x00000101);
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write32(regOffset + D1SCL_HFILTER, 0x00030100);
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write32(regOffset + D1SCL_VFILTER, 0x00030100);
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write32(regOffset + D1SCL_DITHER, 0x00001010);
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}
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}
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@@ -38,7 +38,7 @@
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// list of supported devices
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// list of supported devices
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const struct supported_device {
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const struct supported_device {
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uint32 device_id;
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uint32 device_id;
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int32 chipset;
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uint16 chipset;
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const char* name;
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const char* name;
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} kSupportedDevices[] = {
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} kSupportedDevices[] = {
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// R600 series (HD24xx - HD42xx)
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// R600 series (HD24xx - HD42xx)
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@@ -113,21 +113,23 @@ radeon_hd_init(radeon_info &info)
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if (info.shared_info->device_chipset >= RADEON_R800) {
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if (info.shared_info->device_chipset >= RADEON_R800) {
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// R800+ has memory stored in MB
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// R800+ has memory stored in MB
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info.shared_info->graphics_memory_size
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info.shared_info->graphics_memory_size
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= read32(info.registers + R6XX_CONFIG_MEMSIZE) << 10;
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= read32(info.registers + R6XX_CONFIG_MEMSIZE) / 1024;
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info.shared_info->graphics_aperture_size
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info.shared_info->graphics_aperture_size
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= read32(info.registers + R6XX_CONFIG_APER_SIZE) << 10;
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= read32(info.registers + R6XX_CONFIG_APER_SIZE) / 1024;
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} else {
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} else {
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// R600-R700 has memory stored in bytes
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// R600-R700 has memory stored in bytes
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info.shared_info->graphics_memory_size
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info.shared_info->graphics_memory_size
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= read32(info.registers + R6XX_CONFIG_MEMSIZE) >> 10;
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= read32(info.registers + R6XX_CONFIG_MEMSIZE) * 1024;
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info.shared_info->graphics_aperture_size
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info.shared_info->graphics_aperture_size
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= read32(info.registers + R6XX_CONFIG_APER_SIZE) >> 10;
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= read32(info.registers + R6XX_CONFIG_APER_SIZE) * 1024;
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}
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}
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int32 memory_size = info.shared_info->graphics_memory_size * 1024;
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int32 aperture_size = info.shared_info->graphics_aperture_size * 1024;
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TRACE("card(%ld): found %ld MB memory on card.\n", info.id,
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TRACE("card(%ld): found %ld MB memory on card.\n", info.id,
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info.shared_info->graphics_memory_size >> 10);
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memory_size);
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TRACE("card(%ld): found %ld MB aperture on card.\n", info.id,
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TRACE("card(%ld): found %ld MB aperture on card.\n", info.id,
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info.shared_info->graphics_aperture_size >> 10);
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aperture_size);
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// if there are more then 512MB memory on the card, only map
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// if there are more then 512MB memory on the card, only map
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// the aperture size to prevent overflow of gart
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// the aperture size to prevent overflow of gart
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